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URL https://opencores.org/ocsvn/apbtoaes128/apbtoaes128/trunk

Subversion Repositories apbtoaes128

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    from Rev 17 to Rev 18
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Rev 17 → Rev 18

/trunk/work/README
37,3 → 37,9
 
10 - 02 - 2015
Corrected ECB / CBC / CTR Key gen CR .
 
 
 
05 - 04 - 2015
 
I see the trunk when you try to compile the env it give a error, so if you want compile i recommend you put a folder from icarus verilog on same folder where env is it. i tried fix it to make more simple.
/trunk/pli/random/aes_bfm_sufle.h
77,15 → 77,376
{
 
vpiHandle PRESETn = vpi_handle_by_name("AES_GLADIC_tb.PRESETn", NULL);
vpiHandle i = vpi_handle_by_name("AES_GLADIC_tb.i", NULL);
vpiHandle PWDATA = vpi_handle_by_name("AES_GLADIC_tb.PWDATA", NULL);
vpiHandle PENABLE = vpi_handle_by_name("AES_GLADIC_tb.PENABLE", NULL);
vpiHandle PSEL = vpi_handle_by_name("AES_GLADIC_tb.PSEL", NULL);
vpiHandle PWRITE = vpi_handle_by_name("AES_GLADIC_tb.PWRITE", NULL);
vpiHandle PADDR = vpi_handle_by_name("AES_GLADIC_tb.PADDR", NULL);
vpiHandle PRDATA = vpi_handle_by_name("AES_GLADIC_tb.PRDATA", NULL);
vpiHandle PREADY = vpi_handle_by_name("AES_GLADIC_tb.PREADY", NULL);
vpiHandle PSLVERR = vpi_handle_by_name("AES_GLADIC_tb.PSLVERR", NULL);
vpiHandle int_ccf = vpi_handle_by_name("AES_GLADIC_tb.int_ccf", NULL);
vpiHandle int_err = vpi_handle_by_name("AES_GLADIC_tb.int_err", NULL);
vpiHandle dma_req_wr = vpi_handle_by_name("AES_GLADIC_tb.dma_req_wr", NULL);
vpiHandle dma_req_rd = vpi_handle_by_name("AES_GLADIC_tb.dma_req_rd", NULL);
 
v_generate.format=vpiIntVal;
vpi_get_value(PRESETn, &v_generate);
std::random_device rd;
std::uniform_int_distribution<long int> data_in(0,4294967295);
 
std::uniform_int_distribution<long int> register_config(0,232);
 
v_ecb.format=vpiIntVal;
 
vpi_get_value(PRESETn, &v_ecb);
 
if(type_bfm == SUFLE_TEST && v_generate.value.integer == 1)
{
 
switch(STATE)
{
 
case IDLE:
 
if(PACKETS_GENERATED >= MAX_ITERATIONS)
{
 
STATE = IDLE;
type_bfm = 0;
 
}else
{
STATE = WRITE;
counter = 0;
 
v_ecb.value.integer = 0;
vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
v_ecb.value.integer = vector_address[0];
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
v_ecb.value.integer = 0;
vpi_put_value(PWDATA, &v_ecb, NULL, vpiNoDelay);
 
v_ecb.value.integer = 1;
vpi_put_value(PWRITE, &v_ecb, NULL, vpiNoDelay);
 
v_ecb.value.integer = 1;
vpi_put_value(PSEL, &v_ecb, NULL, vpiNoDelay);
}
 
break;
case WRITE:
 
v_ecb.value.integer = 1;
vpi_put_value(PSEL, &v_ecb, NULL, vpiNoDelay);
if(counter == 0)
{
counter_write++;
counter++;
 
v_ecb.value.integer = 1;
vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
 
 
}else if(counter == 1)
{
 
v_ecb.value.integer = 0;
vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
 
t_ecb.type = vpiScaledRealTime;
t_ecb.real = 0;
v_ecb.format=vpiIntVal;
 
if(counter_write < 9)
{
v_ecb.value.integer = vector_address[counter_write];
vpi_put_value(PADDR, &v_ecb, &t_ecb, vpiTransportDelay);
v_ecb.value.integer = data_in(rd);
vpi_put_value(PWDATA, &v_ecb, &t_ecb, vpiTransportDelay);
 
}else if(counter_write == 9)
{
v_wr.value.integer = ADDR_AES_CR;
vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
last_cr = vector_CR[register_config(rd)];
v_wr.value.integer = last_cr;
vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
 
}else if(counter_write > 9 && counter_write < 14)
{
 
v_ecb.value.integer = ADDR_AES_DINR;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
v_ecb.value.integer = data_in(rd);
vpi_put_value(PWDATA, &v_ecb, &t_ecb, vpiTransportDelay);
}
 
counter=0;
 
 
}
 
 
if(counter_write == 14)
{
counter_write = 0;
STATE = WAIT_SR;
}
 
break;
case WRITE_DINR:
 
 
v_ecb.value.integer = ADDR_AES_DINR;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
 
if(counter == 0)
{
 
 
 
counter++;
counter_write++;
 
v_ecb.value.integer = 1;
vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
 
 
}else if(counter == 1)
{
v_ecb.value.integer = 0;
vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
 
v_ecb.value.integer = ADDR_AES_DINR;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
v_ecb.value.integer = data_in(rd);
vpi_put_value(PWDATA, &v_ecb, &t_ecb, vpiTransportDelay);
 
counter=0;
}
 
if(counter_write == 4)
{
counter_write = 0;
STATE = WAIT_SR;
}
 
 
 
break;
case WAIT_SR:
 
v_ecb.value.integer = ADDR_AES_SR;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
v_ecb.value.integer = 0;
vpi_put_value(PWRITE, &v_ecb, NULL, vpiNoDelay);
 
 
if(counter == 0)
{
 
counter++;
 
v_ecb.value.integer = 1;
vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
 
 
v_ecb.value.integer = 0;
vpi_get_value(PRDATA,&v_ecb);
 
 
if(v_ecb.value.integer == 1)
{
STATE = READ_DOUTR;
}
 
 
}else if(counter == 1)
{
v_ecb.value.integer = 0;
vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
 
counter=0;
}
 
 
break;
case READ_DOUTR:
 
if(counter == 0)
{
 
v_ecb.value.integer = 1;
vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
 
counter_read++;
counter++;
 
 
 
}else if(counter == 1)
{
v_ecb.value.integer = 0;
vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
 
 
if(counter_read < 4)
{
 
v_ecb.value.integer = ADDR_AES_DOUTR;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
}
 
 
if(counter_read == 4)
{
 
v_ecb.value.integer = ADDR_AES_KEYR3;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
}
 
 
if(counter_read == 5)
{
 
v_ecb.value.integer = ADDR_AES_KEYR2;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
}
 
 
 
if(counter_read == 6)
{
 
v_ecb.value.integer = ADDR_AES_KEYR1;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
}
 
 
if(counter_read == 7)
{
 
v_ecb.value.integer = ADDR_AES_KEYR0;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
}
 
 
if(counter_read == 8)
{
 
v_ecb.value.integer = ADDR_AES_IVR3;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
}
 
 
if(counter_read == 9)
{
 
v_ecb.value.integer = ADDR_AES_IVR2;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
}
 
 
 
if(counter_read == 10)
{
 
v_ecb.value.integer = ADDR_AES_IVR1;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
}
 
 
if(counter_read == 11)
{
 
v_ecb.value.integer = ADDR_AES_IVR0;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
}
 
 
counter = 0;
}
 
if(counter_read == 12)
{
STATE = RESET_SR;
counter_read = 0;
}
 
 
break;
case RESET_SR:
 
v_ecb.value.integer = 1;
vpi_put_value(PWRITE, &v_ecb, NULL, vpiNoDelay);
 
v_ecb.value.integer = 1;
vpi_put_value(PSEL, &v_ecb, NULL, vpiNoDelay);
 
v_ecb.value.integer = 0;
vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
 
v_ecb.value.integer = 128 + last_cr;
vpi_put_value(PWDATA, &v_ecb, NULL, vpiNoDelay);
 
 
if(counter == 0)
{
 
counter_write++;
counter++;
 
v_ecb.value.integer = 1;
vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
 
}else if(counter == 1)
{
 
v_ecb.value.integer = 0;
vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
counter=0;
 
}
 
if(counter_write == 1)
{
counter_write = 0;
counter=1;
 
if( counter_sufle == MAX_ITERATION_PER_SUFLE)
{
PACKETS_GENERATED = PACKETS_GENERATED + 1;
counter_sufle = 0 ;
STATE =IDLE;
}else
{
counter_sufle++;
STATE =WRITE_DINR;
}
}
 
break;
 
}
 
 
}
 
return 0;
/trunk/pli/aes_init.h
454,8 → 454,12
vector_address[8]= ADDR_AES_IVR0;
vector_address[9]= ADDR_AES_SR;
 
/*
THIS IS TO BE USED LIKE A BACKUP VALUE FROM LAST CR GENERATED ON SUFLE
*/
last_cr = 0 ;
counter_sufle = 0 ;
 
 
v_initial.format=vpiIntVal;
 
v_initial.value.integer = 0;
/trunk/pli/env_aes.c
73,7 → 73,7
////
///////////////////////////////////////////////////////////////////
 
#include "../../iverilog/vpi_user.h"
#include "../iverilog/vpi_user.h"
//#include <vpi_user.h>
#include <iostream>
#include <random>
128,6 → 128,10
 
unsigned long int O;
 
unsigned long int last_cr;
 
int counter_sufle;
 
int type_bfm;
 
int STATE;
260,8 → 264,10
 
 
/*MAX PACKETS GENERATION*/
#define MAX_ITERATIONS 3
#define MAX_ITERATIONS 4
 
#define MAX_ITERATION_PER_SUFLE 6
 
/*MAX RESET GENERATION */
#define MAX_RESET_TIMES 4
 
297,7 → 303,7
unsigned char KEY_FIPS_CBC_DERIVATED[] = {0xD0,0x14,0xF9,0xA8,0xC9,0xEE,0x25,0x89,0xE1,0x3F,0x0C,0xC8,0xB6,0x63,0x0C,0xA6};
 
 
unsigned char TEXT_CBC_FIPS_DERIVATED[] = {0x76,0x49,0xAB,0xAC,0x81,0x19,0xB2,0x46,0xCE,0xE9,0x8E,0x9B,0x12,0xE9,0x19,0x7D};
unsigned char TEXT_CBC_FIPS_DERIVATED[] = {0x76,0x49,0xAB,0xAC,0x81,0x19,0xB2,0x46,0xCE,0xE9,0x8E,0x9B,0x12,0xE9,0x19,0x7D};
unsigned char TEXT_CBC_FIPS_DATATYPE_T01_DERIVATED[] = {0xAB,0xAC,0x76,0x49,0xB2,0x46,0x81,0x19,0x8E,0x9B,0xCE,0xE9,0x19,0x7D,0x12,0xE9};
unsigned char TEXT_CBC_FIPS_DATATYPE_T02_DERIVATED[] = {0xCD,0x29,0x94,0xFC,0xF6,0xAE,0x27,0x96,0x7D,0xA4,0x45,0xFA,0x28,0x9E,0xE8,0x39};
unsigned char TEXT_CBC_FIPS_DATATYPE_T03_DERIVATED[] = {0x7F,0x59,0xFD,0x0E,0x0F,0x88,0xD0,0x32,0x7F,0x75,0x0E,0xB5,0x07,0x85,0xC3,0x4E};
/trunk/pli/aes_monitor.h
4056,11 → 4056,16
 
 
 
}//counter == 12
else
}else if(type_bfm == SUFLE_TEST && counter_monitor == 12)
{
 
 
//printf("CONFIGURATION REGISTER %d \n",I);
//printf("KEY %X %X %X %X \n",A,B,C,D);
//printf("IVR %X %X %X %X \n",E,F,G,H);
//printf("TEXT CYPHER %X %X %X %X \n",J,L,M,N);
 
 
}
 
}
/trunk/pli/aes_bfm_generate.h
85,7 → 85,7
if(v_generate.value.integer == 1)
{
 
FIPS_ENABLE =FIPS;
FIPS_ENABLE =RANDOM_DATA;
DATATYPE = TYPE_00;
 
// type_bfm = AES_WR_ONLY;
92,7 → 92,7
// type_bfm = AES_WR_ERROR_DINR_ONLY;
// type_bfm = AES_WR_ERROR_DOUTR_ONLY;
 
type_bfm = ECB_ENCRYPTION;
// type_bfm = ECB_ENCRYPTION;
// type_bfm = ECB_DECRYPTION;
// type_bfm = ECB_KEY_GEN;
// type_bfm = ECB_DERIVATION_DECRYPTION;
138,7 → 138,7
// type_bfm = CTR_KEY_GEN_CCFIE;
// type_bfm = CTR_DERIVATION_DECRYPTION_CCFIE;
 
// type_bfm = SUFLE_TEST;
type_bfm = SUFLE_TEST;
 
 
if(PACKETS_GENERATED == MAX_ITERATIONS)
/trunk/doc/AES_GLADIC_IP_BRIF.pdf Cannot display: file marked as a binary type. svn:mime-type = application/pdf

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