URL
https://opencores.org/ocsvn/artificial_neural_network/artificial_neural_network/trunk
Subversion Repositories artificial_neural_network
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- This comparison shows the changes necessary to convert path
/artificial_neural_network/trunk/ANN_kernel/RTL_VHDL_files
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/activation_function.vhd
21,7 → 21,6
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
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entity activation_function is |
generic |
( |
/adder_tree.vhd
46,6 → 46,29
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architecture Behavioral of adder_tree is |
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component adder_tree is |
generic |
( |
NumIn : integer := 9; -- Number of inputs |
Nbit : integer := 12 -- Bit width of the input data |
); |
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port |
( |
-- Input ports |
reset : in std_logic; |
clk : in std_logic; |
en : in std_logic; -- Enable |
inputs : in std_logic_vector((Nbit*NumIn)-1 downto 0); -- Input data |
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-- Output ports |
en_out : out std_logic; -- Output enable (output data validation) |
output : out std_logic_vector(Nbit-1 downto 0) -- Output of the tree adder |
); |
end component; |
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constant NumIn2 : integer := NumIn/2; -- Number of imputs of the next adder tree layer |
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signal next_en : std_logic := '0'; -- Next adder tree layer enable |
107,7 → 130,7
recursion: |
if (NumIn > 2) generate |
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sub_adder_tree: entity work.adder_tree |
sub_adder_tree: adder_tree |
generic map |
( |
NumIn => (NumIn2)+(NumIn mod 2), |