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URL https://opencores.org/ocsvn/astron_diagnostics/astron_diagnostics/trunk

Subversion Repositories astron_diagnostics

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  • This comparison shows the changes necessary to convert path 
    /astron_diagnostics
    from Rev 3 to Rev 4
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  •

Rev 3 → Rev 4

/trunk/diag_block_gen_reg.vhd
19,11 → 19,11
-------------------------------------------------------------------------------
library IEEE, common_pkg_lib, common_ram_lib, common_components_lib;
library IEEE, common_pkg_lib, astron_ram_lib, common_components_lib;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
use common_pkg_lib.common_pkg.ALL;
use common_ram_lib.common_ram_pkg.ALL;
use astron_ram_lib.common_ram_pkg.ALL;
use work.diag_pkg.ALL;
 
entity diag_block_gen_reg is
/trunk/diag_data_buffer.vhd
42,17 → 42,17
-- power of 2 multiple of 32b the user can enforce using splitting the data
-- a c_word_w parts.
 
LIBRARY IEEE, common_pkg_lib, mm_lib, technology_lib, common_ram_lib, common_counter_lib, common_components_lib;
LIBRARY IEEE, common_pkg_lib, astron_mm_lib, astron_ram_lib, astron_counter_lib, common_components_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE common_ram_lib.common_ram_pkg.ALL;
USE astron_ram_lib.common_ram_pkg.ALL;
USE work.diag_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY diag_data_buffer IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
g_data_w : NATURAL := 32;
g_nof_data : NATURAL := 1024;
g_use_in_sync : BOOLEAN := FALSE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
190,7 → 190,7
END IF;
END PROCESS;
 
u_buf : ENTITY common_ram_lib.common_ram_crw_crw_ratio
u_buf : ENTITY astron_ram_lib.common_ram_crw_crw_ratio
GENERIC MAP (
g_technology => g_technology,
g_ram_a => c_buf_mm,
219,7 → 219,7
rd_val_b => OPEN
);
 
u_reg : ENTITY mm_lib.common_reg_r_w_dc
u_reg : ENTITY astron_mm_lib.common_reg_r_w_dc
GENERIC MAP (
g_reg => c_reg
)
243,7 → 243,7
 
reg_slv <= word_cnt & sync_cnt;
 
u_word_cnt : ENTITY common_counter_lib.common_counter
u_word_cnt : ENTITY astron_counter_lib.common_counter
PORT MAP (
rst => st_rst,
clk => st_clk,
252,7 → 252,7
count => word_cnt
);
 
u_sync_cnt : ENTITY common_counter_lib.common_counter
u_sync_cnt : ENTITY astron_counter_lib.common_counter
PORT MAP (
rst => st_rst,
clk => st_clk,
/trunk/diag_rx_seq.vhd
87,7 → 87,7
-- during the sequence, to determine all g_nof_steps next values are correct
-- in case they occur.
 
LIBRARY IEEE, common_pkg_lib, common_components_lib, common_counter_lib;
LIBRARY IEEE, common_pkg_lib, common_components_lib, astron_counter_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_pkg_lib.common_pkg.ALL;
419,7 → 419,7
------------------------------------------------------------------------------
-- Count number of valid input data
------------------------------------------------------------------------------
u_common_counter : ENTITY common_counter_lib.common_counter
u_common_counter : ENTITY astron_counter_lib.common_counter
GENERIC MAP (
g_latency => 1, -- default 1 for registered count output, use 0 for immediate combinatorial count output
g_width => g_cnt_w
/trunk/diag_tx_seq.vhd
18,7 → 18,7
--
--------------------------------------------------------------------------------
LIBRARY IEEE, common_pkg_lib, common_counter_lib;
LIBRARY IEEE, common_pkg_lib, astron_counter_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_pkg_lib.common_pkg.ALL;
134,7 → 134,7
nxt_out_val <= diag_en AND diag_req; -- 'en' for entire test on/off, 'req' for dynamic invalid gaps in the stream
-- Count number of valid output data
u_common_counter : ENTITY common_counter_lib.common_counter
u_common_counter : ENTITY astron_counter_lib.common_counter
GENERIC MAP (
g_latency => g_latency, -- default 1 for registered count output, use 0 for immediate combinatorial count output
g_width => g_cnt_w
/trunk/hdllib.cfg
1,6 → 1,6
hdl_lib_name = diag
hdl_library_clause_name = diag_lib
hdl_lib_uses_synth = common_pkg dp_pkg dp_components common_components common_ram common_counter common_ram dp_mux technology mm dp_pipeline #common_mult
hdl_lib_name = astron_diagnostics
hdl_library_clause_name = astron_diagnostics_lib
hdl_lib_uses_synth = common_pkg dp_pkg dp_components common_components astron_ram astron_counter astron_ram astron_multiplexer astron_mm astron_pipeline
hdl_lib_uses_sim =
hdl_lib_technology =
 
60,7 → 60,7
 
[modelsim_project_file]
modelsim_copy_files =
src/data data
# src/data data
 
 
[quartus_project_file]
/trunk/mms_diag_block_gen.vhd
92,18 → 92,18
-- . A nice new feature would be to support a BG burst of N blocks.
 
 
LIBRARY IEEE, common_pkg_lib, common_ram_lib, technology_lib, dp_pkg_lib, dp_components_lib, dp_mux_lib, mm_lib;
LIBRARY IEEE, common_pkg_lib, astron_ram_lib, dp_pkg_lib, dp_components_lib, astron_multiplexer_lib, astron_mm_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE common_ram_lib.common_ram_pkg.ALL;
USE astron_ram_lib.common_ram_pkg.ALL;
USE dp_pkg_lib.dp_stream_pkg.ALL;
USE work.diag_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY mms_diag_block_gen IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
-- Generate configurations
g_use_usr_input : BOOLEAN := FALSE;
g_use_bg : BOOLEAN := TRUE;
218,7 → 218,7
);
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux_bg_data : ENTITY mm_lib.common_mem_mux
u_mem_mux_bg_data : ENTITY astron_mm_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_streams,
g_mult_addr_w => g_buf_addr_w
240,7 → 240,7
END GENERATE;
gen_buffer_ram : IF g_use_bg_buffer_ram=TRUE GENERATE
u_buffer_ram : ENTITY common_ram_lib.common_ram_crw_crw
u_buffer_ram : ENTITY astron_ram_lib.common_ram_crw_crw
GENERIC MAP (
g_technology => g_technology,
g_ram => c_buf,
336,7 → 336,7
mux_snk_in_2arr_2(I)(0) <= usr_xflow_src_out_arr(I);
mux_snk_in_2arr_2(I)(1) <= bg_src_out_arr(I);
u_dp_mux : ENTITY dp_mux_lib.dp_mux
u_dp_mux : ENTITY astron_multiplexer_lib.dp_mux
GENERIC MAP (
g_technology => g_technology,
-- MUX
/trunk/mms_diag_data_buffer.vhd
56,18 → 56,18
-- detects an error. By delaying the trigger somewhat it the DB can then
-- capture some data before and after the trigger event.
 
LIBRARY IEEE, common_pkg_lib, technology_lib, dp_pkg_lib, common_ram_lib, mm_lib;
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, astron_ram_lib, astron_mm_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE common_ram_lib.common_ram_pkg.ALL;
USE astron_ram_lib.common_ram_pkg.ALL;
USE dp_pkg_lib.dp_stream_pkg.ALL;
USE work.diag_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
ENTITY mms_diag_data_buffer IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_technology : NATURAL := 0;
-- Generate configurations
g_use_db : BOOLEAN := TRUE;
g_use_rx_seq : BOOLEAN := FALSE;
132,7 → 132,7
gen_db : IF g_use_db=TRUE GENERATE
-- Combine the internal array of mm interfaces for the data_buf to one array that is connected to the port of the MM bus
u_mem_mux_data_buf : ENTITY mm_lib.common_mem_mux
u_mem_mux_data_buf : ENTITY astron_mm_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_streams,
g_mult_addr_w => c_buf_adr_w
144,7 → 144,7
miso_arr => ram_data_buf_miso_arr
);
u_mem_mux_reg : ENTITY mm_lib.common_mem_mux
u_mem_mux_reg : ENTITY astron_mm_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_streams,
g_mult_addr_w => c_reg_adr_w
/trunk/mms_diag_rx_seq.vhd
92,12 → 92,12
-- c_diag_seq_rx_reg_nof_steps = 4 MM step registers define the allowed
-- COUNTER increment values.
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, mm_lib, common_ram_lib;
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, astron_mm_lib, astron_ram_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE common_ram_lib.common_ram_pkg.ALL;
USE mm_lib.common_field_pkg.ALL;
USE astron_ram_lib.common_ram_pkg.ALL;
USE astron_mm_lib.common_field_pkg.ALL;
USE dp_pkg_lib.dp_stream_pkg.ALL;
USE work.diag_pkg.ALL;
 
269,7 → 269,7
stat_reg_arr(I)(4*c_word_w-1 DOWNTO 3*c_word_w) <= RESIZE_UVEC(rx_sample_arr(I), c_word_w); -- address 3: read valid sample per stream
END PROCESS;
u_reg : ENTITY mm_lib.common_reg_r_w_dc
u_reg : ENTITY astron_mm_lib.common_reg_r_w_dc
GENERIC MAP (
g_cross_clock_domain => TRUE,
g_readback => FALSE, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
293,7 → 293,7
END GENERATE;
 
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux : ENTITY mm_lib.common_mem_mux
u_mem_mux : ENTITY astron_mm_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_streams,
g_mult_addr_w => c_mm_reg.adr_w
/trunk/mms_diag_tx_seq.vhd
148,11 → 148,11
-- yields a different CNTR value than reading 2**(g_seq_dat_w+1).
 
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, dp_pipeline_lib, common_ram_lib, mm_lib; -- init value for out_dat when diag_en = '0'
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, astron_pipeline_lib, astron_ram_lib, astron_mm_lib; -- init value for out_dat when diag_en = '0'
USE IEEE.std_logic_1164.ALL;
USE common_pkg_lib.common_pkg.ALL;
USE common_ram_lib.common_ram_pkg.ALL;
USE mm_lib.common_field_pkg.ALL;
USE astron_ram_lib.common_ram_pkg.ALL;
USE astron_mm_lib.common_field_pkg.ALL;
USE dp_pkg_lib.dp_stream_pkg.ALL;
USE work.diag_pkg.ALL;
 
290,7 → 290,7
stat_reg_arr(I)(3*c_word_w-1 DOWNTO 2*c_word_w) <= tx_cnt_arr(I); -- address 2: read tx_cnt
END PROCESS;
 
u_reg : ENTITY mm_lib.common_reg_r_w_dc
u_reg : ENTITY astron_mm_lib.common_reg_r_w_dc
GENERIC MAP (
g_cross_clock_domain => TRUE,
g_readback => FALSE, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
314,7 → 314,7
END GENERATE;
 
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux : ENTITY mm_lib.common_mem_mux
u_mem_mux : ENTITY astron_mm_lib.common_mem_mux
GENERIC MAP (
g_broadcast => g_mm_broadcast,
g_nof_mosi => g_nof_streams,
367,7 → 367,7
END PROCESS;
 
-- Pipeline the streams by 1 to register the mux_seq_src_out_arr data to ease timing closure given that c_tx_seq_latency=0
u_dp_pipeline_arr : ENTITY dp_pipeline_lib.dp_pipeline_arr
u_dp_pipeline_arr : ENTITY astron_pipeline_lib.dp_pipeline_arr
GENERIC MAP (
g_nof_streams => g_nof_streams
)

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