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URL https://opencores.org/ocsvn/axi_master/axi_master/trunk

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  • This comparison shows the changes necessary to convert path 
    /axi_master/trunk/src/base
    from Rev 17 to Rev 18
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  •

Rev 17 → Rev 18

/ic_wdata.v
37,28 → 37,28
 
parameter STRB_BITS = DATA_BITS/8;
input clk;
input reset;
input clk;
input reset;
port MMX_AWGROUP_IC_AXI_CMD;
port MMX_WGROUP_IC_AXI_W;
revport SSX_WGROUP_IC_AXI_W;
input SSX_AWVALID;
input SSX_AWREADY;
input [MSTR_BITS-1:0] SSX_AWMSTR;
port MMX_AWGROUP_IC_AXI_CMD;
port MMX_WGROUP_IC_AXI_W;
revport SSX_WGROUP_IC_AXI_W;
input SSX_AWVALID;
input SSX_AWREADY;
input [MSTR_BITS-1:0] SSX_AWMSTR;
 
 
parameter WBUS_WIDTH = GONCAT(GROUP_IC_AXI_W.IN.WIDTH +);
parameter WBUS_WIDTH = GONCAT(GROUP_IC_AXI_W.IN.WIDTH +);
 
wire [WBUS_WIDTH-1:0] SSX_WBUS;
wire [WBUS_WIDTH-1:0] SSX_WBUS;
wire [WBUS_WIDTH-1:0] MMX_WBUS;
wire [WBUS_WIDTH-1:0] MMX_WBUS;
wire [SLV_BITS-1:0] MMX_WSLV;
wire MMX_WOK;
wire [SLV_BITS-1:0] MMX_WSLV;
wire MMX_WOK;
wire SSX_MMX;
wire SSX_MMX;
 
 
78,12 → 78,12
.MMX_WLAST(MMX_WLAST),
.MMX_WSLV(MMX_WSLV),
.MMX_WOK(MMX_WOK),
.SSX_AWVALID(SSX_AWVALID),
.SSX_AWREADY(SSX_AWREADY),
.SSX_AWVALID(SSX_AWVALID),
.SSX_AWREADY(SSX_AWREADY),
.SSX_AWMSTR(SSX_AWMSTR),
.SSX_WVALID(SSX_WVALID),
.SSX_WREADY(SSX_WREADY),
.SSX_WLAST(SSX_WLAST),
.SSX_WVALID(SSX_WVALID),
.SSX_WREADY(SSX_WREADY),
.SSX_WLAST(SSX_WLAST),
STOMP ,
);
 
/def_ic.txt
38,8 → 38,9
SWAP.USER MASTER_NUM 3 ##number of masters
SWAP.USER SLAVE_NUM 6 ##number of slaves
 
SWAP.USER CMD_DEPTH 8 ##AXI command depth for read and write
 
SWAP.USER CMD_DEPTH 4 ##AXI master command depth for read and write
SWAP.USER SLV_DEPTH 8 ##AXI slave command depth for read and write
SWAP.USER DATA_BITS 64 ##AXI data bits
SWAP.USER ADDR_BITS 32 ##AXI address bits
 
/axi_master_stall.v
26,166 → 26,166
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_stall.v
 
INCLUDE def_axi_master.txt
module PREFIX_stall(PORTS);
`include "prgen_rand.v"
input clk;
input reset;
 
input rd_hold;
input wr_hold;
input ARVALID_pre;
input RREADY_pre;
input AWVALID_pre;
input WVALID_pre;
input BREADY_pre;
 
input ARREADY;
input AWREADY;
input WREADY;
output ARVALID;
output RREADY;
output AWVALID;
output WVALID;
output BREADY;
 
 
reg stall_enable = 1;
integer burst_chance = 1;
integer burst_len = 10;
integer burst_val = 90;
integer ar_stall_chance = 10;
integer r_stall_chance = 10;
integer aw_stall_chance = 10;
integer w_stall_chance = 10;
integer b_stall_chance = 10;
 
integer burst_type;
reg burst_stall;
integer ar_stall_chance_valid;
integer r_stall_chance_valid;
integer aw_stall_chance_valid;
integer w_stall_chance_valid;
integer b_stall_chance_valid;
reg ARSTALL_pre = 0;
reg RSTALL_pre = 0;
reg AWSTALL_pre = 0;
reg WSTALL_pre = 0;
reg BSTALL_pre = 0;
reg ARSTALL;
reg RSTALL;
reg AWSTALL;
reg WSTALL;
reg BSTALL;
 
 
assign ARVALID = ARVALID_pre & (~ARSTALL) & (~rd_hold);
assign RREADY = RREADY_pre & (~RSTALL);
assign AWVALID = AWVALID_pre & (~AWSTALL) & (~wr_hold);
assign WVALID = WVALID_pre & (~WSTALL);
assign BREADY = BREADY_pre & (~BSTALL);
 
 
task set_stall;
reg stall;
begin
ar_stall_chance_valid = ar_stall_chance;
r_stall_chance_valid = r_stall_chance;
aw_stall_chance_valid = aw_stall_chance;
w_stall_chance_valid = w_stall_chance;
b_stall_chance_valid = b_stall_chance;
end
endtask
 
initial
begin
#FFD;
set_stall;
 
if (burst_chance > 0)
forever
begin
burst_stall = rand_chance(burst_chance);
if (burst_stall)
begin
#FFD;
burst_type = rand(1, 5);
case (burst_type)
1 : ar_stall_chance_valid = burst_val;
2 : r_stall_chance_valid = burst_val;
3 : aw_stall_chance_valid = burst_val;
4 : w_stall_chance_valid = burst_val;
5 : b_stall_chance_valid = burst_val;
endcase
repeat (burst_len) @(posedge clk);
set_stall;
end
else
begin
@(posedge clk);
end
end
end
always @(posedge clk)
begin
#FFD;
ARSTALL_pre = rand_chance(ar_stall_chance_valid);
RSTALL_pre = rand_chance(r_stall_chance_valid);
AWSTALL_pre = rand_chance(aw_stall_chance_valid);
WSTALL_pre = rand_chance(w_stall_chance_valid);
BSTALL_pre = rand_chance(b_stall_chance_valid);
end
always @(posedge clk or posedge reset)
if (reset)
begin
ARSTALL <= #FFD 1'b0;
RSTALL <= #FFD 1'b0;
AWSTALL <= #FFD 1'b0;
WSTALL <= #FFD 1'b0;
BSTALL <= #FFD 1'b0;
end
else if (stall_enable)
begin
ARSTALL <= #FFD ARSTALL_pre & ARREADY;
RSTALL <= #FFD RSTALL_pre;
AWSTALL <= #FFD AWSTALL_pre & AWREADY;
WSTALL <= #FFD WSTALL_pre & WREADY;
BSTALL <= #FFD BSTALL_pre;
end
else
begin
ARSTALL <= #FFD 1'b0;
RSTALL <= #FFD 1'b0;
AWSTALL <= #FFD 1'b0;
WSTALL <= #FFD 1'b0;
BSTALL <= #FFD 1'b0;
end
endmodule
 
 
 
 
 
 
 
 
OUTFILE PREFIX_stall.v
 
INCLUDE def_axi_master.txt
module PREFIX_stall(PORTS);
`include "prgen_rand.v"
input clk;
input reset;
 
input rd_hold;
input wr_hold;
input ARVALID_pre;
input RREADY_pre;
input AWVALID_pre;
input WVALID_pre;
input BREADY_pre;
 
input ARREADY;
input AWREADY;
input WREADY;
output ARVALID;
output RREADY;
output AWVALID;
output WVALID;
output BREADY;
 
 
reg stall_enable = 1;
integer burst_chance = 1;
integer burst_len = 10;
integer burst_val = 90;
integer ar_stall_chance = 10;
integer r_stall_chance = 10;
integer aw_stall_chance = 10;
integer w_stall_chance = 10;
integer b_stall_chance = 10;
 
integer burst_type;
reg burst_stall;
integer ar_stall_chance_valid;
integer r_stall_chance_valid;
integer aw_stall_chance_valid;
integer w_stall_chance_valid;
integer b_stall_chance_valid;
reg ARSTALL_pre = 0;
reg RSTALL_pre = 0;
reg AWSTALL_pre = 0;
reg WSTALL_pre = 0;
reg BSTALL_pre = 0;
reg ARSTALL;
reg RSTALL;
reg AWSTALL;
reg WSTALL;
reg BSTALL;
 
 
assign ARVALID = ARVALID_pre & (~ARSTALL) & (~rd_hold);
assign RREADY = RREADY_pre & (~RSTALL);
assign AWVALID = AWVALID_pre & (~AWSTALL) & (~wr_hold);
assign WVALID = WVALID_pre & (~WSTALL);
assign BREADY = BREADY_pre & (~BSTALL);
 
 
task set_stall;
reg stall;
begin
ar_stall_chance_valid = ar_stall_chance;
r_stall_chance_valid = r_stall_chance;
aw_stall_chance_valid = aw_stall_chance;
w_stall_chance_valid = w_stall_chance;
b_stall_chance_valid = b_stall_chance;
end
endtask
 
initial
begin
#FFD;
set_stall;
 
if (burst_chance > 0)
forever
begin
burst_stall = rand_chance(burst_chance);
if (burst_stall)
begin
#FFD;
burst_type = rand(1, 5);
case (burst_type)
1 : ar_stall_chance_valid = burst_val;
2 : r_stall_chance_valid = burst_val;
3 : aw_stall_chance_valid = burst_val;
4 : w_stall_chance_valid = burst_val;
5 : b_stall_chance_valid = burst_val;
endcase
repeat (burst_len) @(posedge clk);
set_stall;
end
else
begin
@(posedge clk);
end
end
end
always @(posedge clk)
begin
#FFD;
ARSTALL_pre = rand_chance(ar_stall_chance_valid);
RSTALL_pre = rand_chance(r_stall_chance_valid);
AWSTALL_pre = rand_chance(aw_stall_chance_valid);
WSTALL_pre = rand_chance(w_stall_chance_valid);
BSTALL_pre = rand_chance(b_stall_chance_valid);
end
always @(posedge clk or posedge reset)
if (reset)
begin
ARSTALL <= #FFD 1'b0;
RSTALL <= #FFD 1'b0;
AWSTALL <= #FFD 1'b0;
WSTALL <= #FFD 1'b0;
BSTALL <= #FFD 1'b0;
end
else if (stall_enable)
begin
ARSTALL <= #FFD ARSTALL_pre & ARREADY; //keep VALID signal stable while ~READY
RSTALL <= #FFD RSTALL_pre;
AWSTALL <= #FFD AWSTALL_pre & AWREADY; //keep VALID signal stable while ~READY
WSTALL <= #FFD WSTALL_pre & WREADY; //keep VALID signal stable while ~READY
BSTALL <= #FFD BSTALL_pre;
end
else
begin
ARSTALL <= #FFD 1'b0;
RSTALL <= #FFD 1'b0;
AWSTALL <= #FFD 1'b0;
WSTALL <= #FFD 1'b0;
BSTALL <= #FFD 1'b0;
end
endmodule
 
 
 
 
 
 
 
/ic_registry_wr.v
65,6 → 65,7
wire cmd_pop_MMX;
wire cmd_pop_MMX_IDGROUP_MMX_ID.IDX;
 
wire slave_empty_MMX;
wire [SLV_BITS-1:0] slave_in_MMX_IDGROUP_MMX_ID.IDX;
wire [SLV_BITS-1:0] slave_out_MMX_IDGROUP_MMX_ID.IDX;
wire slave_empty_MMX_IDGROUP_MMX_ID.IDX;
80,6 → 81,9
reg [SLV_BITS-1:0] MMX_WSLV;
reg MMX_WOK;
 
reg MMX_pending;
reg MMX_pending_d;
wire MMX_pending_rise;
88,7 → 92,7
assign Wmatch_MMX_IDGROUP_MMX_ID.IDX = MMX_WID == ID_BITS'bADD_IDGROUP_MMX_ID;
assign cmd_push_MMX = MMX_AWVALID & MMX_AWREADY;
assign cmd_push_MMX = MMX_AWVALID & (MMX_pending ? MMX_pending_rise : MMX_AWREADY);
assign cmd_push_MMX_IDGROUP_MMX_ID.IDX = cmd_push_MMX & AWmatch_MMX_IDGROUP_MMX_ID.IDX;
assign cmd_pop_MMX = MMX_WVALID & MMX_WREADY & MMX_WLAST;
assign cmd_pop_MMX_IDGROUP_MMX_ID.IDX = cmd_pop_MMX & Wmatch_MMX_IDGROUP_MMX_ID.IDX;
99,7 → 103,22
assign slave_in_MMX_IDGROUP_MMX_ID.IDX = MMX_AWSLV;
 
 
assign MMX_pending_rise = MMX_pending & (~MMX_pending_d);
always @(posedge clk or posedge reset)
if (reset)
begin
MMX_pending <= #FFD 1'b0;
MMX_pending_d <= #FFD 1'b0;
end
else
begin
MMX_pending <= #FFD MMX_AWVALID & (~MMX_AWREADY);
MMX_pending_d <= #FFD MMX_pending;
end
LOOP MX
always @(*)
begin
112,7 → 131,7
always @(*)
begin
case (MMX_WSLV)
SLV_BITS'dSX : MMX_WOK = master_out_SSX == MSTR_BITS'dMX;
SLV_BITS'dSX : MMX_WOK = (master_out_SSX == MSTR_BITS'dMX) & (~slave_empty_MMX);
default : MMX_WOK = 1'b0;
endcase
end
120,7 → 139,9
ENDLOOP MX
LOOP MX
assign slave_empty_MMX = GONCAT(slave_empty_MMX_IDGROUP_MMX_ID.IDX &);
LOOP IX GROUP_MMX_ID.NUM
prgen_fifo #(SLV_BITS, CMD_DEPTH)
slave_fifo_MMX_IDIX(
.clk(clk),
139,7 → 160,7
LOOP SX
prgen_fifo #(MSTR_BITS, 32) //TBD SLV_DEPTH
prgen_fifo #(MSTR_BITS, SLV_DEPTH)
master_fifo_SSX(
.clk(clk),
.reset(reset),
/axi_master_single.v
482,11 → 482,19
reg [LEN_BITS-1:0] len;
reg [SIZE_BITS-1:0] size;
 
integer size_bytes;
integer burst_bytes;
begin
if (DATA_BITS==32) size_max = 2'b10;
len = rand(len_min, len_max);
size = rand(size_min, size_max);
addr = rand_align(addr_min, addr_max, 1 << size);
size_bytes = 1 << size;
burst_bytes = size_bytes * (len+1);
addr = rand_align(addr_min, addr_max, size_bytes);
if (addr[11:0] + burst_bytes > 16'h1000) //don't cross 4KByte page
begin
addr = addr - burst_bytes;
end
if (ahb_bursts)
begin
845,28 → 853,28
CREATE axi_master_stall.v
PREFIX_stall
PREFIX_stall (
.clk(clk),
.reset(reset),
.clk(clk),
.reset(reset),
 
.rd_hold(rd_hold),
.wr_hold(wr_hold),
.ARVALID_pre(ARVALID_pre),
.RREADY_pre(RREADY_pre),
.AWVALID_pre(AWVALID_pre),
.WVALID_pre(WVALID_pre),
.BREADY_pre(BREADY_pre),
.ARREADY(ARREADY),
.AWREADY(AWREADY),
.WREADY(WREADY),
.ARVALID(ARVALID),
.RREADY(RREADY),
.AWVALID(AWVALID),
.WVALID(WVALID),
.BREADY(BREADY)
);
.rd_hold(rd_hold),
.wr_hold(wr_hold),
.ARVALID_pre(ARVALID_pre),
.RREADY_pre(RREADY_pre),
.AWVALID_pre(AWVALID_pre),
.WVALID_pre(WVALID_pre),
.BREADY_pre(BREADY_pre),
.ARREADY(ARREADY),
.AWREADY(AWREADY),
.WREADY(WREADY),
.ARVALID(ARVALID),
.RREADY(RREADY),
.AWVALID(AWVALID),
.WVALID(WVALID),
.BREADY(BREADY)
);
 
 
endmodule
/ic_dec.v
45,6 → 45,11
reg [SLV_BITS-1:0] MMX_ASLV;
reg MMX_AIDOK;
wire [DEC_MSB:DEC_LSB] MMX_AADDR_DEC;
 
 
assign MMX_AADDR_DEC = MMX_AADDR[DEC_MSB:DEC_LSB];
LOOP MX
always @(MMX_AADDR or MMX_AIDOK)
begin
52,7 → 57,7
case (MMX_AIDOK)
1'b1 : MMX_ASLV = SLV_BITS'd0;
ELSE TRUE(SLAVE_NUM==1)
case ({MMX_AIDOK, MMX_AADDR[DEC_MSB:DEC_LSB]})
case ({MMX_AIDOK, MMX_AADDR_DEC})
{1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = SLV_BITS'dSX;
ENDIF TRUE(SLAVE_NUM==1)
default : MMX_ASLV = SLV_BITS'dSERR;

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