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URL https://opencores.org/ocsvn/axi_slave/axi_slave/trunk

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    /axi_slave/trunk
    from Rev 11 to Rev 12
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Rev 11 → Rev 12

/src/base/axi_slave_cmd_fifo.v
26,121 → 26,121
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_cmd_fifo.v
 
INCLUDE def_axi_slave.txt
module PREFIX_cmd_fifo (PORTS);
 
parameter DEPTH = 8;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(DEPTH <= 256) ? 8 :
(DEPTH <= 512) ? 9 : 0; //0 is ilegal
 
input clk;
input reset;
input [ADDR_BITS-1:0] AADDR;
input [ID_BITS-1:0] AID;
input [1:0] ASIZE;
input [LEN_BITS-1:0] ALEN;
input AVALID;
input AREADY;
 
input VALID;
input READY;
input LAST;
 
output [ADDR_BITS-1:0] cmd_addr;
output [ID_BITS-1:0] cmd_id;
output [SIZE_BITS-1:0] cmd_size;
output [LEN_BITS-1:0] cmd_len;
output [1:0] cmd_resp;
output cmd_timeout;
output cmd_ready;
output cmd_empty;
output cmd_full;
 
 
wire push;
wire pop;
wire empty;
wire full;
wire [DEPTH_BITS:0] fullness;
 
 
wire [1:0] resp_in;
wire timeout_in;
wire timeout_out;
reg [ADDR_BITS-1:0] SLVERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] DECERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] TIMEOUT_addr = {ADDR_BITS{1'b1}};
 
 
parameter RESP_SLVERR = 2'b10;
parameter RESP_DECERR = 2'b11;
 
 
assign resp_in =
push & (SLVERR_addr == AADDR) ? RESP_SLVERR :
push & (DECERR_addr == AADDR) ? RESP_DECERR : 2'b00;
 
assign timeout_in = push & (TIMEOUT_addr == AADDR);
assign cmd_timeout = timeout_out & (TIMEOUT_addr != 0);
assign cmd_full = full | (DEPTH == fullness);
assign cmd_empty = empty;
assign cmd_ready = ~empty;
assign push = AVALID & AREADY;
assign pop = VALID & READY & LAST;
 
CREATE prgen_fifo.v DEFCMD(DEFINE STUB)
prgen_fifo_stub #(ADDR_BITS+ID_BITS+SIZE_BITS+LEN_BITS+2+1, DEPTH)
cmd_fifo(
.clk(clk),
.reset(reset),
.push(push),
.pop(pop),
.din({AADDR,
AID,
ASIZE,
ALEN,
resp_in,
timeout_in
}
),
.dout({cmd_addr,
cmd_id,
cmd_size,
cmd_len,
cmd_resp,
timeout_out
}
),
.fullness(fullness),
.empty(empty),
.full(full)
);
endmodule
 
 
 
OUTFILE PREFIX_cmd_fifo.v
 
INCLUDE def_axi_slave.txt
module PREFIX_cmd_fifo (PORTS);
 
parameter DEPTH = 8;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(DEPTH <= 256) ? 8 :
(DEPTH <= 512) ? 9 : 0; //0 is ilegal
 
input clk;
input reset;
input [ADDR_BITS-1:0] AADDR;
input [ID_BITS-1:0] AID;
input [SIZE_BITS-1:0] ASIZE;
input [LEN_BITS-1:0] ALEN;
input AVALID;
input AREADY;
 
input VALID;
input READY;
input LAST;
 
output [ADDR_BITS-1:0] cmd_addr;
output [ID_BITS-1:0] cmd_id;
output [SIZE_BITS-1:0] cmd_size;
output [LEN_BITS-1:0] cmd_len;
output [1:0] cmd_resp;
output cmd_timeout;
output cmd_ready;
output cmd_empty;
output cmd_full;
 
 
wire push;
wire pop;
wire empty;
wire full;
wire [DEPTH_BITS:0] fullness;
 
 
wire [1:0] resp_in;
wire timeout_in;
wire timeout_out;
reg [ADDR_BITS-1:0] SLVERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] DECERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] TIMEOUT_addr = {ADDR_BITS{1'b1}};
 
 
parameter RESP_SLVERR = 2'b10;
parameter RESP_DECERR = 2'b11;
 
 
assign resp_in =
push & (SLVERR_addr == AADDR) ? RESP_SLVERR :
push & (DECERR_addr == AADDR) ? RESP_DECERR : 2'b00;
 
assign timeout_in = push & (TIMEOUT_addr == AADDR);
assign cmd_timeout = timeout_out & (TIMEOUT_addr != 0);
assign cmd_full = full | (DEPTH == fullness);
assign cmd_empty = empty;
assign cmd_ready = ~empty;
assign push = AVALID & AREADY;
assign pop = VALID & READY & LAST;
 
CREATE prgen_fifo.v DEFCMD(DEFINE STUB)
prgen_fifo_stub #(ADDR_BITS+ID_BITS+SIZE_BITS+LEN_BITS+2+1, DEPTH)
cmd_fifo(
.clk(clk),
.reset(reset),
.push(push),
.pop(pop),
.din({AADDR,
AID,
ASIZE,
ALEN,
resp_in,
timeout_in
}
),
.dout({cmd_addr,
cmd_id,
cmd_size,
cmd_len,
cmd_resp,
timeout_out
}
),
.fullness(fullness),
.empty(empty),
.full(full)
);
endmodule
 
 
/src/base/def_axi_slave.txt
31,6 → 31,8
 
INCLUDE def_axi_slave_static.txt
 
STARTUSER
SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay
 
SWAP.USER PREFIX axi_slave ##prefix for all module and file names
/src/base/def_axi_slave_static.txt
29,8 → 29,8
 
SWAP.GLOBAL MODEL_NAME AXI slave stub
VERIFY ((DATA_BITS == 64) || (DATA_BITS == 32)) ##stub supports 32 or 64 bits data bus
VERIFY (SIZE_BITS <= 2) ##stub supports 32 or 64 bits data bus
VERIFY (DATA_BITS in 32, 64) ##stub supports 32 or 64 bits data bus
VERIFY (SIZE_BITS in 2, 3) ##stub supports 32 or 64 bits data bus
VERIFY (ADDR_BITS <= 24) ##Memory size should not be too big to prevent maloc fail
 
GROUP STUB_AXI_A is {

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