URL
https://opencores.org/ocsvn/axi_slave/axi_slave/trunk
Subversion Repositories axi_slave
Compare Revisions
- This comparison shows the changes necessary to convert path
/axi_slave/trunk
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/run/run.bat
1,6 → 1,6
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echo off |
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..\..\..\robust.exe ../src/base/axi_slave.v -od out -I ../src/gen -list filelist.txt -listpath -header |
..\..\..\robust.exe ../src/base/axi_slave.v -od out -I ../src/gen -list list.txt -listpath -header |
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echo Completed RobustVerilog axi slave run - results in run/out/ |
/run/run.sh
1,5 → 1,5
#!/bin/bash |
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../../../robust ../src/base/axi_slave.v -od out -I ../src/gen -list filelist.txt -listpath -header |
../../../robust ../src/base/axi_slave.v -od out -I ../src/gen -list list.txt -listpath -header ${@} |
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echo Completed RobustVerilog axi slave run - results in run/out/ |
/src/gen/prgen_rand.v
26,62 → 26,64
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
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function integer rand_chance; |
input [31:0] chance_true; |
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begin |
if (chance_true > 100) |
begin |
$display("RAND_CHANCE-E-: fatal error, rand_chance called with percent chance larger than 100.\tTime: %0d ns", $time); |
$finish; |
end |
rand_chance = (rand(1,100) <= chance_true); |
end |
endfunction // rand_chance |
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function integer rand; |
input [31:0] min; |
input [31:0] max; |
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integer range; |
begin |
if (min > max) |
begin |
$display("RAND-E-: fatal error, rand was called with min larger than max.\tTime: %0d ns", $time); |
$finish; |
end |
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range = (max - min) + 1; |
if (range == 0) range = -1; |
rand = min + ($random % range); |
end |
endfunction // rand |
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function integer align; |
input [31:0] num; |
input [31:0] align_size; |
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integer align; |
begin |
align = num - (num % align_size); |
end |
endfunction |
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function integer rand_align; |
input [31:0] min; |
input [31:0] max; |
input [31:0] align; |
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integer rand_align; |
begin |
rand_align = rand(min, max); |
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if (rand_align > align) |
rand_align = align(rand_align, align); |
end |
endfunction |
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OUTFILE prgen_rand.v |
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function integer rand_chance; |
input [31:0] chance_true; |
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begin |
if (chance_true > 100) |
begin |
$display("RAND_CHANCE-E-: fatal error, rand_chance called with percent chance larger than 100.\tTime: %0d ns", $time); |
$finish; |
end |
rand_chance = (rand(1,100) <= chance_true); |
end |
endfunction // rand_chance |
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function integer rand; |
input [31:0] min; |
input [31:0] max; |
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integer range; |
begin |
if (min > max) |
begin |
$display("RAND-E-: fatal error, rand was called with min larger than max.\tTime: %0d ns", $time); |
$finish; |
end |
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range = (max - min) + 1; |
if (range == 0) range = -1; |
rand = min + ($random % range); |
end |
endfunction // rand |
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function integer align; |
input [31:0] num; |
input [31:0] align_size; |
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integer align; |
begin |
align = num - (num % align_size); |
end |
endfunction |
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function integer rand_align; |
input [31:0] min; |
input [31:0] max; |
input [31:0] align; |
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integer rand_align; |
begin |
rand_align = rand(min, max); |
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if (rand_align > align) |
rand_align = align(rand_align, align); |
end |
endfunction |
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/src/base/axi_slave_busy.v
26,162 → 26,163
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
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OUTFILE PREFIX_busy.v |
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INCLUDE def_axi_slave.txt |
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module PREFIX_busy(PORTS); |
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`include "prgen_rand.v" |
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input clk; |
input reset; |
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input ARREADY_pre; |
input RVALID_pre; |
input AWREADY_pre; |
input WREADY_pre; |
input BVALID_pre; |
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output ARREADY; |
output RVALID; |
output AWREADY; |
output WREADY; |
output BVALID; |
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output RBUSY; |
output BBUSY; |
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reg stall_enable = 1; |
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integer burst_chance = 1; |
integer burst_len = 10; |
integer burst_val = 90; |
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integer ar_stall_chance = 10; |
integer r_stall_chance = 10; |
integer aw_stall_chance = 10; |
integer w_stall_chance = 10; |
integer b_stall_chance = 10; |
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integer burst_type; |
reg burst_stall; |
integer ar_stall_chance_valid; |
integer r_stall_chance_valid; |
integer aw_stall_chance_valid; |
integer w_stall_chance_valid; |
integer b_stall_chance_valid; |
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reg ARBUSY_pre = 0; |
reg RBUSY_pre = 0; |
reg AWBUSY_pre = 0; |
reg WBUSY_pre = 0; |
reg BBUSY_pre = 0; |
reg ARBUSY; |
reg RBUSY; |
reg AWBUSY; |
reg WBUSY; |
reg BBUSY; |
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assign ARREADY = ARREADY_pre & (~ARBUSY); |
assign RVALID = RVALID_pre; //in rd_buff |
assign AWREADY = AWREADY_pre & (~AWBUSY); |
assign WREADY = WREADY_pre & (~WBUSY); |
assign BVALID = BVALID_pre; //in wresp |
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task set_stall; |
reg stall; |
begin |
ar_stall_chance_valid = ar_stall_chance; |
r_stall_chance_valid = r_stall_chance; |
aw_stall_chance_valid = aw_stall_chance; |
w_stall_chance_valid = w_stall_chance; |
b_stall_chance_valid = b_stall_chance; |
end |
endtask |
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initial |
begin |
#FFD; |
set_stall; |
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if (burst_chance > 0) |
forever |
begin |
burst_stall = rand_chance(burst_chance); |
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if (burst_stall) |
begin |
#FFD; |
burst_type = rand(1, 5); |
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case (burst_type) |
1 : ar_stall_chance_valid = burst_val; |
2 : r_stall_chance_valid = burst_val; |
3 : aw_stall_chance_valid = burst_val; |
4 : w_stall_chance_valid = burst_val; |
5 : b_stall_chance_valid = burst_val; |
endcase |
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repeat (burst_len) @(posedge clk); |
set_stall; |
end |
else |
begin |
@(posedge clk); |
end |
end |
end |
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always @(posedge clk) |
begin |
#FFD; |
ARBUSY_pre = rand_chance(ar_stall_chance_valid); |
RBUSY_pre = rand_chance(r_stall_chance_valid); |
AWBUSY_pre = rand_chance(aw_stall_chance_valid); |
WBUSY_pre = rand_chance(w_stall_chance_valid); |
BBUSY_pre = rand_chance(b_stall_chance_valid); |
end |
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always @(posedge clk or posedge reset) |
if (reset) |
begin |
ARBUSY <= #FFD 1'b0; |
RBUSY <= #FFD 1'b0; |
AWBUSY <= #FFD 1'b0; |
WBUSY <= #FFD 1'b0; |
BBUSY <= #FFD 1'b0; |
end |
else if (stall_enable) |
begin |
ARBUSY <= #FFD ARBUSY_pre; |
RBUSY <= #FFD RBUSY_pre; |
AWBUSY <= #FFD AWBUSY_pre; |
WBUSY <= #FFD WBUSY_pre; |
BBUSY <= #FFD BBUSY_pre; |
end |
else |
begin |
ARBUSY <= #FFD 1'b0; |
RBUSY <= #FFD 1'b0; |
AWBUSY <= #FFD 1'b0; |
WBUSY <= #FFD 1'b0; |
BBUSY <= #FFD 1'b0; |
end |
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endmodule |
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OUTFILE PREFIX_busy.v |
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INCLUDE def_axi_slave.txt |
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module PREFIX_busy(PORTS); |
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CREATE prgen_rand.v DEFCMD(DEFINE NOT_IN_LIST) |
`include "prgen_rand.v" |
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input clk; |
input reset; |
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input ARREADY_pre; |
input RVALID_pre; |
input AWREADY_pre; |
input WREADY_pre; |
input BVALID_pre; |
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output ARREADY; |
output RVALID; |
output AWREADY; |
output WREADY; |
output BVALID; |
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output RBUSY; |
output BBUSY; |
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reg stall_enable = 1; |
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integer burst_chance = 1; |
integer burst_len = 10; |
integer burst_val = 90; |
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integer ar_stall_chance = 10; |
integer r_stall_chance = 10; |
integer aw_stall_chance = 10; |
integer w_stall_chance = 10; |
integer b_stall_chance = 10; |
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integer burst_type; |
reg burst_stall; |
integer ar_stall_chance_valid; |
integer r_stall_chance_valid; |
integer aw_stall_chance_valid; |
integer w_stall_chance_valid; |
integer b_stall_chance_valid; |
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reg ARBUSY_pre = 0; |
reg RBUSY_pre = 0; |
reg AWBUSY_pre = 0; |
reg WBUSY_pre = 0; |
reg BBUSY_pre = 0; |
reg ARBUSY; |
reg RBUSY; |
reg AWBUSY; |
reg WBUSY; |
reg BBUSY; |
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assign ARREADY = ARREADY_pre & (~ARBUSY); |
assign RVALID = RVALID_pre; //in rd_buff |
assign AWREADY = AWREADY_pre & (~AWBUSY); |
assign WREADY = WREADY_pre & (~WBUSY); |
assign BVALID = BVALID_pre; //in wresp |
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task set_stall; |
reg stall; |
begin |
ar_stall_chance_valid = ar_stall_chance; |
r_stall_chance_valid = r_stall_chance; |
aw_stall_chance_valid = aw_stall_chance; |
w_stall_chance_valid = w_stall_chance; |
b_stall_chance_valid = b_stall_chance; |
end |
endtask |
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initial |
begin |
#FFD; |
set_stall; |
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if (burst_chance > 0) |
forever |
begin |
burst_stall = rand_chance(burst_chance); |
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if (burst_stall) |
begin |
#FFD; |
burst_type = rand(1, 5); |
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case (burst_type) |
1 : ar_stall_chance_valid = burst_val; |
2 : r_stall_chance_valid = burst_val; |
3 : aw_stall_chance_valid = burst_val; |
4 : w_stall_chance_valid = burst_val; |
5 : b_stall_chance_valid = burst_val; |
endcase |
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repeat (burst_len) @(posedge clk); |
set_stall; |
end |
else |
begin |
@(posedge clk); |
end |
end |
end |
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always @(posedge clk) |
begin |
#FFD; |
ARBUSY_pre = rand_chance(ar_stall_chance_valid); |
RBUSY_pre = rand_chance(r_stall_chance_valid); |
AWBUSY_pre = rand_chance(aw_stall_chance_valid); |
WBUSY_pre = rand_chance(w_stall_chance_valid); |
BBUSY_pre = rand_chance(b_stall_chance_valid); |
end |
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always @(posedge clk or posedge reset) |
if (reset) |
begin |
ARBUSY <= #FFD 1'b0; |
RBUSY <= #FFD 1'b0; |
AWBUSY <= #FFD 1'b0; |
WBUSY <= #FFD 1'b0; |
BBUSY <= #FFD 1'b0; |
end |
else if (stall_enable) |
begin |
ARBUSY <= #FFD ARBUSY_pre; |
RBUSY <= #FFD RBUSY_pre; |
AWBUSY <= #FFD AWBUSY_pre; |
WBUSY <= #FFD WBUSY_pre; |
BBUSY <= #FFD BBUSY_pre; |
end |
else |
begin |
ARBUSY <= #FFD 1'b0; |
RBUSY <= #FFD 1'b0; |
AWBUSY <= #FFD 1'b0; |
WBUSY <= #FFD 1'b0; |
BBUSY <= #FFD 1'b0; |
end |
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endmodule |
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