URL
https://opencores.org/ocsvn/axi_slave/axi_slave/trunk
Subversion Repositories axi_slave
Compare Revisions
- This comparison shows the changes necessary to convert path
/axi_slave/trunk
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/run/run.bat
1,6 → 1,4
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echo off |
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..\..\..\robust.exe ../src/base/axi_slave.v -od out -I ../src/gen -list list.txt -listpath -header |
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echo Completed RobustVerilog axi slave run - results in run/out/ |
..\..\..\robust.exe ../src/base/axi_slave.v -od out -I ../src/gen -list list.txt -listpath -header -gui |
/run/run.sh
1,5 → 1,3
#!/bin/bash |
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../../../robust ../src/base/axi_slave.v -od out -I ../src/gen -list list.txt -listpath -header ${@} |
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echo Completed RobustVerilog axi slave run - results in run/out/ |
../../../robust ../src/base/axi_slave.v -od out -I ../src/gen -list list.txt -listpath -header -gui ${@} |
/src/base/def_axi_slave.txt
26,21 → 26,21
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
//////////////////////////////////////////////////////////////////##> |
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INCLUDE def_axi_slave_static.txt |
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SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay |
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SWAP PREFIX axi_slave ##prefix for all module and file names |
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SWAP ID_BITS 4 ##AXI ID bits |
SWAP ADDR_BITS 24 ##AXI address bits |
SWAP DATA_BITS 64 ##AXI data bits |
SWAP LEN_BITS 4 ##AXI LEN bits |
SWAP SIZE_BITS 2 ##AXI SIZE bits |
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SWAP WCMD_DEPTH 8 ##AXI write command depth |
SWAP RCMD_DEPTH 8 ##AXI write command depth |
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##DEFINE TRACE ##print memory trace to file |
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INCLUDE def_axi_slave_static.txt |
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SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay |
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SWAP.USER PREFIX axi_slave ##prefix for all module and file names |
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SWAP.USER ID_BITS 4 ##AXI ID bits |
SWAP.USER ADDR_BITS 24 ##AXI address bits |
SWAP.USER DATA_BITS 64 ##AXI data bits |
SWAP.USER LEN_BITS 4 ##AXI LEN bits |
SWAP.USER SIZE_BITS 2 ##AXI SIZE bits |
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SWAP.USER WCMD_DEPTH 8 ##AXI write command depth |
SWAP.USER RCMD_DEPTH 8 ##AXI write command depth |
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UNDEF TRACE ##print memory trace to file |
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/src/base/def_axi_slave_static.txt
26,64 → 26,66
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
//////////////////////////////////////////////////////////////////##> |
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VERIFY (DATA_BITS <= 64) else stub supports 32 or 64 bits data bus |
VERIFY (SIZE_BITS <= 3) else stub supports 32 or 64 bits data bus |
VERIFY (ADDR_BITS<=24) else Memory size should not be too big to prevent maloc fail |
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GROUP STUB_AXI_A is { |
ID ID_BITS output |
ADDR ADDR_BITS output |
LEN LEN_BITS output |
SIZE SIZE_BITS output |
BURST 2 output |
CACHE 4 output |
PROT 3 output |
LOCK 2 output |
VALID 1 output |
READY 1 input |
} |
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GROUP STUB_AXI_W is { |
ID ID_BITS output |
DATA DATA_BITS output |
STRB DATA_BITS/8 output |
LAST 1 output |
VALID 1 output |
READY 1 input |
} |
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GROUP STUB_AXI_B is { |
ID ID_BITS input |
RESP 2 input |
VALID 1 input |
READY 1 output |
} |
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GROUP STUB_AXI_R is { |
ID ID_BITS input |
DATA DATA_BITS input |
RESP 2 input |
LAST 1 input |
VALID 1 input |
READY 1 output |
} |
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GROUP STUB_AXI joins { |
GROUP STUB_AXI_A prefix_AW |
GROUP STUB_AXI_W prefix_W |
GROUP STUB_AXI_B prefix_B |
GROUP STUB_AXI_A prefix_AR |
GROUP STUB_AXI_R prefix_R |
} |
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GROUP STUB_MEM is { |
WR 1 output |
RD 1 output |
ADDR_WR ADDR_BITS output |
ADDR_RD ADDR_BITS output |
DIN DATA_BITS output |
BSEL DATA_BITS/8 output |
DOUT DATA_BITS input |
} |
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SWAP MODEL_NAME AXI slave stub |
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VERIFY (DATA_BITS <= 64) else stub supports 32 or 64 bits data bus |
VERIFY (SIZE_BITS <= 3) else stub supports 32 or 64 bits data bus |
VERIFY (ADDR_BITS<=24) else Memory size should not be too big to prevent maloc fail |
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GROUP STUB_AXI_A is { |
ID ID_BITS output |
ADDR ADDR_BITS output |
LEN LEN_BITS output |
SIZE SIZE_BITS output |
BURST 2 output |
CACHE 4 output |
PROT 3 output |
LOCK 2 output |
VALID 1 output |
READY 1 input |
} |
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GROUP STUB_AXI_W is { |
ID ID_BITS output |
DATA DATA_BITS output |
STRB DATA_BITS/8 output |
LAST 1 output |
VALID 1 output |
READY 1 input |
} |
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GROUP STUB_AXI_B is { |
ID ID_BITS input |
RESP 2 input |
VALID 1 input |
READY 1 output |
} |
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GROUP STUB_AXI_R is { |
ID ID_BITS input |
DATA DATA_BITS input |
RESP 2 input |
LAST 1 input |
VALID 1 input |
READY 1 output |
} |
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GROUP STUB_AXI joins { |
GROUP STUB_AXI_A prefix_AW |
GROUP STUB_AXI_W prefix_W |
GROUP STUB_AXI_B prefix_B |
GROUP STUB_AXI_A prefix_AR |
GROUP STUB_AXI_R prefix_R |
} |
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GROUP STUB_MEM is { |
WR 1 output |
RD 1 output |
ADDR_WR ADDR_BITS output |
ADDR_RD ADDR_BITS output |
DIN DATA_BITS output |
BSEL DATA_BITS/8 output |
DOUT DATA_BITS input |
} |
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