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URL https://opencores.org/ocsvn/axi_slave/axi_slave/trunk

Subversion Repositories axi_slave

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  • This comparison shows the changes necessary to convert path 
    /axi_slave
    from Rev 9 to Rev 10
    ↔ Reverse comparison
  •

Rev 9 → Rev 10

/trunk/run/robust_axi_slave.pro File deleted
/trunk/run/run.bat
1,6 → 1,6
 
echo off
 
:..\..\..\robust.exe ../src/base/axi_slave.v -od out -I ../src/gen -list list.txt -listpath -header -gui
:..\..\..\..\robust.exe ../src/base/axi_slave.v -od out -I ../src/gen -list list.txt -listpath -header -gui
 
..\..\..\robust.exe robust_axi_slave.pro -gui %1 %2 %3
..\..\..\..\robust.exe ../robust_axi_slave.pro -gui %1 %2 %3
/trunk/run/run.sh
1,12 → 1,12
#!/bin/bash
 
../../../robust -null
../../../../robust -null
if [ $? -eq 0 ];then
ROBUST=../../../robust
ROBUST=../../../../robust
else
echo "RobustVerilog warning: GUI version not supported - using non-GUI version robust-lite"
ROBUST=../../../robust-lite
ROBUST=../../../../robust-lite
fi
 
#$ROBUST ../src/base/axi_slave.v -od out -I ../src/gen -list list.txt -listpath -header -gui ${@}
$ROBUST robust_axi_slave.pro -gui ${@}
#$ROBUST src/base/axi_slave.v -od out -I ../src/gen -list list.txt -listpath -header -gui ${@}
$ROBUST ../robust_axi_slave.pro -gui ${@}
/trunk/src/gen/prgen_rand.v
66,7 → 66,6
input [31:0] num;
input [31:0] align_size;
integer align;
begin
align = num - (num % align_size);
end
76,14 → 75,13
function integer rand_align;
input [31:0] min;
input [31:0] max;
input [31:0] align;
input [31:0] align_val;
 
integer rand_align;
begin
rand_align = rand(min, max);
if (rand_align > align)
rand_align = align(rand_align, align);
if (rand_align > align_val)
rand_align = align(rand_align, align_val);
end
endfunction
 
/trunk/src/base/axi_slave_busy.v
39,19 → 39,10
input clk;
input reset;
input ARREADY_pre;
input RVALID_pre;
input AWREADY_pre;
input WREADY_pre;
input BVALID_pre;
output ARREADY;
output RVALID;
output AWREADY;
output WREADY;
output BVALID;
 
output ARBUSY;
output RBUSY;
output AWBUSY;
output WBUSY;
output BBUSY;
 
 
88,15 → 79,7
reg WBUSY;
reg BBUSY;
 
 
assign ARREADY = ARREADY_pre & (~ARBUSY);
assign RVALID = RVALID_pre; //in rd_buff
assign AWREADY = AWREADY_pre & (~AWBUSY);
assign WREADY = WREADY_pre & (~WBUSY);
assign BVALID = BVALID_pre; //in wresp
 
 
task set_stall;
reg stall;
begin
/trunk/src/base/axi_slave_addr_gen.v
37,7 → 37,7
input reset;
 
input [ADDR_BITS-1:0] cmd_addr;
input [1:0] cmd_size;
input [SIZE_BITS-1:0] cmd_size;
 
input advance;
input restart;
48,7 → 48,7
reg [ADDR_BITS-1:0] offset;
wire [3:0] size_bytes;
 
assign size_bytes =
assign size_bytes =
cmd_size == 2'b00 ? 4'd1 :
cmd_size == 2'b01 ? 4'd2 :
cmd_size == 2'b10 ? 4'd4 :
/trunk/src/base/axi_slave_cmd_fifo.v
63,7 → 63,7
 
output [ADDR_BITS-1:0] cmd_addr;
output [ID_BITS-1:0] cmd_id;
output [1:0] cmd_size;
output [SIZE_BITS-1:0] cmd_size;
output [LEN_BITS-1:0] cmd_len;
output [1:0] cmd_resp;
output cmd_timeout;
111,7 → 111,7
 
CREATE prgen_fifo.v DEFCMD(DEFINE STUB)
prgen_fifo_stub #(ADDR_BITS+ID_BITS+LEN_BITS+2+2+1, DEPTH)
prgen_fifo_stub #(ADDR_BITS+ID_BITS+SIZE_BITS+LEN_BITS+2+1, DEPTH)
cmd_fifo(
.clk(clk),
.reset(reset),
/trunk/src/base/def_axi_slave.txt
27,7 → 27,7
//// ////
//////////////////////////////////////////////////////////////////##>
 
REQUIRE(1.3)
REQUIRE(1.4)
 
INCLUDE def_axi_slave_static.txt
 
/trunk/src/base/axi_slave_ram.v
41,19 → 41,17
port GROUP_STUB_MEM;
//busy
wire ARREADY_pre;
wire RVALID_pre;
wire AWREADY_pre;
wire WREADY_pre;
wire BVALID_pre;
wire RBUSY;
//busy
wire ARBUSY;
wire RBUSY;
wire AWBUSY;
wire WBUSY;
wire BBUSY;
//wcmd fifo
wire [ADDR_BITS-1:0] wcmd_addr;
wire [ID_BITS-1:0] wcmd_id;
wire [1:0] wcmd_size;
wire [SIZE_BITS-1:0] wcmd_size;
wire [LEN_BITS-1:0] wcmd_len;
wire [1:0] wcmd_resp;
wire wcmd_timeout;
64,11 → 62,12
//rcmd fifo
wire [ADDR_BITS-1:0] rcmd_addr;
wire [ID_BITS-1:0] rcmd_id;
wire [1:0] rcmd_size;
wire [SIZE_BITS-1:0] rcmd_size;
wire [LEN_BITS-1:0] rcmd_len;
wire [1:0] rcmd_resp;
wire rcmd_timeout;
wire rcmd_ready;
wire rcmd_ready;
wire rcmd_empty;
wire rcmd_full;
 
wire [ID_BITS-1:0] rcmd_id2;
87,27 → 86,20
 
assign RID = rcmd_id2;
 
 
assign ARREADY = ((~rcmd_full) & (~AR_stall) & (~ARBUSY)) || (~ARVALID);
assign AWREADY = ((~wcmd_full) & (~AW_stall) & (~AWBUSY)) || (~AWVALID);
assign BVALID = (~wresp_timeout) & (wresp_pending ? (~wresp_empty) : (~wresp_empty) & (~BBUSY));
 
assign ARREADY_pre = (~rcmd_full) & (~AR_stall);
assign AWREADY_pre = (~wcmd_full) & (~AW_stall);
assign BVALID_pre = (~wresp_timeout) & (wresp_pending ? (~wresp_empty) : (~wresp_empty) & (~BBUSY));
 
CREATE axi_slave_busy.v
PREFIX_busy
PREFIX_busy (
.clk(clk),
.reset(reset),
.ARREADY_pre(ARREADY_pre),
.RVALID_pre(RVALID_pre),
.AWREADY_pre(AWREADY_pre),
.WREADY_pre(WREADY_pre),
.BVALID_pre(BVALID_pre),
.ARREADY(ARREADY),
.RVALID(RVALID),
.AWREADY(AWREADY),
.WREADY(WREADY),
.BVALID(BVALID),
.RBUSY(RBUSY),
.reset(reset),
.ARBUSY(ARBUSY),
.RBUSY(RBUSY),
.AWBUSY(AWBUSY),
.WBUSY(WBUSY),
.BBUSY(BBUSY)
);
 
181,7 → 173,7
.cmd_resp(),
.cmd_timeout(),
.cmd_ready(),
.cmd_empty(),
.cmd_empty(rcmd_empty),
.cmd_full(rcmd_full)
);
231,7 → 223,7
);
CREATE axi_slave_rd_buff.v
PREFIX_rd_buff #(DATA_BITS, ID_BITS)
PREFIX_rd_buff
PREFIX_rd_buff(
.clk(clk),
.reset(reset),
242,7 → 234,7
.rcmd_resp(rcmd_resp),
.rcmd_timeout(rcmd_timeout),
.rcmd_ready(rcmd_ready),
.RVALID(RVALID_pre),
.RVALID(RVALID),
.RREADY(RREADY),
.RLAST(RLAST),
.RDATA(RDATA),
252,10 → 244,10
);
 
//wr_buff
assign WREADY_pre = (~wcmd_timeout) & (~wcmd_empty);
assign WR = WVALID & WREADY & (~wcmd_empty);
assign DIN = WDATA;
assign BSEL = WSTRB;
assign WREADY = (~wcmd_timeout) & (~wcmd_empty) & (~WBUSY);
assign WR = WVALID & WREADY & (~wcmd_empty);
assign DIN = WDATA;
assign BSEL = WSTRB;
endmodule
/trunk/src/base/def_axi_slave_static.txt
29,9 → 29,9
 
SWAP.GLOBAL MODEL_NAME AXI slave stub
VERIFY ((DATA_BITS == 64) || (DATA_BITS == 32))
VERIFY (SIZE_BITS <= 3) else stub supports 32 or 64 bits data bus
VERIFY (ADDR_BITS <= 24) else Memory size should not be too big to prevent maloc fail
VERIFY ((DATA_BITS == 64) || (DATA_BITS == 32)) ##stub supports 32 or 64 bits data bus
VERIFY (SIZE_BITS <= 2) ##stub supports 32 or 64 bits data bus
VERIFY (ADDR_BITS <= 24) ##Memory size should not be too big to prevent maloc fail
 
GROUP STUB_AXI_A is {
ID ID_BITS output
/trunk/robust_axi_slave.pro
0,0 → 1,14
PROJDIR = run
 
SRCFILE = axi_slave.v
DEFFILE =
 
OUTDIR = out
 
INCDIR += ../src/base
INCDIR += ../src/gen
 
LIST = list.txt
+LISTPATH
 
+HEADER

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