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URL https://opencores.org/ocsvn/b163arith/b163arith/trunk

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/b163arith/trunk/shift_xor_128.vhd
0,0 → 1,70
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity shift_xor_128 is
port(clk : in std_logic;
a : in std_logic_vector(162 downto 0);
m : in std_logic_vector(162 downto 0);
c : out std_logic_vector(162 downto 0));
end shift_xor_128;
 
architecture Behavioral of shift_xor_128 is
 
component dsp_xor is
port (clk : in std_logic;
op_1 : in std_logic_vector(47 downto 0);
op_2 : in std_logic_vector(47 downto 0);
op_3 : out std_logic_vector(47 downto 0));
end component;
 
signal op_1_s : std_logic_vector(162 downto 0);
 
signal r_0_s : std_logic_vector(47 downto 0);
signal r_1_s : std_logic_vector(47 downto 0);
signal r_2_s : std_logic_vector(47 downto 0);
signal r_3_s : std_logic_vector(47 downto 0);
 
signal xor_in_aux_0_s : std_logic_vector(47 downto 0);
signal xor_in_aux_1_s : std_logic_vector(47 downto 0);
signal xor_out_aux_s : std_logic_vector(47 downto 0);
 
begin
 
process(a, m, op_1_s, r_3_s, r_2_s, r_1_s, r_0_s)
begin
if a(162) = '1' then
c <= r_3_s(47 downto 29) & r_2_s & r_1_s & r_0_s;
else
c <= op_1_s;
end if;
end process;
 
op_1_s <= a(161 downto 0) & '0';
 
DSP_XOR_0 : dsp_xor port map (clk, op_1_s(47 downto 0), m(47 downto 0), r_0_s);
DSP_XOR_1 : dsp_xor port map (clk, op_1_s(95 downto 48), m(95 downto 48), r_1_s);
DSP_XOR_2 : dsp_xor port map (clk, op_1_s(143 downto 96), m(143 downto 96), r_2_s);
 
xor_in_aux_0_s <= op_1_s(162 downto 134) & "0000000000000000000";
xor_in_aux_1_s <= m(162 downto 134) & "0000000000000000000";
 
DSP_XOR_3 : dsp_xor port map (clk, xor_in_aux_0_s, xor_in_aux_1_s, r_3_s);
 
end Behavioral;
 
/b163arith/trunk/poly.coe
0,0 → 1,3
memory_initialization_radix=16;
memory_initialization_vector=
00000000000000000000000000000087;
/b163arith/trunk/poly_rom.xco
0,0 → 1,108
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Thu May 02 09:34:53 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a100t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=C:\Users\vmr\Desktop\crypto_ng\b_163\mul\poly.coe
CSET collision_warnings=ALL
CSET component_name=poly_rom
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_32bit_address=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=true
CSET mem_file=no_Mem_file_loaded
CSET memory_type=Single_Port_ROM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=0
CSET port_b_clock=0
CSET port_b_enable_rate=0
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=163
CSET read_width_b=163
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_bram_block=Stand_Alone
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=2
CSET write_width_a=163
CSET write_width_b=163
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T16:22:25Z
# END Extra information
GENERATE
# CRC: 8973e54f
/b163arith/trunk/gf_163_bram_dsp.vhd
0,0 → 1,120
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity gf_163_bram_dsp is
port(clk : in std_logic;
rst : in std_logic;
a : in std_logic_vector(162 downto 0);
b : in std_logic_vector(162 downto 0);
p : out std_logic_vector(162 downto 0));
end gf_163_bram_dsp;
 
architecture Behavioral of gf_163_bram_dsp is
 
COMPONENT poly_rom
PORT (clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(162 DOWNTO 0));
END COMPONENT;
 
component dsp_xor is
port (clk : in std_logic;
op_1 : in std_logic_vector(47 downto 0);
op_2 : in std_logic_vector(47 downto 0);
op_3 : out std_logic_vector(47 downto 0));
end component;
 
component shift_xor_128 is
port(clk : in std_logic;
a : in std_logic_vector(162 downto 0);
m : in std_logic_vector(162 downto 0);
c : out std_logic_vector(162 downto 0));
end component;
 
signal p_1_s : std_logic_vector(162 downto 0);
signal p_2_s : std_logic_vector(162 downto 0);
signal b_s : std_logic;
signal p_s : std_logic_vector(162 downto 0);
signal m_s : std_logic_vector(162 downto 0);
signal c_s : std_logic_vector(162 downto 0);
signal r_0_s : std_logic_vector(47 downto 0);
signal r_1_s : std_logic_vector(47 downto 0);
signal r_2_s : std_logic_vector(47 downto 0);
signal r_3_s : std_logic_vector(47 downto 0);
 
signal xor_in_aux_0_s : std_logic_vector(47 downto 0);
signal xor_in_aux_1_s : std_logic_vector(47 downto 0);
signal xor_out_aux_s : std_logic_vector(47 downto 0);
 
begin
 
shr_p_2_pr : process(clk, rst, b)
begin
if rising_edge(clk) then
if rst = '1' then
p_2_s <= b;
else
p_2_s <= '0' & p_2_s(162 downto 1);
end if;
end if;
b_s <= p_2_s(0);
end process;
 
pr_1_seq: process(clk, rst, b_s, p_1_s, r_3_s, r_2_s, r_1_s, r_0_s)
begin
if rising_edge(clk) then
if rst = '1' then
p_s <= (others => '0');
elsif b_s = '1' then
p_s <= r_3_s(47 downto 29) & r_2_s & r_1_s & r_0_s;
end if;
end if;
end process;
 
DSP_XOR_0 : dsp_xor port map (clk, p_s(47 downto 0), p_1_s(47 downto 0), r_0_s);
DSP_XOR_1 : dsp_xor port map (clk, p_s(95 downto 48), p_1_s(95 downto 48), r_1_s);
DSP_XOR_2 : dsp_xor port map (clk, p_s(143 downto 96), p_1_s(143 downto 96), r_2_s);
 
xor_in_aux_0_s <= p_s(162 downto 134) & "0000000000000000000";
xor_in_aux_1_s <= p_1_s(162 downto 134) & "0000000000000000000";
 
DSP_XOR_3 : dsp_xor port map (clk, xor_in_aux_0_s, xor_in_aux_1_s, r_3_s);
 
SHIFT_XOR_0 : shift_xor_128 port map (clk, p_1_s, m_s, c_s);
 
pr_2_seq: process(clk, a, c_s)
begin
if rising_edge(clk) then
if rst = '1' then
p_1_s <= a;
else
p_1_s <= c_s;
end if;
end if;
end process;
p <= p_s;
 
POLY_ROM_0 : poly_rom port map (clk, "0", m_s);
 
end Behavioral;
 
/b163arith/trunk/dsp_xor.vhd
0,0 → 1,129
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
library UNISIM;
use UNISIM.VComponents.all;
 
entity dsp_xor is
port (clk : in std_logic;
op_1 : in std_logic_vector(47 downto 0);
op_2 : in std_logic_vector(47 downto 0);
op_3 : out std_logic_vector(47 downto 0));
end dsp_xor;
 
architecture Behavioral of dsp_xor is
 
signal alumode_s : std_logic_vector(3 downto 0);
signal opmode_s : std_logic_vector(6 downto 0);
signal a_s : std_logic_vector(29 downto 0);
signal b_s : std_logic_vector(17 downto 0);
signal c_s : std_logic_vector(47 downto 0);
signal p_s : std_logic_vector(47 downto 0);
 
begin
 
a_s <= op_1(47 downto 18);
b_s <= op_1(17 downto 0);
c_s <= op_2;
alumode_s <= "0100";
opmode_s <= "0110011";
 
op_3 <= p_s;
 
dsp48e1_inst : dsp48e1
generic map (
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => FALSE,
USE_MULT => "NONE",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48")
port map (
ACOUT => open,
BCOUT => open,
CARRYCASCOUT => open,
CARRYOUT => open,
MULTSIGNOUT => open,
OVERFLOW => open,
P => p_s,
PATTERNBDETECT => open,
PATTERNDETECT => open,
PCOUT => open,
UNDERFLOW => open,
A => a_s,
ACIN => (others => '0'),
ALUMODE => alumode_s,
B => b_s,
BCIN => (others => '0'),
C => c_s,
CARRYCASCIN => '0',
CARRYIN => '0',
CARRYINSEL => (others => '0'),
CEA1 => '0',
CEA2 => '1',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '1',
CEC => '1',
CECARRYIN => '0',
CECTRL => '1',
CED => '0',
CEINMODE => '1',
CEM => '0',
CEP => '0',
CLK => clk,
D => (others => '0'),
INMODE => (others => '0'),
MULTSIGNIN => '0',
OPMODE => opmode_s,
PCIN => (others => '0'),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0');
end Behavioral;

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