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/bpsk_spread_spectrum_modulator_demodulator/trunk/tb_spread_bpsk_0.vhd
0,0 → 1,209
-------------------------------------------------------------------------------
-- Title : Testbench for spread_bpsk.vhd
-- Project :
-------------------------------------------------------------------------------
-- File : tb_spread_bpsk_0.vhd
-- Author : Tomasz Turek <tomasz.turek@gmail.com>
-- Company : SzuWar INC
-- Created : 22:24:52 26-03-2010
-- Last update: 09:02:29 11-05-2010
-- Platform : Xilinx ISE 10.1.03
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010 SzuWar INC
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 22:24:52 26-03-2010 1.0 szuwarek Created
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity tb_spread_bpsk_0 is
end entity tb_spread_bpsk_0;
 
architecture tb of tb_spread_bpsk_0 is
 
-------------------------------------------------------------------------------
-- Unit Under Test --
-------------------------------------------------------------------------------
component spread_bpsk is
 
generic (
iDataWidith : integer range 1 to 16 := 2;
iSingleValueSpread : integer range 2 to 255 := 17;
iTrigerType : integer range 0 to 2 := 2
);
 
port (
CLK_I : in std_logic;
RESET_I : in std_logic;
DATA_I : in std_logic_vector(iDataWidith - 1 downto 0);
DATA_VALID_I : in std_logic;
TRIGER_I : in std_logic;
SPREAD_SEQUENCE_I : in std_logic_vector(iSingleValueSpread - 1 downto 0);
DATA_O : out std_logic_vector(iDataWidith - 1 downto 0);
DATA_VALID_O : out std_logic;
READY_FOR_DATA_O : out std_logic
);
 
end component spread_bpsk;
 
-------------------------------------------------------------------------------
-- consttants --
-------------------------------------------------------------------------------
constant iDataWidith : integer range 1 to 16 := 4;
constant iSingleValueSpread : integer range 2 to 255 := 16;
constant iTrigerType : integer range 0 to 2 := 2;
constant tTs : time := 5 ns;
 
-------------------------------------------------------------------------------
-- signals --
-------------------------------------------------------------------------------
-- In --
signal CLK_I : std_logic := '0';
signal RESET_I : std_logic := '0';
signal DATA_VALID_I : std_logic := '0';
signal TRIGER_I : std_logic := '0';
-- signal DATA_I : std_logic_vector(iDataWidith - 1 downto 0) := (others => '0');
signal DATA_I : std_logic_vector(iDataWidith - 1 downto 0) := x"5";
signal SPREAD_SEQUENCE_I : std_logic_vector(iSingleValueSpread - 1 downto 0) := (others => '0');
-- signal SPREAD_SEQUENCE_I : std_logic_vector(iSingleValueSpread - 1 downto 0) := x"a5c9";
 
-- Out --
signal DATA_VALID_O : std_logic;
signal READY_FOR_DATA_O : std_logic;
signal DATA_O : std_logic_vector(iDataWidith - 1 downto 0);
 
-- Others --
signal v_count : std_logic_vector(15 downto 0) := (others => '0');
-- +1 bpsk == '1' --
signal p_one : std_logic_vector(iDataWidith - 1 downto 0) := (others => '1');
-- -1 bpsk == '0' --
signal s_one : std_logic_vector(iDataWidith - 1 downto 0) := (others => '0');
begin -- architecture tb
 
 
UUT :
spread_bpsk
 
generic map (
iDataWidith => iDataWidith,
iSingleValueSpread => iSingleValueSpread,
iTrigerType => iTrigerType
)
 
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
DATA_I => DATA_I,
DATA_VALID_I => DATA_VALID_I,
 
TRIGER_I => TRIGER_I,
SPREAD_SEQUENCE_I => SPREAD_SEQUENCE_I,
DATA_O => DATA_O,
DATA_VALID_O => DATA_VALID_O,
READY_FOR_DATA_O => READY_FOR_DATA_O
);
 
StimulationProcess : process
begin
for i in 0 to 1000000 loop
CLK_I <= not CLK_I;
 
wait for tTs;
 
end loop;
 
wait;
end process StimulationProcess;
 
T0: process (CLK_I) is
begin -- process T0
 
if rising_edge(CLK_I) then
 
case v_count is
 
when x"0002" =>
 
RESET_I <= '1';
 
TRIGER_I <= TRIGER_I;
DATA_VALID_I <= DATA_VALID_I;
DATA_I <= DATA_I;
v_count <= v_count + 1;
 
when x"0005" =>
 
RESET_I <= '0';
 
TRIGER_I <= TRIGER_I;
DATA_VALID_I <= DATA_VALID_I;
DATA_I <= DATA_I;
v_count <= v_count + 1;
 
when x"0007" =>
 
 
RESET_I <= RESET_I;
TRIGER_I <= TRIGER_I;
DATA_VALID_I <= '1';
DATA_I <= x"5";
v_count <= v_count + 1;
 
when x"0026" =>
 
RESET_I <= RESET_I;
TRIGER_I <= TRIGER_I;
DATA_VALID_I <= '0';
DATA_I <= DATA_I;
v_count <= v_count;
 
when x"0027" =>
 
 
RESET_I <= RESET_I;
TRIGER_I <= TRIGER_I;
DATA_VALID_I <= '1';
DATA_I <= x"a";
v_count <= v_count + 1;
 
when x"0040" =>
 
 
RESET_I <= RESET_I;
TRIGER_I <= TRIGER_I;
DATA_VALID_I <= '0';
DATA_I <= DATA_I;
v_count <= v_count;
when others =>
 
 
RESET_I <= RESET_I;
TRIGER_I <= TRIGER_I;
DATA_VALID_I <= DATA_VALID_I;
DATA_I <= DATA_I + 1;
-- DATA_I <= DATA_I xor p_one;
v_count <= v_count + 1;
end case;
end if;
end process T0;
end architecture tb;
 
/bpsk_spread_spectrum_modulator_demodulator/trunk/ss_bpsk.do
0,0 → 1,54
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal -radix unsigned /tb_spread_bpsk_0/v_count
add wave -noupdate -format Literal /tb_spread_bpsk_0/v_count
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/clk_i
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/reset_i
add wave -noupdate -format Literal -radix unsigned /tb_spread_bpsk_0/uut/data_i
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/fifo_ce
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/data_valid_i
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/triger_type_i
add wave -noupdate -format Literal /tb_spread_bpsk_0/uut/spread_sequence_i
add wave -noupdate -color {Orange Red} -format Logic /tb_spread_bpsk_0/uut/data_valid_o
add wave -noupdate -color Gold -format Logic /tb_spread_bpsk_0/uut/data_procesing
add wave -noupdate -format Literal -radix unsigned -expand /tb_spread_bpsk_0/uut/v_fifo_data_spread
add wave -noupdate -format Literal -radix unsigned /tb_spread_bpsk_0/uut/v_spread_count
add wave -noupdate -format Literal /tb_spread_bpsk_0/uut/data_o
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/ready_for_data_o
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/fifo_read
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/fifo_empty
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/rfd
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/spread_triger
add wave -noupdate -format Literal -radix unsigned /tb_spread_bpsk_0/uut/v_fifo_data
add wave -noupdate -format Literal -radix hexadecimal /tb_spread_bpsk_0/uut/v_delay_counter
add wave -noupdate -format Literal /tb_spread_bpsk_0/uut/i_delay_counter
add wave -noupdate -format Literal -radix unsigned /tb_spread_bpsk_0/uut/v_data_in
add wave -noupdate -format Literal /tb_spread_bpsk_0/uut/g0__3/fifo_in/shift_reg
add wave -noupdate -color Gold -format Literal /tb_spread_bpsk_0/uut/g0__2/fifo_in/shift_reg
add wave -noupdate -format Literal /tb_spread_bpsk_0/uut/g0__1/fifo_in/shift_reg
add wave -noupdate -color Gold -format Literal /tb_spread_bpsk_0/uut/g0__0/fifo_in/shift_reg
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/g0__3/fifo_in/q15
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/g0__2/fifo_in/q15
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/g0__1/fifo_in/q15
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/g0__0/fifo_in/q15
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/g0__3/fifo_in/q
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/g0__2/fifo_in/q
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/g0__1/fifo_in/q
add wave -noupdate -format Logic /tb_spread_bpsk_0/uut/g0__0/fifo_in/q
add wave -noupdate -color Firebrick -format Logic /tb_spread_bpsk_0/uut/fifo_read
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1430829 ps} 0}
configure wave -namecolwidth 355
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {4200 ns}
/bpsk_spread_spectrum_modulator_demodulator/trunk/spread_bpsk.vhd
0,0 → 1,265
-------------------------------------------------------------------------------
-- Title : Spread using spreading sequence based on BPSK constelation.
-- Project :
-------------------------------------------------------------------------------
-- File : spread_bpsk.vhd
-- Author : Tomasz Turek <tomasz.turek@gmail.com>
-- Company : SzuWar INC
-- Created : 21:37:13 20-03-2010
-- Last update: 09:03:26 11-05-2010
-- Platform : Xilinx ISE 10.1.03
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010 SzuWar INC
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 21:37:13 20-03-2010 1.0 szuwarek Created
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
Library UNISIM;
use UNISIM.vcomponents.all;
 
entity spread_bpsk is
 
generic (
iDataWidith : integer range 1 to 16 := 2;
iSingleValueSpread : integer range 2 to 255 := 17;
iTrigerType : integer range 0 to 2 := 2
);
 
port (
CLK_I : in std_logic;
RESET_I : in std_logic;
DATA_I : in std_logic_vector(iDataWidith - 1 downto 0);
DATA_VALID_I : in std_logic;
TRIGER_I : in std_logic;
SPREAD_SEQUENCE_I : in std_logic_vector(iSingleValueSpread - 1 downto 0);
DATA_O : out std_logic_vector(iDataWidith - 1 downto 0);
DATA_VALID_O : out std_logic;
READY_FOR_DATA_O : out std_logic
);
 
end entity spread_bpsk;
 
architecture rtl of spread_bpsk is
-------------------------------------------------------------------------------
-- signals --
-------------------------------------------------------------------------------
signal fifo_ce : std_logic;
signal fifo_read : std_logic;
signal FF_fifo_read : std_logic;
signal fifo_empty : std_logic;
signal rfd : std_logic;
signal data_processing : std_logic;
signal v_data_processing : std_logic_vector(1 downto 0);
signal spread_triger : std_logic;
signal v_fifo_data : std_logic_vector(iDataWidith - 1 downto 0);
signal v_data_in : std_logic_vector(iDataWidith - 1 downto 0);
signal v_fifo_data_spread : std_logic_vector(iDataWidith - 1 downto 0);
signal v_spread_count : std_logic_vector(7 downto 0);
signal v_delay_counter : std_logic_vector(3 downto 0) := x"0";
signal i_delay_counter : integer range 0 to 16 := 0;
begin -- architecture rtl
 
-------------------------------------------------------------------------------
-- FIFO IN --
-------------------------------------------------------------------------------
 
rfd <= '1' when v_delay_counter < x"f" else '0';
READY_FOR_DATA_O <= rfd;
fifo_empty <= '1' when i_delay_counter = 0 else '0';
fifo_ce <= '1' when (DATA_VALID_I = '1') and (fifo_read = '1') else
DATA_VALID_I and rfd ;
 
DATA_VALID_O <= v_data_processing(0);
v_data_in <= DATA_I when fifo_ce = '1' else
(others => 'Z');
G0: for i in 0 to (iDataWidith - 1) generate
 
FIFO_IN :
SRLC16E
port map
(
Q => v_fifo_data(i), -- SRL data output
A0 => v_delay_counter(0), -- Select[0] input
A1 => v_delay_counter(1), -- Select[1] input
A2 => v_delay_counter(2), -- Select[2] input
A3 => v_delay_counter(3), -- Select[3] input
CE => fifo_ce, -- Clock enable input
CLK => CLK_I, -- Clock input
D => v_data_in(i) -- SRL data input
);
end generate G0;
 
P0: process (CLK_I) is
begin -- process P0
 
if rising_edge(CLK_I) then
 
if RESET_I = '1' then
 
i_delay_counter <= 0;
v_delay_counter <= x"0";
else
if (DATA_VALID_I = '1') and (fifo_read = '0') and (rfd = '1') then
 
if i_delay_counter < 1 then
i_delay_counter <= i_delay_counter + 1;
v_delay_counter <= x"0";
 
else
 
i_delay_counter <= i_delay_counter + 1;
v_delay_counter <= v_delay_counter + 1;
end if;
 
elsif (DATA_VALID_I = '0') and (fifo_read = '1') and (fifo_empty = '0') then
 
if ((i_delay_counter < 2) and (i_delay_counter > 0)) then
i_delay_counter <= i_delay_counter - 1;
v_delay_counter <= x"0";
 
else
 
i_delay_counter <= i_delay_counter - 1;
v_delay_counter <= v_delay_counter - 1;
end if;
 
else
 
i_delay_counter <= i_delay_counter;
v_delay_counter <= v_delay_counter;
end if;
end if;
end if;
end process P0;
-------------------------------------------------------------------------------
-- FIFO IN --
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- Triger --
-------------------------------------------------------------------------------
P1: process (CLK_I) is
begin -- process P1
 
if rising_edge(CLK_I) then
 
if RESET_I = '1' then
 
 
else
 
if iTrigerType = 0 then -- ce
 
triger <= TRIGER_I;
end if;
end if;
end if;
end process P1;
-------------------------------------------------------------------------------
-- Triger --
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- SPREAD --
-------------------------------------------------------------------------------
P2: process (CLK_I) is
begin -- process P2
 
if rising_edge(CLK_I) then
 
if RESET_I = '1' then
 
data_processing <= '0';
v_data_processing <= "00";
fifo_read <= '0';
FF_fifo_read <= '0';
DATA_O <= (others => '0');
v_spread_count <= (others => '0');
v_fifo_data_spread <= (others => '0');
else
 
v_data_processing <= v_data_processing(0) & data_processing;
FF_fifo_read <= fifo_read;
if ((fifo_empty = '0') and (data_processing = '0')) then
 
data_processing <= '1';
fifo_read <= '1';
v_spread_count <= (others => '0');
v_fifo_data_spread <= v_fifo_data;
 
else
 
if v_spread_count = conv_std_logic_vector(iSingleValueSpread - 1 , 8) then
 
v_spread_count <= v_spread_count;
 
data_procesing <= '0';
else
 
v_spread_count <= v_spread_count + 1;
end if;
 
fifo_read <= '0';
for i in 0 to iDataWidith - 1 loop
if v_fifo_data_spread(i) = '1' then
 
DATA_O(i) <= SPREAD_SEQUENCE_I(conv_integer(v_spread_count));
elsif v_fifo_data_spread(i) = '0' then
 
DATA_O(i) <= not SPREAD_SEQUENCE_I(conv_integer(v_spread_count));
end if;
 
end loop; -- i
end if;
end if;
end if;
end process P2;
-------------------------------------------------------------------------------
-- SPREAD --
-------------------------------------------------------------------------------
end architecture rtl;

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