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URL https://opencores.org/ocsvn/can/can/trunk

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    from Rev 129 to Rev 130
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Rev 129 → Rev 130

/trunk/bench/verilog/can_testbench.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.37 2003/09/30 20:53:58 mohor
// Fixing the core to be Bosch VHDL Reference compatible.
//
// Revision 1.36 2003/08/20 10:03:20 mohor
// Artisan RAMs added.
//
261,11 → 264,9
`ifdef CAN_BIST
,
// debug chain signals
.scanb_rst(1'b1), // bist scan reset
.scanb_clk(1'b0), // bist scan clock
.scanb_si(1'b0), // bist scan serial in
.scanb_so(), // bist scan serial out
.scanb_en(1'b0) // bist scan shift enable
.mbist_si_i(1'b0), // bist scan serial in
.mbist_so_o(), // bist scan serial out
.mbist_ctrl_i(3'b001) // mbist scan {enable, clock, reset}
`endif
);
 
/trunk/rtl/verilog/can_defines.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2003/09/05 12:46:42 mohor
// ALTERA_RAM supported.
//
// Revision 1.10 2003/08/14 16:04:52 simons
// Artisan ram instances added.
//
105,3 → 108,6
 
// Uncomment the following line when RAM BIST is needed (ASIC implementation)
//`define CAN_BIST // Bist (for ASIC implementation)
 
/* width of MBIST control bus */
`define CAN_MBIST_CTRL_WIDTH 3
/trunk/rtl/verilog/can_top.v
50,6 → 50,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.45 2003/09/30 00:55:13 mohor
// Error counters fixed to be compatible with Bosch VHDL reference model.
// Small synchronization changes.
//
// Revision 1.44 2003/09/25 18:55:49 mohor
// Synchronization changed, error counters fixed.
//
232,11 → 236,9
`ifdef CAN_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
 
287,11 → 289,9
 
// Bist
`ifdef CAN_BIST
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
reg data_out_fifo_selected;
730,11 → 730,9
`ifdef CAN_BIST
,
/* BIST signals */
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en)
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i)
`endif
);
 
/trunk/rtl/verilog/can_fifo.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.23 2003/09/05 12:46:41 mohor
// ALTERA_RAM supported.
//
// Revision 1.22 2003/08/20 09:59:16 mohor
// Artisan RAM fixed (when not using BIST).
//
151,11 → 154,9
 
`ifdef CAN_BIST
,
scanb_rst,
scanb_clk,
scanb_si,
scanb_so,
scanb_en
mbist_si_i,
mbist_so_o,
mbist_ctrl_i
`endif
);
 
177,12 → 178,10
output [6:0] info_cnt;
 
`ifdef CAN_BIST
input scanb_rst;
input scanb_clk;
input scanb_si;
output scanb_so;
input scanb_en;
wire scanb_s_0;
input mbist_si_i;
output mbist_so_o;
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
wire mbist_s_0;
`endif
 
`ifdef ALTERA_RAM
578,11 → 577,9
`ifdef CAN_BIST
,
// debug chain signals
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_s_0),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_s_0),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
603,11 → 600,9
`ifdef CAN_BIST
,
// debug chain signals
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_s_0),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_s_0),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
 
636,11 → 631,9
.Q (data_out),
.REN (~fifo_selected),
.WEN (~(wr & (~fifo_full))),
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_s_0),
.scanb_en (scanb_en)
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_s_0),
.mbist_ctrl_i (mbist_ctrl_i)
);
art_hstp_64x4_bist info_fifo
(
652,11 → 645,9
.Q (length_info),
.REN (1'b0),
.WEN (~(write_length_info & (~info_full) | initialize_memories)),
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_s_0),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.mbist_si_i (mbist_s_0),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
);
`else
art_hsdp_64x8 fifo
/trunk/rtl/verilog/can_bsp.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.45 2003/09/30 21:14:33 mohor
// Error counters changed.
//
// Revision 1.44 2003/09/30 00:55:12 mohor
// Error counters fixed to be compatible with Bosch VHDL reference model.
// Small synchronization changes.
336,11 → 339,9
/* Bist */
`ifdef CAN_BIST
,
scanb_rst,
scanb_clk,
scanb_si,
scanb_so,
scanb_en
mbist_si_i,
mbist_so_o,
mbist_ctrl_i
`endif
);
 
469,11 → 470,9
 
/* Bist */
`ifdef CAN_BIST
input scanb_rst;
input scanb_clk;
input scanb_si;
output scanb_so;
input scanb_en;
input mbist_si_i;
output mbist_so_o;
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
reg reset_mode_q;
1432,11 → 1431,9
 
`ifdef CAN_BIST
,
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en)
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i)
`endif
);
 

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