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- This comparison shows the changes necessary to convert path
/
- from Rev 136 to Rev 137
- ↔ Reverse comparison
Rev 136 → Rev 137
/trunk/rtl/verilog/can_defines.v
17,7 → 17,7
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002, 2003 Authors //// |
//// Copyright (C) 2002, 2003, 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2003/10/17 05:55:20 markom |
// mbist signals updated according to newest convention |
// |
// Revision 1.11 2003/09/05 12:46:42 mohor |
// ALTERA_RAM supported. |
// |
/trunk/rtl/verilog/can_register_syn.v
17,7 → 17,7
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002, 2003 Authors //// |
//// Copyright (C) 2002, 2003, 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2003/03/11 16:31:58 mohor |
// timescale.v is used for simulation only. |
// |
// Revision 1.3 2003/02/09 02:24:33 mohor |
// Bosch license warning added. Error counters finished. Overload frames |
// still need to be fixed. |
/trunk/rtl/verilog/can_register_asyn.v
17,7 → 17,7
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002, 2003 Authors //// |
//// Copyright (C) 2002, 2003, 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2003/03/20 16:58:50 mohor |
// unix. |
// |
// Revision 1.4 2003/03/11 16:32:34 mohor |
// timescale.v is used for simulation only. |
// |
/trunk/rtl/verilog/can_btl.v
17,7 → 17,7
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002, 2003 Authors //// |
//// Copyright (C) 2002, 2003, 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
50,6 → 50,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.27 2003/09/30 00:55:13 mohor |
// Error counters fixed to be compatible with Bosch VHDL reference model. |
// Small synchronization changes. |
// |
// Revision 1.26 2003/09/25 18:55:49 mohor |
// Synchronization changed, error counters fixed. |
// |
300,7 → 304,6
else |
tx_point <=#Tp ~tx_point & seg2 & ( clk_en & (quant_cnt[2:0] == time_segment2) |
| clk_en_q & (resync | hard_sync) |
// | clk_en & (resync | hard_sync) |
); // When transmitter we should transmit as soon as possible. |
end |
|
370,7 → 373,6
begin |
if (rst) |
delay <= 4'h0; |
// else if (resync & seg1 & (~transmitting | transmitting & tx_next_sp)) // when transmitting 0 with positive error delay is set to 0 |
else if (resync & seg1 & (~transmitting | transmitting & (tx_next_sp | (tx & (~rx))))) // when transmitting 0 with positive error delay is set to 0 |
delay <=#Tp (quant_cnt > {2'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1); |
else if (go_sync | go_seg1) |
455,10 → 457,8
begin |
if (rst) |
hard_sync_blocked <=#Tp 1'b0; |
// else if (hard_sync & clk_en_q | transmitting & transmitter & tx_point) |
else if (hard_sync & clk_en_q | transmitting & transmitter & tx_point & (~tx_next)) |
hard_sync_blocked <=#Tp 1'b1; |
// else if (go_rx_inter) |
else if (go_rx_inter | (rx_idle | rx_inter) & sample_point & sampled_bit) // When a glitch performed synchronization |
hard_sync_blocked <=#Tp 1'b0; |
end |
/trunk/rtl/verilog/can_fifo.v
17,7 → 17,7
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002, 2003 Authors //// |
//// Copyright (C) 2002, 2003, 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
50,6 → 50,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.25 2003/10/23 16:52:17 mohor |
// Active high/low problem when Altera devices are used. Bug fixed by |
// Rojhalat Ibrahim. |
// |
// Revision 1.24 2003/10/17 05:55:20 markom |
// mbist signals updated according to newest convention |
// |
465,19 → 469,6
`else |
`ifdef XILINX_RAM |
|
/* |
ram_64x8_sync fifo |
( |
.addra(wr_pointer), |
.addrb(read_address), |
.clka(clk), |
.clkb(clk), |
.dina(data_in), |
.doutb(data_out), |
.wea(wr & (~fifo_full)) |
); |
*/ |
|
RAMB4_S8_S8 fifo |
( |
.DOA(), |
497,19 → 488,6
); |
|
|
|
/* |
ram_64x4_sync info_fifo |
( |
.addra(wr_info_pointer), |
.addrb(rd_info_pointer), |
.clka(clk), |
.clkb(clk), |
.dina(len_cnt), |
.doutb(length_info), |
.wea(write_length_info & (~info_full)) |
); |
*/ |
RAMB4_S4_S4 info_fifo |
( |
.DOA(), |
528,20 → 506,7
.WEB(1'b0) |
); |
|
/* |
ram_64x1_sync overrun_fifo |
( |
.addra(wr_info_pointer), |
.addrb(rd_info_pointer), |
.clka(clk), |
.clkb(clk), |
.dina(latch_overrun | (wr & fifo_full)), |
.doutb(overrun), |
.wea(write_length_info & (~info_full)) |
); |
*/ |
|
|
RAMB4_S1_S1 overrun_fifo |
( |
.DOA(), |
/trunk/rtl/verilog/can_register.v
17,7 → 17,7
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002, 2003 Authors //// |
//// Copyright (C) 2002, 2003, 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2003/03/20 16:58:50 mohor |
// unix. |
// |
// Revision 1.4 2003/03/11 16:32:34 mohor |
// timescale.v is used for simulation only. |
// |
/trunk/rtl/verilog/can_crc.v
17,7 → 17,7
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002, 2003 Authors //// |
//// Copyright (C) 2002, 2003, 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2003/07/16 13:16:51 mohor |
// Fixed according to the linter. |
// |
// Revision 1.3 2003/02/10 16:02:11 mohor |
// CAN is working according to the specification. WB interface and more |
// registers (status, IRQ, ...) needs to be added. |
/trunk/rtl/verilog/can_register_asyn_syn.v
17,7 → 17,7
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002, 2003 Authors //// |
//// Copyright (C) 2002, 2003, 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2003/03/20 16:52:43 mohor |
// unix. |
// |
// Revision 1.4 2003/03/11 16:32:34 mohor |
// timescale.v is used for simulation only. |
// |
/trunk/rtl/verilog/can_ibo.v
17,7 → 17,7
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002, 2003 Authors //// |
//// Copyright (C) 2002, 2003, 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
50,6 → 50,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2003/02/09 02:24:33 mohor |
// Bosch license warning added. Error counters finished. Overload frames |
// still need to be fixed. |
// |
// Revision 1.1 2003/02/04 14:34:52 mohor |
// *** empty log message *** |
// |