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Rev 139 → Rev 140
/trunk/bench/verilog/can_testbench.v
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.39 2004/03/18 17:15:26 igorm |
// Signal bus_off_on added. |
// |
// Revision 1.38 2003/10/17 05:55:18 markom |
// mbist signals updated according to newest convention |
// |
275,7 → 278,7
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// Combining tx with the output enable signal. |
assign tx = tx_oen? 1'bz : tx_i; |
assign tx = bus_off_on? tx_i : 1'bz; |
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`ifdef CAN_WISHBONE_IF |
// Generate wishbone clock signal 10 MHz |