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URL https://opencores.org/ocsvn/can/can/trunk

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Rev 140 → Rev 141

/trunk/rtl/verilog/can_defines.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2004/02/08 14:28:03 mohor
// Header changed.
//
// Revision 1.12 2003/10/17 05:55:20 markom
// mbist signals updated according to newest convention
//
97,7 → 100,7
// `define CAN_WISHBONE_IF
 
// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)
`define ACTEL_APA_RAM
// `define ACTEL_APA_RAM
 
// Uncomment following line if you want to use CAN in Altera devices (embedded memory used)
// `define ALTERA_RAM
113,4 → 116,4
//`define CAN_BIST // Bist (for ASIC implementation)
 
/* width of MBIST control bus */
`define CAN_MBIST_CTRL_WIDTH 3
//`define CAN_MBIST_CTRL_WIDTH 3
/trunk/rtl/verilog/can_btl.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.28 2004/02/08 14:25:26 mohor
// Header changed.
//
// Revision 1.27 2003/09/30 00:55:13 mohor
// Error counters fixed to be compatible with Bosch VHDL reference model.
// Small synchronization changes.
222,8 → 225,6
output tx_point;
output hard_sync;
 
 
 
reg [6:0] clk_cnt;
reg clk_en;
reg clk_en_q;
250,12 → 251,12
wire resync;
 
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
assign hard_sync = (rx_idle | rx_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization
assign resync = (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization
 
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
303,11 → 304,12
tx_point <= 1'b0;
else
tx_point <=#Tp ~tx_point & seg2 & ( clk_en & (quant_cnt[2:0] == time_segment2)
| clk_en_q & (resync | hard_sync)
| (clk_en | clk_en_q) & (resync | hard_sync)
); // When transmitter we should transmit as soon as possible.
end
 
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
SJW is reached */
always @ (posedge clk or posedge rst)
403,6 → 405,11
sampled_bit_q <= 1'b1;
sample_point <= 1'b0;
end
else if (go_error_frame)
begin
sampled_bit_q <=#Tp sampled_bit;
sample_point <=#Tp 1'b0;
end
else if (clk_en_q & (~hard_sync))
begin
if (seg1 & (quant_cnt == (time_segment1 + delay)))
457,7 → 464,7
begin
if (rst)
hard_sync_blocked <=#Tp 1'b0;
else if (hard_sync & clk_en_q | transmitting & transmitter & tx_point & (~tx_next))
else if (hard_sync & clk_en_q | (transmitting & transmitter | go_tx) & tx_point & (~tx_next))
hard_sync_blocked <=#Tp 1'b1;
else if (go_rx_inter | (rx_idle | rx_inter) & sample_point & sampled_bit) // When a glitch performed synchronization
hard_sync_blocked <=#Tp 1'b0;
468,3 → 475,4
 
 
endmodule
 
/trunk/rtl/verilog/can_bsp.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.47 2004/02/08 14:24:10 mohor
// Error counters changed.
//
// Revision 1.46 2003/10/17 05:55:20 markom
// mbist signals updated according to newest convention
//
374,9 → 377,8
input single_shot_transmission;
output tx_state;
output tx_state_q;
input overload_request;
output overload_frame; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
// be send in a row. This is not implemented, yet, because host can not send an overload request.
input overload_request; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
output overload_frame; // be send in a row. This is not implemented, yet, because host can not send an overload request.
 
/* Arbitration Lost Capture Register */
input read_arbitration_lost_capture_reg;
579,7 → 581,10
reg [7:0] error_capture_code;
reg [7:6] error_capture_code_type;
reg error_capture_code_blocked;
reg tx_next;
reg first_compare_bit;
 
 
wire [4:0] error_capture_code_segment;
wire error_capture_code_direction;
 
1152,11 → 1157,8
 
 
// Conditions for form error
assign form_err = sample_point & ( ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
( rx_ack_lim & (~sampled_bit) ) |
// ((eof_cnt < 3'd6)& rx_eof & (~sampled_bit) & (~tx_state) ) |
// ( & rx_eof & (~sampled_bit) & tx_state )
// ((eof_cnt < 3'd6)& rx_eof & (~sampled_bit) & (~tx_state) )
assign form_err = sample_point & ( ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
( rx_ack_lim & (~sampled_bit) ) |
((eof_cnt < 3'd6)& rx_eof & (~sampled_bit) & (~transmitter) ) |
( & rx_eof & (~sampled_bit) & transmitter )
);
1380,7 → 1382,7
6'b1_1_1_100 : data_for_fifo = {id[4:0], 3'h0}; // extended mode, extended format header
6'b1_1_0_000 : data_for_fifo = {1'b0, rtr1, 2'h0, data_len}; // extended mode, standard format header
6'b1_1_0_001 : data_for_fifo = id[10:3]; // extended mode, standard format header
6'b1_1_0_010 : data_for_fifo = {id[2:0], 5'h0}; // extended mode, standard format header
6'b1_1_0_010 : data_for_fifo = {id[2:0], rtr1, 4'h0}; // extended mode, standard format header
6'b1_0_x_000 : data_for_fifo = id[10:3]; // normal mode header
6'b1_0_x_001 : data_for_fifo = {id[2:0], rtr1, data_len}; // normal mode header
default : data_for_fifo = tmp_fifo[data_cnt - {1'b0, header_len}]; // data
1452,7 → 1454,7
 
 
 
assign error_flag_over = ((~node_error_passive) & sample_point & (error_cnt1 == 3'd7) | node_error_passive & sample_point & (passive_cnt == 3'h5)) & (~enable_error_cnt2);
assign error_flag_over = ((~node_error_passive) & sample_point & (error_cnt1 == 3'd7) | node_error_passive & sample_point & (passive_cnt == 3'h6)) & (~enable_error_cnt2);
 
 
always @ (posedge clk or posedge rst)
1503,20 → 1505,31
always @ (posedge clk or posedge rst)
begin
if (rst)
passive_cnt <= 3'h0;
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
passive_cnt <=#Tp 3'h0;
else if (sample_point & (passive_cnt < 3'h5))
passive_cnt <= 3'h1;
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame | first_compare_bit)
passive_cnt <=#Tp 3'h1;
else if (sample_point & (passive_cnt < 3'h6))
begin
if (error_frame_q & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
if (error_frame & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
passive_cnt <=#Tp passive_cnt + 1'b1;
else
passive_cnt <=#Tp 3'h0;
passive_cnt <=#Tp 3'h1;
end
end
 
 
// When comparing 6 equal bits, first is always equal
always @ (posedge clk or posedge rst)
begin
if (rst)
first_compare_bit <= 1'b0;
else if (go_error_frame)
first_compare_bit <=#Tp 1'b1;
else if (sample_point)
first_compare_bit <= 1'b0;
end
 
 
// Transmitting overload frame.
always @ (posedge clk or posedge rst)
begin
1590,8 → 1603,8
assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
 
 
reg tx_next;
always @ (reset_mode or node_bus_off or tx_state or bit_de_stuff_tx or tx_bit or tx_q or
 
always @ (reset_mode or node_bus_off or tx_state or go_tx or bit_de_stuff_tx or tx_bit or tx_q or
send_ack or go_overload_frame or overload_frame or overload_cnt1 or
go_error_frame or error_frame or error_cnt1 or node_error_passive)
begin
1618,7 → 1631,7
else
tx_next = 1'b1;
end
else if (tx_state) // Transmitting message
else if (go_tx | tx_state) // Transmitting message
tx_next = ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
else if (send_ack) // Acknowledge
tx_next = 1'b0;
1740,7 → 1753,7
tx_pointer <= 6'h0;
else if (rst_tx_pointer)
tx_pointer <=#Tp 6'h0;
else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
else if (go_early_tx | (tx_point & (tx_state | go_tx) & (~bit_de_stuff_tx)))
tx_pointer <=#Tp tx_pointer + 1'b1;
end
 
1760,10 → 1773,9
 
 
 
assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
assign go_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & (go_early_tx | rx_idle);
assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend | (susp_cnt == 3'h7)) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
assign go_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend | (sample_point & (susp_cnt == 3'h7))) & (go_early_tx | rx_idle);
 
 
// go_early_tx latched (for proper bit_de_stuff generation)
always @ (posedge clk or posedge rst)
begin
1805,7 → 1817,7
transmitter <= 1'b0;
else if (go_tx)
transmitter <=#Tp 1'b1;
else if (reset_mode | go_rx_idle)
else if (reset_mode | go_rx_idle | suspend & go_rx_id1)
transmitter <=#Tp 1'b0;
end
1819,7 → 1831,7
transmitting <= 1'b0;
else if (go_error_frame | go_overload_frame | go_tx | send_ack)
transmitting <=#Tp 1'b1;
else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state) | rx_ack_lim)
else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state))
transmitting <=#Tp 1'b0;
end
 
1857,8 → 1869,6
end
 
 
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
1874,10 → 1884,8
begin
if (rst)
arbitration_lost <= 1'b0;
// else if (go_rx_idle | error_frame | reset_mode)
else if (go_rx_idle | error_frame_ended | reset_mode)
arbitration_lost <=#Tp 1'b0;
// else if (tx_state & sample_point & tx & arbitration_field)
else if (transmitter & sample_point & tx & arbitration_field)
arbitration_lost <=#Tp (~sampled_bit);
end
1940,7 → 1948,6
rx_err_cnt <=#Tp 9'h0;
else
begin
// if ((~listen_only_mode) & (~transmitter | arbitration_lost | suspend))
if ((~listen_only_mode) & (~transmitter | arbitration_lost))
begin
if (go_rx_ack_lim & (~go_error_frame) & (~crc_err) & (rx_err_cnt > 9'h0))
1952,13 → 1959,11
end
else if (rx_err_cnt < 9'd128)
begin
if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
// else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked) ) | // 2
// else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) ) | // 2
else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) ) | // 2
(go_error_frame & rule5 ) | // 5
(sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) ) | // 2
(go_error_frame & rule5 ) | // 5
(sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
)
rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
end
1976,17 → 1981,16
else
begin
if (set_reset_mode)
tx_err_cnt <=#Tp 9'd127;
tx_err_cnt <=#Tp 9'd128;
else if ((tx_err_cnt > 9'd0) & (tx_successful | bus_free))
tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
// else if (transmitter & (~arbitration_lost) & (~suspend))
else if (transmitter & (~arbitration_lost))
begin
if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) | // 6
(go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
(go_error_frame & (~(transmitter & node_error_passive & ack_err)) & (~(transmitter & stuff_err & arbitration_field & sample_point & tx & (~sampled_bit))) ) | // 3
(error_frame & rule3_exc1_2 ) //| // 3
// (go_error_frame & (~(transmitter & stuff_err & arbitration_field & sample_point & tx & (~sampled_bit))) ) //
(go_error_frame & (~(transmitter & node_error_passive & ack_err)) & (~(transmitter & stuff_err &
arbitration_field & sample_point & tx & (~sampled_bit))) ) | // 3
(error_frame & rule3_exc1_2 ) // 3
)
tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
end
2140,3 → 2144,4
 
 
endmodule
 
/trunk/rtl/verilog/README.txt
0,0 → 1,69
//////////////////////////////////////////////////////////////////////
//// ////
//// README.txt ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
//
 
 
This CAN Controller was tested with the Bosch VHDL Reference Model and
passed all the tests. Because of the licensing issue it can not be
published on the Opencores web site.
 
The Can Controller was also implemented in real HW (12 boards
were constantly talking to each other).
 
The included test bench is not a real test bench and should be improved.
However a volunteer is needed for such a job. I can provide some help
but am not willing to write it by myself.
 
Best regards,
Igor Mohor
 
 
/trunk/rtl/verilog/can_registers.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.31 2003/09/25 18:55:49 mohor
// Synchronization changed, error counters fixed.
//
// Revision 1.30 2003/07/16 15:19:34 mohor
// Fixed according to the linter.
// Case statement for data_out joined.
759,7 → 762,6
reg [2:0] clkout_div;
reg [2:0] clkout_cnt;
reg clkout_tmp;
//reg clkout;
 
can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_7
( .data_in(data_in[7]),
830,18 → 832,6
end
 
 
/*
//always @ (cd or clk or clkout_tmp or clock_off)
always @ (cd or clkout_tmp or clock_off)
begin
if (clock_off)
clkout <=#Tp 1'b1;
// else if (&cd)
// clkout <=#Tp clk;
else
clkout <=#Tp clkout_tmp;
end
*/
assign clkout = clock_off ? 1'b1 : ((&cd)? clk : clkout_tmp);
 
 
/trunk/sim/rtl_sim/run/run_sim.scr
33,18 → 33,18
echo "../../../rtl/verilog/"$filename >> ncvlog.args
end
 
foreach filename ( `cat ../bin/memory_file_list` )
echo "../../../bench/verilog/"$filename >> ncvlog.args
end
#foreach filename ( `cat ../bin/memory_file_list` )
# echo "../../../bench/verilog/"$filename >> ncvlog.args
#end
 
foreach filename ( `cat ../bin/sim_file_list` )
echo "../../../bench/verilog/"$filename >> ncvlog.args
end
 
echo "../../../../bist/rtl/verilog/bist.v" >> ncvlog.args
echo "../../../../bist/rtl/verilog/bist_dp_top.v" >> ncvlog.args
echo "../../../../bist/rtl/verilog/bist_sp_top.v" >> ncvlog.args
echo "../../../../bist/rtl/verilog/bist_tp_top.v" >> ncvlog.args
#echo "../../../../bist/rtl/verilog/bist.v" >> ncvlog.args
#echo "../../../../bist/rtl/verilog/bist_dp_top.v" >> ncvlog.args
#echo "../../../../bist/rtl/verilog/bist_sp_top.v" >> ncvlog.args
#echo "../../../../bist/rtl/verilog/bist_tp_top.v" >> ncvlog.args
 
ncvlog -f ncvlog.args
 

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