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https://opencores.org/ocsvn/can/can/trunk
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- This comparison shows the changes necessary to convert path
/
- from Rev 146 to Rev 147
- ↔ Reverse comparison
Rev 146 → Rev 147
/trunk/rtl/verilog/can_top.v
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.47 2004/02/08 14:53:54 mohor |
// Header changed. Address latched to posedge. bus_off_on signal added. |
// |
// Revision 1.46 2003/10/17 05:55:20 markom |
// mbist signals updated according to newest convention |
// |
300,7 → 303,6
reg data_out_fifo_selected; |
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wire irq_o; |
wire [7:0] data_out_fifo; |
wire [7:0] data_out_regs; |
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447,7 → 449,7
.addr(addr), |
.data_in(data_in), |
.data_out(data_out_regs), |
.irq(irq_o), |
.irq_n(irq_on), |
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.sample_point(sample_point), |
.transmitting(transmitting), |
555,7 → 557,6
); |
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assign irq_on = ~irq_o; |
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/* Connecting can_btl module */ |
/trunk/rtl/verilog/can_registers.v
50,6 → 50,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.32 2004/05/12 15:58:41 igorm |
// Core improved to pass all tests with the Bosch VHDL Reference system. |
// |
// Revision 1.31 2003/09/25 18:55:49 mohor |
// Synchronization changed, error counters fixed. |
// |
165,7 → 168,7
addr, |
data_in, |
data_out, |
irq, |
irq_n, |
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sample_point, |
transmitting, |
290,7 → 293,7
output [7:0] data_out; |
reg [7:0] data_out; |
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output irq; |
output irq_n; |
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input sample_point; |
input transmitting; |
416,6 → 419,7
reg transmit_buffer_status; |
reg single_shot_transmission; |
reg self_rx_request; |
reg irq_n; |
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// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed. |
wire data_overrun_irq_en; |
424,6 → 428,7
wire receive_irq_en; |
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wire [7:0] irq_reg; |
wire irq; |
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wire we_mode = cs & we & (addr == 8'd0); |
wire we_command = cs & we & (addr == 8'd1); |
1224,6 → 1229,15
assign irq = data_overrun_irq | transmit_irq | receive_irq | error_irq | bus_error_irq | arbitration_lost_irq | error_passive_irq; |
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always @ (posedge clk or posedge rst) |
begin |
if (rst) |
irq_n <= 1'b1; |
else if (read_irq_reg) |
irq_n <=#Tp 1'b1; |
else if (irq) |
irq_n <=#Tp 1'b0; |
end |
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