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Rev 151 → Rev 152

/trunk/rtl/verilog/can_fifo.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.26 2004/02/08 14:30:57 mohor
// Header changed.
//
// Revision 1.25 2003/10/23 16:52:17 mohor
// Active high/low problem when Altera devices are used. Bug fixed by
// Rojhalat Ibrahim.
264,7 → 267,7
else if (write_length_info & (~info_full) | initialize_memories)
wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
else if (reset_mode)
wr_info_pointer <=#Tp 6'h0;
wr_info_pointer <=#Tp rd_info_pointer;
end
 
 
274,8 → 277,6
begin
if (rst)
rd_info_pointer <= 6'h0;
else if (reset_mode)
rd_info_pointer <=#Tp 6'h0;
else if (release_buffer & (~fifo_empty))
rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
288,8 → 289,6
rd_pointer <= 5'h0;
else if (release_buffer & (~fifo_empty))
rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
else if (reset_mode)
rd_pointer <=#Tp 5'h0;
end
 
 
298,10 → 297,10
begin
if (rst)
wr_pointer <= 5'h0;
else if (reset_mode)
wr_pointer <=#Tp rd_pointer;
else if (wr & (~fifo_full))
wr_pointer <=#Tp wr_pointer + 1'b1;
else if (reset_mode)
wr_pointer <=#Tp 5'h0;
end
 
 
322,6 → 321,8
begin
if (rst)
fifo_cnt <= 7'h0;
else if (reset_mode)
fifo_cnt <=#Tp 7'h0;
else if (wr & (~release_buffer) & (~fifo_full))
fifo_cnt <=#Tp fifo_cnt + 1'b1;
else if ((~wr) & release_buffer & (~fifo_empty))
328,8 → 329,6
fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
else if (reset_mode)
fifo_cnt <=#Tp 7'h0;
end
 
assign fifo_full = fifo_cnt == 7'd64;
/trunk/rtl/verilog/can_bsp.v
50,6 → 50,11
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.51 2004/11/15 18:23:21 igorm
// When CAN was reset by setting the reset_mode signal in mode register, it
// was possible that CAN was blocked for a short period of time. Problem
// occured very rarly.
//
// Revision 1.50 2004/10/27 18:51:36 igorm
// Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
//
915,7 → 920,7
begin
if (rst)
rx_eof <= 1'b0;
else if (go_rx_inter | go_error_frame | go_overload_frame)
else if (reset_mode | go_rx_inter | go_error_frame | go_overload_frame)
rx_eof <=#Tp 1'b0;
else if (go_rx_eof)
rx_eof <=#Tp 1'b1;
940,6 → 945,8
begin
if (rst)
id <= 29'h0;
else if (reset_mode)
id <= 29'h0;
else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
id <=#Tp {id[27:0], sampled_bit};
end
950,6 → 957,8
begin
if (rst)
rtr1 <= 1'b0;
else if (reset_mode)
rtr1 <= 1'b0;
else if (sample_point & rx_rtr1 & (~bit_de_stuff))
rtr1 <=#Tp sampled_bit;
end
960,6 → 969,8
begin
if (rst)
rtr2 <= 1'b0;
else if (reset_mode)
rtr2 <= 1'b0;
else if (sample_point & rx_rtr2 & (~bit_de_stuff))
rtr2 <=#Tp sampled_bit;
end
970,6 → 981,8
begin
if (rst)
ide <= 1'b0;
else if (reset_mode)
ide <= 1'b0;
else if (sample_point & rx_ide & (~bit_de_stuff))
ide <=#Tp sampled_bit;
end
980,6 → 993,8
begin
if (rst)
data_len <= 4'b0;
else if (reset_mode)
data_len <= 4'b0;
else if (sample_point & rx_dlc & (~bit_de_stuff))
data_len <=#Tp {data_len[2:0], sampled_bit};
end
990,6 → 1005,8
begin
if (rst)
tmp_data <= 8'h0;
else if (reset_mode)
tmp_data <= 8'h0;
else if (sample_point & rx_data & (~bit_de_stuff))
tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
end
999,6 → 1016,8
begin
if (rst)
write_data_to_tmp_fifo <= 1'b0;
else if (reset_mode)
write_data_to_tmp_fifo <= 1'b0;
else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
write_data_to_tmp_fifo <=#Tp 1'b1;
else
1010,9 → 1029,11
begin
if (rst)
byte_cnt <= 3'h0;
else if (reset_mode)
byte_cnt <= 3'h0;
else if (write_data_to_tmp_fifo)
byte_cnt <=#Tp byte_cnt + 1'b1;
else if (reset_mode | (sample_point & go_rx_crc_lim))
else if (sample_point & go_rx_crc_lim)
byte_cnt <=#Tp 3'h0;
end
 
1030,6 → 1051,8
begin
if (rst)
crc_in <= 15'h0;
else if (reset_mode)
crc_in <= 15'h0;
else if (sample_point & rx_crc & (~bit_de_stuff))
crc_in <=#Tp {crc_in[13:0], sampled_bit};
end
1040,6 → 1063,8
begin
if (rst)
bit_cnt <= 6'd0;
else if (reset_mode)
bit_cnt <= 6'd0;
else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
bit_cnt <=#Tp 6'd0;
1053,9 → 1078,11
begin
if (rst)
eof_cnt <= 3'd0;
else if (reset_mode)
eof_cnt <= 3'd0;
else if (sample_point)
begin
if (reset_mode | go_rx_inter | go_error_frame | go_overload_frame)
if (go_rx_inter | go_error_frame | go_overload_frame)
eof_cnt <=#Tp 3'd0;
else if (rx_eof)
eof_cnt <=#Tp eof_cnt + 1'b1;
1068,6 → 1095,8
begin
if (rst)
bit_stuff_cnt_en <= 1'b0;
else if (reset_mode)
bit_stuff_cnt_en <= 1'b0;
else if (bit_de_stuff_set)
bit_stuff_cnt_en <=#Tp 1'b1;
else if (bit_de_stuff_reset)
1080,6 → 1109,8
begin
if (rst)
bit_stuff_cnt <= 3'h1;
else if (reset_mode)
bit_stuff_cnt <= 3'h1;
else if (bit_de_stuff_reset)
bit_stuff_cnt <=#Tp 3'h1;
else if (sample_point & bit_stuff_cnt_en)
1099,6 → 1130,8
begin
if (rst)
bit_stuff_cnt_tx <= 3'h1;
else if (reset_mode)
bit_stuff_cnt_tx <= 3'h1;
else if (bit_de_stuff_reset)
bit_stuff_cnt_tx <=#Tp 3'h1;
else if (tx_point_q & bit_stuff_cnt_en)
1144,10 → 1177,10
begin
if (rst)
crc_enable <= 1'b0;
else if (reset_mode | rst_crc_enable)
crc_enable <=#Tp 1'b0;
else if (go_crc_enable)
crc_enable <=#Tp 1'b1;
else if (reset_mode | rst_crc_enable)
crc_enable <=#Tp 1'b0;
end
 
 
1156,10 → 1189,10
begin
if (rst)
crc_err <= 1'b0;
else if (reset_mode | error_frame_ended)
crc_err <=#Tp 1'b0;
else if (go_rx_ack)
crc_err <=#Tp crc_in != calculated_crc;
else if (reset_mode | error_frame_ended)
crc_err <=#Tp 1'b0;
end
 
 
1641,6 → 1674,8
begin
if (rst)
tx_q <=#Tp 1'b0;
else if (reset_mode)
tx_q <=#Tp 1'b0;
else if (tx_point)
tx_q <=#Tp tx & (~go_early_tx_latched);
end
1651,6 → 1686,8
begin
if (rst)
tx_point_q <=#Tp 1'b0;
else if (reset_mode)
tx_point_q <=#Tp 1'b0;
else
tx_point_q <=#Tp tx_point;
end
1768,7 → 1805,7
begin
if (rst)
go_early_tx_latched <= 1'b0;
else if (tx_point)
else if (reset_mode || tx_point)
go_early_tx_latched <=#Tp 1'b0;
else if (go_early_tx)
go_early_tx_latched <=#Tp 1'b1;
1791,6 → 1828,8
begin
if (rst)
tx_state_q <=#Tp 1'b0;
else if (reset_mode)
tx_state_q <=#Tp 1'b0;
else
tx_state_q <=#Tp tx_state;
end
1885,6 → 1924,11
arbitration_lost_q <=#Tp 1'b0;
read_arbitration_lost_capture_reg_q <=#Tp 1'b0;
end
else if (reset_mode)
begin
arbitration_lost_q <=#Tp 1'b0;
read_arbitration_lost_capture_reg_q <=#Tp 1'b0;
end
else
begin
arbitration_lost_q <=#Tp arbitration_lost;
1900,7 → 1944,7
begin
if (rst)
arbitration_cnt_en <= 1'b0;
else if (arbitration_blocked)
else if (reset_mode || arbitration_blocked)
arbitration_cnt_en <=#Tp 1'b0;
else if (rx_id1 & sample_point & (~arbitration_blocked))
arbitration_cnt_en <=#Tp 1'b1;
1912,7 → 1956,7
begin
if (rst)
arbitration_blocked <= 1'b0;
else if (read_arbitration_lost_capture_reg)
else if (reset_mode || read_arbitration_lost_capture_reg)
arbitration_blocked <=#Tp 1'b0;
else if (set_arbitration_lost_irq)
arbitration_blocked <=#Tp 1'b1;
2048,6 → 2092,8
begin
if (rst)
bus_free <= 1'b0;
else if (reset_mode)
bus_free <= 1'b0;
else if (sample_point & sampled_bit & (bus_free_cnt==4'd10))
bus_free <=#Tp 1'b1;
else
2059,6 → 2105,8
begin
if (rst)
waiting_for_bus_free <= 1'b1;
else if (reset_mode)
waiting_for_bus_free <= 1'b1;
else if (bus_free & (~node_bus_off))
waiting_for_bus_free <=#Tp 1'b0;
else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
2069,13 → 2117,13
assign bus_off_on = ~node_bus_off;
 
assign set_reset_mode = node_bus_off & (~node_bus_off_q);
assign error_status = (~reset_mode) & extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit)) :
((rx_err_cnt >= 9'd96) | (tx_err_cnt >= 9'd96)) ;
assign error_status = extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit)) :
((rx_err_cnt >= 9'd96) | (tx_err_cnt >= 9'd96)) ;
 
assign transmit_status = transmitting | (extended_mode & waiting_for_bus_free);
assign receive_status = (~rx_idle) & (~transmitting) | (extended_mode & waiting_for_bus_free);
assign transmit_status = transmitting || (extended_mode && waiting_for_bus_free);
assign receive_status = extended_mode ? (waiting_for_bus_free || (!rx_idle) && (!transmitting)) :
((!waiting_for_bus_free) && (!rx_idle) && (!transmitting));
 
 
/* Error code capture register */
always @ (posedge clk or posedge rst)
begin
/trunk/rtl/verilog/can_registers.v
50,6 → 50,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.33 2004/10/25 11:44:38 igorm
// Interrupt is always cleared for one clock after the irq register is read.
// This fixes problems when CPU is using IRQs that are edge triggered.
//
// Revision 1.32 2004/05/12 15:58:41 igorm
// Core improved to pass all tests with the Bosch VHDL Reference system.
//
542,7 → 546,7
.we(we_command),
.clk(clk),
.rst(rst),
.rst_sync(command[0] & sample_point)
.rst_sync(command[0] & sample_point | reset_mode)
);
 
can_register_asyn_syn #(1, 1'h0) COMMAND_REG1
551,7 → 555,7
.we(we_command),
.clk(clk),
.rst(rst),
.rst_sync(sample_point & (tx_request | (abort_tx & ~transmitting)))
.rst_sync(sample_point & (tx_request | (abort_tx & ~transmitting)) | reset_mode)
);
 
can_register_asyn_syn #(2, 2'h0) COMMAND_REG
560,7 → 564,7
.we(we_command),
.clk(clk),
.rst(rst),
.rst_sync(|command[3:2])
.rst_sync(|command[3:2] | reset_mode)
);
 
can_register_asyn_syn #(1, 1'h0) COMMAND_REG4
569,7 → 573,7
.we(we_command),
.clk(clk),
.rst(rst),
.rst_sync(command[4] & sample_point)
.rst_sync(command[4] & sample_point | reset_mode)
);
 
 
662,7 → 666,7
transmit_buffer_status <= 1'b1;
else if (tx_request)
transmit_buffer_status <=#Tp 1'b0;
else if (~need_to_tx)
else if (reset_mode || !need_to_tx)
transmit_buffer_status <=#Tp 1'b1;
end
 
673,7 → 677,7
overrun_status <= 1'b0;
else if (overrun & (~overrun_q))
overrun_status <=#Tp 1'b1;
else if (clear_data_overrun)
else if (reset_mode || clear_data_overrun)
overrun_status <=#Tp 1'b0;
end
 
682,7 → 686,7
begin
if (rst)
receive_buffer_status <= 1'b0;
else if (release_buffer)
else if (reset_mode || release_buffer)
receive_buffer_status <=#Tp 1'b0;
else if (~info_empty)
receive_buffer_status <=#Tp 1'b1;
1145,7 → 1149,7
data_overrun_irq <= 1'b0;
else if (overrun & (~overrun_q) & data_overrun_irq_en)
data_overrun_irq <=#Tp 1'b1;
else if (read_irq_reg)
else if (reset_mode || read_irq_reg)
data_overrun_irq <=#Tp 1'b0;
end
 
1155,10 → 1159,10
begin
if (rst)
transmit_irq <= 1'b0;
else if (reset_mode || read_irq_reg)
transmit_irq <=#Tp 1'b0;
else if (transmit_buffer_status & (~transmit_buffer_status_q) & transmit_irq_en)
transmit_irq <=#Tp 1'b1;
else if (read_irq_reg)
transmit_irq <=#Tp 1'b0;
end
 
 
1167,10 → 1171,10
begin
if (rst)
receive_irq <= 1'b0;
else if (release_buffer)
receive_irq <=#Tp 1'b0;
else if ((~info_empty) & (~receive_irq) & receive_irq_en)
receive_irq <=#Tp 1'b1;
else if (reset_mode || release_buffer)
receive_irq <=#Tp 1'b0;
end
 
 
1193,7 → 1197,7
bus_error_irq <= 1'b0;
else if (set_bus_error_irq & bus_error_irq_en)
bus_error_irq <=#Tp 1'b1;
else if (read_irq_reg)
else if (reset_mode || read_irq_reg)
bus_error_irq <=#Tp 1'b0;
end
 
1205,7 → 1209,7
arbitration_lost_irq <= 1'b0;
else if (set_arbitration_lost_irq & arbitration_lost_irq_en)
arbitration_lost_irq <=#Tp 1'b1;
else if (read_irq_reg)
else if (reset_mode || read_irq_reg)
arbitration_lost_irq <=#Tp 1'b0;
end
 
1218,7 → 1222,7
error_passive_irq <= 1'b0;
else if ((node_error_passive & (~node_error_passive_q) | (~node_error_passive) & node_error_passive_q & node_error_active) & error_passive_irq_en)
error_passive_irq <=#Tp 1'b1;
else if (read_irq_reg)
else if (reset_mode || read_irq_reg)
error_passive_irq <=#Tp 1'b0;
end
 
1242,3 → 1246,4
 
 
endmodule
 

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