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Rev 5 → Rev 4

cop/trunk/sim/verilog/run/run_iverilog Property changes : Deleted: svn:executable Index: cop/trunk/sim/verilog/run/.cop_wave.sav =================================================================== --- cop/trunk/sim/verilog/run/.cop_wave.sav (revision 5) +++ cop/trunk/sim/verilog/run/.cop_wave.sav (nonexistent) @@ -1,63 +0,0 @@ -[size] 1271 653 -[pos] -1 -1 -*-18.000000 8760000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] tst_bench_top. -[treeopen] tst_bench_top.cop_1. -[treeopen] tst_bench_top.cop_4. -@24 -tst_bench_top.vector[19:0] -@28 -tst_bench_top.cop_1.por_reset_i -tst_bench_top.rstn -tst_bench_top.cop_1.wb_adr_i[2:0] -tst_bench_top.cop_1.wb_we_i -tst_bench_top.cop_1.wb_cyc_i -@22 -tst_bench_top.cop_1.wb_dat_i[15:0] -@28 -tst_bench_top.cop_1.wb_stb_i -tst_bench_top.cop_1.regs.bus_clk -tst_bench_top.cop_1.wb_ack_o -@22 -tst_bench_top.cop_1.wb_dat_o[15:0] -@28 -tst_bench_top.cop_1.wishbone.wb_wacc -tst_bench_top.cop_1.wishbone.wb_racc -@200 -- -@22 -tst_bench_top.cop_1.regs.timeout_value[15:0] -@28 -tst_bench_top.cop_1.regs.cop_ena -tst_bench_top.cop_1.regs.cwp -tst_bench_top.cop_1.regs.clck -@22 -tst_bench_top.cop_1.regs.write_regs[4:0] -@200 -- -@28 -tst_bench_top.osc_clk -@22 -tst_bench_top.osc_div[8:0] -tst_bench_top.cop_1.counter.cop_counter[15:0] -@28 -tst_bench_top.en_osc_clk -tst_bench_top.cop_1.counter.reload_count -tst_bench_top.cop_1.counter.reload_1 -tst_bench_top.cop_1.counter.reload_2 -tst_bench_top.cop_1.cop_rst_o -tst_bench_top.cop_1.counter.cop_event -tst_bench_top.cop_1.counter.clear_event -tst_bench_top.cop_1.counter.event_reset -@22 -tst_bench_top.cop_1.counter.cop_capture[15:0] -@200 -- -@28 -tst_bench_top.cop_4.regs.cop_ena -tst_bench_top.cop_4.counter.cop_event -@22 -tst_bench_top.cop_4.counter.cop_counter[15:0] -@28 -tst_bench_top.cop_4.regs.service_cop -tst_bench_top.cop_4.regs.reload_count

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