URL
https://opencores.org/ocsvn/cop/cop/trunk
Subversion Repositories cop
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 7 to Rev 6
- ↔ Reverse comparison
Rev 7 → Rev 6
/cop/trunk/bench/verilog/tst_bench_top.v
313,11 → 313,31
cop_count_test; |
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cop_count_test_8; |
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cop_irq_test; |
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$finish; |
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u0.wb_write(1, SLAVE_0_CNTRL, COP_CNTRL_DEBUG_ENA); // Enable Slave Mode |
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// Set Master Mode PS=0, Modulo=16 |
test_num = test_num + 1; |
$display("TEST #%d Starts at vector=%d, ms_test", test_num, vector); |
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u0.wb_write(1, COP_TOUT, 16'h0010); // load prescaler hi-byte |
u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA); // Enable to start counting |
$display("status: %t programmed registers", $time); |
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wait_flag_set; // Wait for Counter to tomeout |
u0.wb_write(1, COP_CNTRL, COP_CNTRL_STOP_ENA | COP_CNTRL_COP_ENA); // |
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wait_flag_set; // Wait for Counter to tomeout |
u0.wb_write(1, COP_CNTRL, COP_CNTRL_STOP_ENA | COP_CNTRL_COP_ENA); // |
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repeat(10) @(posedge mstr_test_clk); |
u0.wb_write(1, COP_CNTRL, 16'b0); // |
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repeat(10) @(posedge mstr_test_clk); |
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repeat(100) @(posedge mstr_test_clk); |
$display("\nTestbench done at vector=%d\n", vector); |
$finish; |
end |
326,7 → 346,7
task wait_flag_set; |
begin |
u0.wb_read(1, COP_CNTRL, q); |
while(~|(q & COP_CNTRL_COP_EVENT)) |
while(~|(q & COP_CNTRL_STOP_ENA)) |
u0.wb_read(1, COP_CNTRL, q); // poll it until it is set |
$display("COP Flag set detected at vector =%d", vector); |
end |
494,27 → 514,6
end |
endtask |
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task cop_irq_test; |
begin |
test_num = test_num + 1; |
$display("TEST #%d Starts at vector=%d, cop_irq_test", |
test_num, vector); |
// program internal registers |
u0.wb_write(1, COP_CNTRL, 16'h0000); // Turn off COP_ENA |
u0.wb_write(1, COP_TOUT, 16'h0014); // Write TOUT reg |
// u0.wb_write(1, COP_CNTRL, COP_CNTRL_IRQ | COP_CNTRL_COP_ENA); // |
u0.wb_write(1, COP_CNTRL, 16'h0040 | COP_CNTRL_COP_ENA); // |
send_x_osc_clks(10); |
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u0.wb_write(1, COP_CNTRL, 16'h0000); // Turn off COP_ENA |
u0.wb_write(1, COP_TOUT, 16'h0022); // Write TOUT reg |
send_x_osc_clks(1); |
// u0.wb_write(1, COP_CNTRL, COP_CNTRL_IRQ | COP_CNTRL_COP_ENA); // |
u0.wb_write(1, COP_CNTRL, 16'h0080 | COP_CNTRL_COP_ENA); // |
send_x_osc_clks(10); |
end |
endtask |
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task cop_count_test_8; |
begin |
test_num = test_num + 1; |