OpenCores
URL https://opencores.org/ocsvn/cop/cop/trunk

Subversion Repositories cop

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /cop
    from Rev 6 to Rev 5
    Reverse comparison

Rev 6 → Rev 5

/trunk/sim/verilog/run/.cop_wave.sav
0,0 → 1,63
[size] 1271 653
[pos] -1 -1
*-18.000000 8760000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tst_bench_top.
[treeopen] tst_bench_top.cop_1.
[treeopen] tst_bench_top.cop_4.
@24
tst_bench_top.vector[19:0]
@28
tst_bench_top.cop_1.por_reset_i
tst_bench_top.rstn
tst_bench_top.cop_1.wb_adr_i[2:0]
tst_bench_top.cop_1.wb_we_i
tst_bench_top.cop_1.wb_cyc_i
@22
tst_bench_top.cop_1.wb_dat_i[15:0]
@28
tst_bench_top.cop_1.wb_stb_i
tst_bench_top.cop_1.regs.bus_clk
tst_bench_top.cop_1.wb_ack_o
@22
tst_bench_top.cop_1.wb_dat_o[15:0]
@28
tst_bench_top.cop_1.wishbone.wb_wacc
tst_bench_top.cop_1.wishbone.wb_racc
@200
-
@22
tst_bench_top.cop_1.regs.timeout_value[15:0]
@28
tst_bench_top.cop_1.regs.cop_ena
tst_bench_top.cop_1.regs.cwp
tst_bench_top.cop_1.regs.clck
@22
tst_bench_top.cop_1.regs.write_regs[4:0]
@200
-
@28
tst_bench_top.osc_clk
@22
tst_bench_top.osc_div[8:0]
tst_bench_top.cop_1.counter.cop_counter[15:0]
@28
tst_bench_top.en_osc_clk
tst_bench_top.cop_1.counter.reload_count
tst_bench_top.cop_1.counter.reload_1
tst_bench_top.cop_1.counter.reload_2
tst_bench_top.cop_1.cop_rst_o
tst_bench_top.cop_1.counter.cop_event
tst_bench_top.cop_1.counter.clear_event
tst_bench_top.cop_1.counter.event_reset
@22
tst_bench_top.cop_1.counter.cop_capture[15:0]
@200
-
@28
tst_bench_top.cop_4.regs.cop_ena
tst_bench_top.cop_4.counter.cop_event
@22
tst_bench_top.cop_4.counter.cop_counter[15:0]
@28
tst_bench_top.cop_4.regs.service_cop
tst_bench_top.cop_4.regs.reload_count

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.