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Rev 26 → Rev 25

/trunk/asm/readme.txt
28,5 → 28,5
; => trap_ne ;unexpected B-flag! - this may fail on a real 6502
;due to a hardware bug on concurrent BRK & NMI
 
All three tests: SUCCESS with v1.4
All four tests: SUCCESS with v1.52RC
 
/trunk/doc/6502 IP Core Specification_V0_7.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/6502 IP Core Specification_V0_7.pdf
trunk/doc/6502 IP Core Specification_V0_7.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/HTML_r6502_tc.7z =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/HTML_r6502_tc.7z =================================================================== --- trunk/doc/HTML_r6502_tc.7z (revision 26) +++ trunk/doc/HTML_r6502_tc.7z (nonexistent)
trunk/doc/HTML_r6502_tc.7z Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/errata.txt =================================================================== --- trunk/doc/errata.txt (revision 26) +++ trunk/doc/errata.txt (revision 25) @@ -1,16 +1,5 @@ -v1.4 2018/09/15 +v1.11 BETA 2013/07/24 FUNCTIONALITY: - no errata reported/opened - -TIMING: - no errata reported/opened - -SIGNALING: - no errata reported/opened - - -v1.4 BETA 2013/07/24 -FUNCTIONALITY: - ADC and SBC in decimal mode (all op codes - seems to use a formula different from a real R6502.
/trunk/doc/HTML.rar Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/HTML.rar
trunk/doc/HTML.rar Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/src/6502 IP Core Specification_V0_6.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/6502 IP Core Specification_V0_6.doc =================================================================== --- trunk/doc/src/6502 IP Core Specification_V0_6.doc (nonexistent) +++ trunk/doc/src/6502 IP Core Specification_V0_6.doc (revision 25)
trunk/doc/src/6502 IP Core Specification_V0_6.doc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/src/6502_opcodes_cycles_testet_V0_9_DRAFT.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/6502_opcodes_cycles_testet_V0_9_DRAFT.doc =================================================================== --- trunk/doc/src/6502_opcodes_cycles_testet_V0_9_DRAFT.doc (nonexistent) +++ trunk/doc/src/6502_opcodes_cycles_testet_V0_9_DRAFT.doc (revision 25)
trunk/doc/src/6502_opcodes_cycles_testet_V0_9_DRAFT.doc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/6502 IP Core Specification_V0_6.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/6502 IP Core Specification_V0_6.pdf =================================================================== --- trunk/doc/6502 IP Core Specification_V0_6.pdf (nonexistent) +++ trunk/doc/6502 IP Core Specification_V0_6.pdf (revision 25)
trunk/doc/6502 IP Core Specification_V0_6.pdf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/rtl/vhdl/fsm_intnmi.vhd =================================================================== --- trunk/rtl/vhdl/fsm_intnmi.vhd (revision 26) +++ trunk/rtl/vhdl/fsm_intnmi.vhd (nonexistent) @@ -1,165 +0,0 @@ --- VHDL Entity r6502_tc.fsm_intnmi.symbol --- --- Created: --- by - remoteghost.UNKNOWN (ENTW-7HPZ200) --- at - 09:22:12 07/24/13 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity fsm_intnmi is - port( - clk_clk_i : in std_logic; - nmi_n_i : in std_logic; - rst_nmi_i : in std_logic; - rst_rst_n_i : in std_logic; - nmi_o : out std_logic - ); - --- Declarations - -end fsm_intnmi ; - --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.9 2018/09/11 11:37:00 jens --- - NMI = '0' need at least 1 cycles for correct --- operation now (2 cycles in the past) --- --- Revision 1.8 2013/07/24 11:11:00 jens --- - Changing the title block and internal revision history --- --- Revision 1.6 2009/01/04 10:20:47 eda --- Changes for cosmetic issues only --- --- Revision 1.5 2009/01/04 09:23:10 eda --- - Delete unused nets and blocks --- - Rename blocks --- --- Revision 1.4 2009/01/03 16:53:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.3 2009/01/03 16:42:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.2 2008/12/31 19:31:24 eda --- Production Release --- --- --- --- VHDL Architecture r6502_tc.fsm_intnmi.fsm --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 11:45:38 11.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -architecture fsm of fsm_intnmi is - - subtype state_type is - std_logic_vector(1 downto 0); - - -- Hard encoding - constant idle : state_type := "00"; - constant idle1 : state_type := "01"; - constant IMP : state_type := "11"; - - -- Declare current and next state signals - signal current_state : state_type; - signal next_state : state_type; - - -- Declare any pre-registered internal signals - signal nmi_o_cld : std_logic ; - -begin - - ----------------------------------------------------------------- - clocked_proc : process ( - clk_clk_i, - rst_rst_n_i - ) - ----------------------------------------------------------------- - begin - if (rst_rst_n_i = '0') then - current_state <= idle; - -- Default Reset Values - nmi_o_cld <= '0'; - elsif (clk_clk_i'event and clk_clk_i = '1') then - current_state <= next_state; - -- Default Assignment To Internals - nmi_o_cld <= '0'; - - -- Combined Actions - case current_state is - when idle1 => - if (nmi_n_i = '0') then - nmi_o_cld <= '1'; - end if; - when IMP => - nmi_o_cld <= '1'; - if (rst_nmi_i = '1') then - nmi_o_cld <= '0'; - end if; - when others => - null; - end case; - end if; - end process clocked_proc; - - ----------------------------------------------------------------- - nextstate_proc : process ( - current_state, - nmi_n_i, - rst_nmi_i - ) - ----------------------------------------------------------------- - begin - case current_state is - when idle => - if (nmi_n_i = '1') then - next_state <= idle1; - else - next_state <= idle; - end if; - when idle1 => - if (nmi_n_i = '0') then - next_state <= IMP; - else - next_state <= idle1; - end if; - when IMP => - if (rst_nmi_i = '1') then - next_state <= idle; - else - next_state <= IMP; - end if; - when others => - next_state <= idle; - end case; - end process nextstate_proc; - - -- Concurrent Statements - -- Clocked output assignments - nmi_o <= nmi_o_cld; -end fsm; Index: trunk/rtl/vhdl/reg_pc.vhd =================================================================== --- trunk/rtl/vhdl/reg_pc.vhd (revision 26) +++ trunk/rtl/vhdl/reg_pc.vhd (revision 25) @@ -1,226 +1,216 @@ --- VHDL Entity r6502_tc.reg_pc.symbol +-- VHDL Entity R6502_TC.Reg_PC.symbol -- -- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 11:45:07 11.09.2018 +-- by - eda.UNKNOWN (ENTW1) +-- at - 18:39:48 08.02.2010 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -entity reg_pc is - port( - adr_i : in std_logic_vector (15 downto 0); - clk_clk_i : in std_logic; - ld_i : in std_logic_vector (1 downto 0); - ld_pc_i : in std_logic; - offset_i : in std_logic_vector (15 downto 0); - rst_rst_n_i : in std_logic; - sel_pc_in_i : in std_logic; - sel_pc_val_i : in std_logic_vector (1 downto 0); - adr_nxt_pc_o : out std_logic_vector (15 downto 0); - adr_pc_o : out std_logic_vector (15 downto 0) +ENTITY Reg_PC IS + PORT( + adr_i : IN std_logic_vector (15 DOWNTO 0); + clk_clk_i : IN std_logic; + ld_i : IN std_logic_vector (1 DOWNTO 0); + ld_pc_i : IN std_logic; + offset_i : IN std_logic_vector (15 DOWNTO 0); + rst_rst_n_i : IN std_logic; + sel_pc_in_i : IN std_logic; + sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0); + adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0); + adr_pc_o : OUT std_logic_vector (15 DOWNTO 0) ); -- Declarations -end reg_pc ; +END Reg_PC ; --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.15 2013/07/21 11:11:00 jens --- - Change mux 3-1 to mux 4-1 for vendors like Xilinx --- - Changing the title block and internal revision history --- --- Revision 1.3 2009/01/04 10:20:50 eda --- Changes for cosmetic issues only --- --- Revision 1.2 2009/01/04 09:23:12 eda --- - Delete unused nets and blocks --- - Rename blocks --- - Re-arrage FSM symbols in block FSM_Execution_Unit --- --- Revision 1.1 2009/01/03 16:36:48 eda --- Production Release --- --- +-- Jens-D. Gutschmidt Project: R6502_TC +-- scantara2003@yahoo.de +-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- CVS Revisins History +-- +-- $Log: struct.bd,v $ +-- <<-- more -->> +-- Title: Program Counter Logic +-- Path: R6502_TC/Reg_PC/struct +-- Edited: by eda on 08 Feb 2010 -- --- VHDL Architecture r6502_tc.reg_pc.struct +-- VHDL Architecture R6502_TC.Reg_PC.struct -- -- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 11:45:07 11.09.2018 +-- by - eda.UNKNOWN (ENTW1) +-- at - 18:39:49 08.02.2010 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -architecture struct of reg_pc is +ARCHITECTURE struct OF Reg_PC IS -- Architecture declarations -- Internal signal declarations - signal adr_pc_high_o_i : std_logic_vector(7 downto 0); - signal adr_pc_low_o_i : std_logic_vector(7 downto 0); - signal adr_pc_o_i : std_logic_vector(15 downto 0); - signal ci_o_i : std_logic; - signal cout_pc_o_i : std_logic; - signal load3_o_i : std_logic; - signal load_o_i : std_logic; - signal offset_high_o_i : std_logic_vector(7 downto 0); - signal offset_low_o_i : std_logic_vector(7 downto 0); - signal val_o_i : std_logic_vector(7 downto 0); - signal val_one : std_logic_vector(7 downto 0); - signal val_zero : std_logic_vector(7 downto 0); + SIGNAL adr_pc_high_o_i : std_logic_vector(7 DOWNTO 0); + SIGNAL adr_pc_low_o_i : std_logic_vector(7 DOWNTO 0); + SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0); + SIGNAL ci_o_i : std_logic; + SIGNAL cout_pc_o_i : std_logic; + SIGNAL load3_o_i : std_logic; + SIGNAL load_o_i : std_logic; + SIGNAL offset_high_o_i : std_logic_vector(7 DOWNTO 0); + SIGNAL offset_low_o_i : std_logic_vector(7 DOWNTO 0); + SIGNAL val_o_i : std_logic_vector(7 DOWNTO 0); + SIGNAL val_one : std_logic_vector(7 DOWNTO 0); + SIGNAL val_zero : std_logic_vector(7 DOWNTO 0); -- Implicit buffer signal declarations - signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0); - signal adr_pc_o_internal : std_logic_vector (15 downto 0); + SIGNAL adr_nxt_pc_o_internal : std_logic_vector (15 DOWNTO 0); + SIGNAL adr_pc_o_internal : std_logic_vector (15 DOWNTO 0); - -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' - signal mw_U_0reg_cval : std_logic_vector(7 downto 0); + -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff' + SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0); - -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' - signal mw_U_4reg_cval : std_logic_vector(7 downto 0); + -- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff' + SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0); - -- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'split' - signal mw_U_3temp_din : std_logic_vector(15 downto 0); + -- ModuleWare signal declarations(v1.9) for instance 'U_3' of 'split' + SIGNAL mw_U_3temp_din : std_logic_vector(15 DOWNTO 0); - -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'split' - signal mw_U_5temp_din : std_logic_vector(15 downto 0); + -- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'split' + SIGNAL mw_U_5temp_din : std_logic_vector(15 DOWNTO 0); -begin +BEGIN - -- ModuleWare code(v1.12) for instance 'U_2' of 'add' - u_2combo_proc: process (adr_pc_low_o_i, val_o_i) - variable temp_din0 : std_logic_vector(8 downto 0); - variable temp_din1 : std_logic_vector(8 downto 0); - variable temp_sum : unsigned(8 downto 0); - variable temp_carry : std_logic; - begin + -- ModuleWare code(v1.9) for instance 'U_2' of 'add' + u_2combo_proc: PROCESS (adr_pc_low_o_i, val_o_i) + VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0); + VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0); + VARIABLE temp_sum : unsigned(8 DOWNTO 0); + VARIABLE temp_carry : std_logic; + BEGIN temp_din0 := '0' & adr_pc_low_o_i; temp_din1 := '0' & val_o_i; temp_carry := '0'; temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; - adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 downto 0),8); + adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8); cout_pc_o_i <= temp_sum(8) ; - end process u_2combo_proc; + END PROCESS u_2combo_proc; - -- ModuleWare code(v1.12) for instance 'U_11' of 'add' - u_11combo_proc: process (adr_pc_high_o_i, offset_high_o_i, ci_o_i) - variable temp_din0 : std_logic_vector(8 downto 0); - variable temp_din1 : std_logic_vector(8 downto 0); - variable temp_sum : unsigned(8 downto 0); - variable temp_carry : std_logic; - begin + -- ModuleWare code(v1.9) for instance 'U_11' of 'add' + u_11combo_proc: PROCESS (adr_pc_high_o_i, offset_high_o_i, ci_o_i) + VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0); + VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0); + VARIABLE temp_sum : unsigned(8 DOWNTO 0); + VARIABLE temp_carry : std_logic; + BEGIN temp_din0 := '0' & adr_pc_high_o_i; temp_din1 := '0' & offset_high_o_i; temp_carry := ci_o_i; temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; - adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 downto 0),8); - end process u_11combo_proc; + adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8); + END PROCESS u_11combo_proc; - -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' + -- ModuleWare code(v1.9) for instance 'U_0' of 'adff' adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; - u_0seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then + u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i) + BEGIN + IF (rst_rst_n_i = '0') THEN mw_U_0reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load_o_i = '1') then + ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN + IF (load_o_i = '1') THEN mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0); - end if; - end if; - end process u_0seq_proc; + END IF; + END IF; + END PROCESS u_0seq_proc; - -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' + -- ModuleWare code(v1.9) for instance 'U_4' of 'adff' adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval; - u_4seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then + u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i) + BEGIN + IF (rst_rst_n_i = '0') THEN mw_U_4reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load3_o_i = '1') then + ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN + IF (load3_o_i = '1') THEN mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8); - end if; - end if; - end process u_4seq_proc; + END IF; + END IF; + END PROCESS u_4seq_proc; - -- ModuleWare code(v1.12) for instance 'U_6' of 'and' - load_o_i <= ld_pc_i and ld_i(0); + -- ModuleWare code(v1.9) for instance 'U_6' of 'and' + load_o_i <= ld_pc_i AND ld_i(0); - -- ModuleWare code(v1.12) for instance 'U_7' of 'and' - load3_o_i <= ld_pc_i and ld_i(1); + -- ModuleWare code(v1.9) for instance 'U_7' of 'and' + load3_o_i <= ld_pc_i AND ld_i(1); - -- ModuleWare code(v1.12) for instance 'U_10' of 'and' - ci_o_i <= cout_pc_o_i and ld_pc_i; + -- ModuleWare code(v1.9) for instance 'U_10' of 'and' + ci_o_i <= cout_pc_o_i AND ld_pc_i; - -- ModuleWare code(v1.12) for instance 'U_1' of 'constval' + -- ModuleWare code(v1.9) for instance 'U_1' of 'constval' val_zero <= "00000000"; - -- ModuleWare code(v1.12) for instance 'U_9' of 'constval' + -- ModuleWare code(v1.9) for instance 'U_9' of 'constval' val_one <= "00000001"; - -- ModuleWare code(v1.12) for instance 'U_8' of 'mux' - u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i) - begin - case sel_pc_in_i is - when '0' => adr_pc_o_i <= adr_pc_o_internal; - when '1' => adr_pc_o_i <= adr_i; - when others => adr_pc_o_i <= (others => 'X'); - end case; - end process u_8combo_proc; + -- ModuleWare code(v1.9) for instance 'U_8' of 'mux' + u_8combo_proc: PROCESS(adr_pc_o_internal, adr_i, sel_pc_in_i) + BEGIN + CASE sel_pc_in_i IS + WHEN '0' => adr_pc_o_i <= adr_pc_o_internal; + WHEN '1' => adr_pc_o_i <= adr_i; + WHEN OTHERS => adr_pc_o_i <= (OTHERS => 'X'); + END CASE; + END PROCESS u_8combo_proc; - -- ModuleWare code(v1.12) for instance 'U_13' of 'mux' - u_13combo_proc: process(val_one, val_zero, offset_low_o_i, + -- ModuleWare code(v1.9) for instance 'U_13' of 'mux' + u_13combo_proc: PROCESS(val_one, val_zero, offset_low_o_i, sel_pc_val_i) - begin - case sel_pc_val_i is - when "00" => val_o_i <= val_one; - when "01" => val_o_i <= val_zero; - when "10" => val_o_i <= offset_low_o_i; - when "11" => val_o_i <= val_zero; - when others => val_o_i <= (others => 'X'); - end case; - end process u_13combo_proc; + BEGIN + CASE sel_pc_val_i IS + WHEN "00" => val_o_i <= val_one; + WHEN "01" => val_o_i <= val_zero; + WHEN "10" => val_o_i <= offset_low_o_i; + WHEN "11" => val_o_i <= val_zero; + WHEN OTHERS => val_o_i <= (OTHERS => 'X'); + END CASE; + END PROCESS u_13combo_proc; - -- ModuleWare code(v1.12) for instance 'U_3' of 'split' + -- ModuleWare code(v1.9) for instance 'U_3' of 'split' mw_U_3temp_din <= adr_pc_o_i; - u_3combo_proc: process (mw_U_3temp_din) - variable temp_din: std_logic_vector(15 downto 0); - begin - temp_din := mw_U_3temp_din(15 downto 0); - adr_pc_low_o_i <= temp_din(7 downto 0); - adr_pc_high_o_i <= temp_din(15 downto 8); - end process u_3combo_proc; + u_3combo_proc: PROCESS (mw_U_3temp_din) + VARIABLE temp_din: std_logic_vector(15 DOWNTO 0); + BEGIN + temp_din := mw_U_3temp_din(15 DOWNTO 0); + adr_pc_low_o_i <= temp_din(7 DOWNTO 0); + adr_pc_high_o_i <= temp_din(15 DOWNTO 8); + END PROCESS u_3combo_proc; - -- ModuleWare code(v1.12) for instance 'U_5' of 'split' + -- ModuleWare code(v1.9) for instance 'U_5' of 'split' mw_U_5temp_din <= offset_i; - u_5combo_proc: process (mw_U_5temp_din) - variable temp_din: std_logic_vector(15 downto 0); - begin - temp_din := mw_U_5temp_din(15 downto 0); - offset_low_o_i <= temp_din(7 downto 0); - offset_high_o_i <= temp_din(15 downto 8); - end process u_5combo_proc; + u_5combo_proc: PROCESS (mw_U_5temp_din) + VARIABLE temp_din: std_logic_vector(15 DOWNTO 0); + BEGIN + temp_din := mw_U_5temp_din(15 DOWNTO 0); + offset_low_o_i <= temp_din(7 DOWNTO 0); + offset_high_o_i <= temp_din(15 DOWNTO 8); + END PROCESS u_5combo_proc; -- Instance port mappings. @@ -228,4 +218,4 @@ adr_nxt_pc_o <= adr_nxt_pc_o_internal; adr_pc_o <= adr_pc_o_internal; -end struct; +END struct;
/trunk/rtl/vhdl/reg_sp.vhd
1,157 → 1,141
-- VHDL Entity r6502_tc.reg_sp.symbol
-- VHDL Entity R6502_TC.Reg_SP.symbol
--
-- Created:
-- by - remoteghost.UNKNOWN (ENTW-7HPZ200)
-- at - 18:50:08 05/20/10
-- by - eda.UNKNOWN (ENTW1)
-- at - 14:13:51 08.03.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity reg_sp is
port(
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic;
ld_low_i : in std_logic;
ld_sp_i : in std_logic;
rst_rst_n_i : in std_logic;
sel_sp_as_i : in std_logic;
sel_sp_in_i : in std_logic;
adr_sp_o : out std_logic_vector (15 downto 0)
ENTITY Reg_SP IS
PORT(
adr_low_i : IN std_logic_vector (7 DOWNTO 0);
clk_clk_i : IN std_logic;
ld_low_i : IN std_logic;
ld_sp_i : IN std_logic;
rst_rst_n_i : IN std_logic;
sel_sp_as_i : IN std_logic;
sel_sp_in_i : IN std_logic;
adr_sp_o : OUT std_logic_vector (15 DOWNTO 0)
);
 
-- Declarations
 
end reg_sp ;
END Reg_SP ;
 
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.8 2013/07/24 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: struct.bd,v $
-- <<-- more -->>
-- Title: Stack Pointer Logic
-- Path: R6502_TC/Reg_SP/struct
-- Edited: by eda on 21 Feb 2010
--
-- VHDL Architecture r6502_tc.reg_sp.struct
-- VHDL Architecture R6502_TC.Reg_SP.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 11:44:25 11.09.2018
-- by - eda.UNKNOWN (ENTW1)
-- at - 14:13:52 08.03.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
 
architecture struct of reg_sp is
ARCHITECTURE struct OF Reg_SP IS
 
-- Architecture declarations
 
-- Internal signal declarations
signal adr_sp_low_o_i : std_logic_vector(7 downto 0);
signal load_o_i : std_logic;
signal result_low1_o_i : std_logic_vector(7 downto 0);
signal result_low_o_i : std_logic_vector(7 downto 0);
signal sp_as_n_o_i : std_logic;
signal val_one : std_logic_vector(7 downto 0);
SIGNAL adr_sp_low_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL load_o_i : std_logic;
SIGNAL result_low1_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL result_low_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL sp_as_n_o_i : std_logic;
SIGNAL val_one : std_logic_vector(7 DOWNTO 0);
 
-- Implicit buffer signal declarations
signal adr_sp_o_internal : std_logic_vector (15 downto 0);
SIGNAL adr_sp_o_internal : std_logic_vector (15 DOWNTO 0);
 
 
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
 
 
begin
BEGIN
 
-- ModuleWare code(v1.12) for instance 'U_11' of 'addsub'
u_11combo_proc: process (adr_sp_low_o_i, val_one, sp_as_n_o_i)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
variable temp_carry : std_logic;
begin
-- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
u_11combo_proc: PROCESS (adr_sp_low_o_i, val_one, sp_as_n_o_i)
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & adr_sp_low_o_i;
temp_din1 := '0' & val_one;
temp_carry := '0';
if (sp_as_n_o_i = '1') then
IF (sp_as_n_o_i = '1') THEN
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
else
ELSE
temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
end if;
result_low_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8);
end process u_11combo_proc;
END IF;
result_low_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
END PROCESS u_11combo_proc;
 
-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0') THEN
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load_o_i = '1') then
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load_o_i = '1') THEN
mw_U_0reg_cval <= result_low1_o_i;
end if;
end if;
end process u_0seq_proc;
END IF;
END IF;
END PROCESS u_0seq_proc;
 
-- ModuleWare code(v1.12) for instance 'U_6' of 'and'
load_o_i <= ld_sp_i and ld_low_i;
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
load_o_i <= ld_sp_i AND ld_low_i;
 
-- ModuleWare code(v1.12) for instance 'U_3' of 'buff'
-- ModuleWare code(v1.9) for instance 'U_3' of 'buff'
adr_sp_o_internal(15 DOWNTO 8) <= val_one;
 
-- ModuleWare code(v1.12) for instance 'U_4' of 'constval'
-- ModuleWare code(v1.9) for instance 'U_4' of 'constval'
val_one <= "00000001";
 
-- ModuleWare code(v1.12) for instance 'U_2' of 'inv'
sp_as_n_o_i <= not(sel_sp_as_i);
-- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
sp_as_n_o_i <= NOT(sel_sp_as_i);
 
-- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i)
begin
case sel_sp_in_i is
when '0' => result_low1_o_i <= result_low_o_i;
when '1' => result_low1_o_i <= adr_low_i;
when others => result_low1_o_i <= (others => 'X');
end case;
end process u_8combo_proc;
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
u_8combo_proc: PROCESS(result_low_o_i, adr_low_i, sel_sp_in_i)
BEGIN
CASE sel_sp_in_i IS
WHEN '0' => result_low1_o_i <= result_low_o_i;
WHEN '1' => result_low1_o_i <= adr_low_i;
WHEN OTHERS => result_low1_o_i <= (OTHERS => 'X');
END CASE;
END PROCESS u_8combo_proc;
 
-- ModuleWare code(v1.12) for instance 'U_10' of 'tap'
adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0);
-- ModuleWare code(v1.9) for instance 'U_10' of 'tap'
adr_sp_low_o_i <= adr_sp_o_internal(7 DOWNTO 0);
 
-- Instance port mappings.
 
158,4 → 142,4
-- Implicit buffered output assignments
adr_sp_o <= adr_sp_o_internal;
 
end struct;
END struct;
/trunk/rtl/vhdl/r6502_tc.vhd
1,100 → 1,70
-- VHDL Entity r6502_tc.r6502_tc.symbol
-- VHDL Entity R6502_TC.R6502_TC.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 10:34:09 11.09.2018
-- by - eda.UNKNOWN (ENTW1)
-- at - 14:13:53 08.03.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity r6502_tc is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
ENTITY R6502_TC IS
PORT(
clk_clk_i : IN std_logic;
d_i : IN std_logic_vector (7 DOWNTO 0);
irq_n_i : IN std_logic;
nmi_n_i : IN std_logic;
rdy_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
d_o : OUT std_logic_vector (7 DOWNTO 0);
rd_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
);
 
-- Declarations
 
end r6502_tc ;
END R6502_TC ;
 
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.4 2018/09/15 22:07:00 jens
-- - RESET generates SYNC now, 1 dead cycle
-- delayed
-- - ADC / SBC flags and A like R6502 now
-- - Bug Fix ADC and SBC in decimal mode
-- (all op codes - "Overflow" flag was computed
-- wrong)
-- - Interrupt priority order is now: BRK - NMI -
-- IRQ
-- - Performance improvements on-going
-- (Mealy -> Moore)
-- - Bug Fixes All Branch Instructions
-- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC,
-- BVS)
-- 3 cycles now if branch forward occur and
-- the branch instruction lies on a xxFEh
-- location.
-- - Bug Fix Hardware Interrupts NMI & IRQ -
-- "SYNC" now
--
-- Revision 1.4 BETA 2013/07/24 11:11:00 jens
-- - Changing the title block and internal revision history
-- - Bug Fix ADC and SBC (all sub codes - "Overflow" flag was computed wrong)
--
-- Revision 1.3 2009/01/04 10:20:50 eda
-- Changes for cosmetic issues only
--
-- Revision 1.2 2009/01/04 09:23:12 eda
-- - Delete unused nets and blocks
-- - Rename blocks
-- - Re-arrage FSM symbols in block FSM_Execution_Unit
--
-- Revision 1.1 2009/01/03 16:36:48 eda
-- Production version
--
--
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: struct.bd,v $
-- <<-- more -->>
-- Title: Top Level
-- Path: R6502_TC/R6502_TC/struct
-- Edited: by eda on 08 Feb 2010
--
-- VHDL Architecture r6502_tc.r6502_tc.struct
-- VHDL Architecture R6502_TC.R6502_TC.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 22:34:11 15.09.2018
-- by - eda.UNKNOWN (ENTW1)
-- at - 14:13:53 08.03.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
library r6502_tc;
LIBRARY R6502_TC;
 
architecture struct of r6502_tc is
ARCHITECTURE struct OF R6502_TC IS
 
-- Architecture declarations
 
102,35 → 72,35
 
 
-- Component Declarations
component core
port (
clk_clk_i : in std_logic ;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic ;
nmi_n_i : in std_logic ;
rdy_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
COMPONENT Core
PORT (
clk_clk_i : IN std_logic ;
d_i : IN std_logic_vector (7 DOWNTO 0);
irq_n_i : IN std_logic ;
nmi_n_i : IN std_logic ;
rdy_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
so_n_i : IN std_logic ;
a_o : OUT std_logic_vector (15 DOWNTO 0);
d_o : OUT std_logic_vector (7 DOWNTO 0);
rd_o : OUT std_logic ;
sync_o : OUT std_logic ;
wr_n_o : OUT std_logic ;
wr_o : OUT std_logic
);
end component;
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
for all : core use entity r6502_tc.core;
FOR ALL : Core USE ENTITY R6502_TC.Core;
-- pragma synthesis_on
 
 
begin
BEGIN
 
-- Instance port mappings.
U_0 : core
port map (
U_0 : Core
PORT MAP (
clk_clk_i => clk_clk_i,
d_i => d_i,
irq_n_i => irq_n_i,
146,4 → 116,4
wr_o => wr_o
);
 
end struct;
END struct;
/trunk/rtl/vhdl/fsm_execution_unit.vhd
1,341 → 1,305
-- VHDL Entity r6502_tc.fsm_execution_unit.symbol
-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 11:35:43 11.09.2018
-- by - eda.UNKNOWN (ENTW1)
-- at - 15:57:20 20.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity fsm_execution_unit is
port(
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic;
nmi_i : in std_logic;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic;
reg_0flag_i : in std_logic;
reg_1flag_i : in std_logic;
reg_7flag_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
int_fetch_o : out std_logic;
int_reg_2flag_o : out std_logic;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic;
ld_sp_o : out std_logic;
load_regs_o : out std_logic;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic;
rst_nmi_o : out std_logic;
sel_pc_in_o : out std_logic;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic;
sel_sp_in_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
ENTITY FSM_Execution_Unit IS
PORT(
adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_sp_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic;
d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );
irq_n_i : IN std_logic;
nmi_i : IN std_logic;
q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );
rdy_i : IN std_logic;
reg_0flag_i : IN std_logic;
reg_1flag_i : IN std_logic;
reg_7flag_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
adr_o : OUT std_logic_vector (15 DOWNTO 0);
ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );
ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );
ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );
ld_pc_o : OUT std_logic;
ld_sp_o : OUT std_logic;
load_regs_o : OUT std_logic;
offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );
rd_o : OUT std_logic;
rst_nmi_o : OUT std_logic;
sel_pc_in_o : OUT std_logic;
sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_sp_as_o : OUT std_logic;
sel_sp_in_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
);
 
-- Declarations
 
end fsm_execution_unit ;
END FSM_Execution_Unit ;
 
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.11 2018/09/11 11:50:00 jens
-- - RESET generates SYNC now, 1 dead cycle delayed
-- - ADC / SBC flags and A like R6502 now
-- - Bug Fix ADC and SBC in decimal mode (all op codes -
-- "Overflow" flag was computed wrong)
-- - Interrupt priority order is now: BRK - NMI - IRQ
-- - Performance improvements on-going (Mealy -> Moore)
-- - Bug Fixes All Branch Instructions
-- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)
-- 3 cycles now if branch forward occur and the branch
-- instruction lies on a xxFEh location.
-- - Bug Fix Hardware Interrupts NMI & IRQ - "SYNC" now
--
-- Revision 1.11 BETA 2013/07/24 15:46:00 jens
-- - Changing the title block and internal revision history
-- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong)
--
-- Revision 1.10 2010/02/08 17:34:20 eda
-- BUGFIX for IRQn, NMIn and RTI
-- After detection of NMI or IRQ the address of the next instruction stacked wrong.
-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the
-- vector address is not loaded yet.
--
-- Revision 1.9 2010/02/08 17:32:19 eda
-- BUGFIX for IRQn, NMIn and RTI
-- After detection of NMI or IRQ the address of the next instruction stacked wrong.
-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the
-- vector address is not loaded yet.
--
-- Revision 1.8 2009/01/04 20:23:42 eda
-- *** EMERGENCY BUGFIX ***
-- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.
-- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist
-- when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from
-- $02FF and $0200, instead of $02FF and $0300)
--
-- Revision 1.7 2009/01/04 16:54:59 eda
-- - Removed unused bits in ALU (zw_ALUx)
--
-- Revision 1.6 2009/01/04 10:27:49 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 10:25:04 eda
-- Changes for cosmetic issues only
--
-- Revision 1.4 2009/01/03 16:53:01 eda
-- - Unused nets and blocks deleted
-- - Re-arragend symbols in block FSM_Execution_Unit
-- - Renamed blocks
-- - Input SO implemented
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Re-arragend symbols in block FSM_Execution_Unit
-- - Renamed blocks
-- - Input SO implemented
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
-- Jens-D. Gutschmidt Project: R6502_TC
 
-- scantara2003@yahoo.de
 
-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
 
--
 
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
 
-- the Free Software Foundation, either version 3 of the License, or any later version.
 
--
 
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
 
--
 
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
 
--
 
-- CVS Revisins History
 
--
 
-- $Log: fsm.sm,v $
 
-- <<-- more -->>
 
-- Title: FSM Execution Unit for all op codes
 
-- Path: R6502_TC/FSM_Execution_Unit/fsm
 
-- Edited: by eda on 20 Feb 2010
 
--
-- VHDL Architecture r6502_tc.fsm_execution_unit.fsm
-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 22:31:13 15.09.2018
-- by - eda.UNKNOWN (ENTW1)
-- at - 15:57:21 20.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of fsm_execution_unit is
ARCHITECTURE fsm OF FSM_Execution_Unit IS
 
-- Architecture Declarations
signal reg_F : std_logic_vector( 7 DOWNTO 0 );
signal reg_sel_pc_in : std_logic;
signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_sp_as : std_logic;
signal reg_sel_sp_in : std_logic;
signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
signal sig_PC : std_logic_vector(15 DOWNTO 0);
signal sig_RD : std_logic;
signal sig_RWn : std_logic;
signal sig_SYNC : std_logic;
signal sig_WR : std_logic;
signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
signal zw_alu : std_logic_vector(9 DOWNTO 0);
signal zw_alu1 : std_logic_vector(9 DOWNTO 0);
signal zw_alu2 : std_logic_vector(9 DOWNTO 0);
signal zw_alu3 : std_logic_vector(9 DOWNTO 0);
signal zw_alu4 : std_logic_vector(9 DOWNTO 0);
signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
signal zw_bit : std_logic;
signal zw_irq : std_logic;
signal zw_ninebits4 : std_logic_vector(8 DOWNTO 0);
signal zw_nmi : std_logic;
signal zw_so : std_logic;
SIGNAL reg_F : std_logic_vector( 7 DOWNTO 0 );
SIGNAL reg_sel_pc_in : std_logic;
SIGNAL reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_sp_as : std_logic;
SIGNAL reg_sel_sp_in : std_logic;
SIGNAL sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
SIGNAL sig_PC : std_logic_vector(15 DOWNTO 0);
SIGNAL sig_RD : std_logic;
SIGNAL sig_RWn : std_logic;
SIGNAL sig_SYNC : std_logic;
SIGNAL sig_WR : std_logic;
SIGNAL zw_ALU : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_ALU1 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU2 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU3 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU4 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU5 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL zw_ALU6 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b1 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b2 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b3 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b4 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_so : std_logic;
 
subtype state_type is
std_logic_vector(7 downto 0);
SUBTYPE STATE_TYPE IS
std_logic_vector(7 DOWNTO 0);
-- Hard encoding
constant FETCH : state_type := "00000000";
constant s0001 : state_type := "00000001";
constant s0101 : state_type := "00000011";
constant s0201 : state_type := "00000010";
constant s0301 : state_type := "00000110";
constant s0401 : state_type := "00000111";
constant s1001 : state_type := "00000101";
constant s1101 : state_type := "00000100";
constant s1201 : state_type := "00001100";
constant s1301 : state_type := "00001101";
constant s1501 : state_type := "00001111";
constant s1601 : state_type := "00001110";
constant s1602 : state_type := "00001010";
constant s1603 : state_type := "00001011";
constant s1604 : state_type := "00001001";
constant s2601 : state_type := "00001000";
constant s2605 : state_type := "00011000";
constant s2604 : state_type := "00011001";
constant s2603 : state_type := "00011011";
constant s2602 : state_type := "00011010";
constant s2606 : state_type := "00011110";
constant s2607 : state_type := "00011111";
constant s2608 : state_type := "00011101";
constant s2609 : state_type := "00011100";
constant s2610 : state_type := "00010100";
constant s2611 : state_type := "00010101";
constant s1901 : state_type := "00010111";
constant s1902 : state_type := "00010110";
constant s2001 : state_type := "00010010";
constant s2002 : state_type := "00010011";
constant s2101 : state_type := "00010001";
constant s2102 : state_type := "00010000";
constant s2103 : state_type := "00110000";
constant s2201 : state_type := "00110001";
constant s2202 : state_type := "00110011";
constant s2203 : state_type := "00110010";
constant s2301 : state_type := "00110110";
constant s2302 : state_type := "00110111";
constant s2303 : state_type := "00110101";
constant s2304 : state_type := "00110100";
constant s2305 : state_type := "00111100";
constant s2401 : state_type := "00111101";
constant s2402 : state_type := "00111111";
constant s2403 : state_type := "00111110";
constant s2404 : state_type := "00111010";
constant s2405 : state_type := "00111011";
constant s1701 : state_type := "00111001";
constant s1702 : state_type := "00111000";
constant s1703 : state_type := "00101000";
constant s1704 : state_type := "00101001";
constant s1705 : state_type := "00101011";
constant s0901 : state_type := "00101010";
constant s0902 : state_type := "00101110";
constant s0903 : state_type := "00101111";
constant s9901 : state_type := "00101101";
constant s9903 : state_type := "00101100";
constant s9904 : state_type := "00100100";
constant s9905 : state_type := "00100101";
constant s9906 : state_type := "00100111";
constant s9902 : state_type := "00100110";
constant s2801 : state_type := "00100010";
constant s2901 : state_type := "00100011";
constant s3001 : state_type := "00100001";
constant s3101 : state_type := "00100000";
constant s1801 : state_type := "01100000";
constant s1803 : state_type := "01100001";
constant s1805 : state_type := "01100011";
constant s1806 : state_type := "01100010";
constant s1802 : state_type := "01100110";
constant s1804 : state_type := "01100111";
constant s1808 : state_type := "01100101";
constant s1807 : state_type := "01100100";
constant s1810 : state_type := "01101100";
constant s1809 : state_type := "01101101";
constant s1401 : state_type := "01101111";
constant s1403 : state_type := "01101110";
constant s1404 : state_type := "01101010";
constant s1402 : state_type := "01101011";
constant s1405 : state_type := "01101001";
constant s1406 : state_type := "01101000";
constant s1407 : state_type := "01111000";
constant s1408 : state_type := "01111001";
constant s0801 : state_type := "01111011";
constant s0803 : state_type := "01111010";
constant s0802 : state_type := "01111110";
constant s0601 : state_type := "01111111";
constant s0603 : state_type := "01111101";
constant s0604 : state_type := "01111100";
constant s0602 : state_type := "01110100";
constant s0605 : state_type := "01110101";
constant s0606 : state_type := "01110111";
constant s0607 : state_type := "01110110";
constant s0608 : state_type := "01110010";
constant s0501 : state_type := "01110011";
constant s0503 : state_type := "01110001";
constant s0505 : state_type := "01110000";
constant s0506 : state_type := "01010000";
constant s0502 : state_type := "01010001";
constant s0504 : state_type := "01010011";
constant s0507 : state_type := "01010010";
constant s0509 : state_type := "01010110";
constant s0510 : state_type := "01010111";
constant s0508 : state_type := "01010101";
constant s0701 : state_type := "01010100";
constant s0702 : state_type := "01011100";
constant s0703 : state_type := "01011101";
constant s2501 : state_type := "01011111";
constant s2503 : state_type := "01011110";
constant s2505 : state_type := "01011010";
constant s2506 : state_type := "01011011";
constant s2502 : state_type := "01011001";
constant s2504 : state_type := "01011000";
constant s2507 : state_type := "01001000";
constant s2508 : state_type := "01001001";
constant s2509 : state_type := "01001011";
constant s2510 : state_type := "01001010";
constant s2701 : state_type := "01001110";
constant s2702 : state_type := "01001111";
constant s2703 : state_type := "01001101";
constant s2704 : state_type := "01001100";
constant s2707 : state_type := "01000100";
constant s2706 : state_type := "01000101";
constant s2705 : state_type := "01000111";
constant s0905 : state_type := "01000110";
constant s0907 : state_type := "01000010";
constant s0906 : state_type := "01000011";
constant s0904 : state_type := "01000001";
constant RES : state_type := "01000000";
constant RES7 : state_type := "11000000";
CONSTANT FETCH : STATE_TYPE := "00000000";
CONSTANT s1 : STATE_TYPE := "00000001";
CONSTANT s2 : STATE_TYPE := "00000011";
CONSTANT s5 : STATE_TYPE := "00000010";
CONSTANT s3 : STATE_TYPE := "00000110";
CONSTANT s4 : STATE_TYPE := "00000111";
CONSTANT s12 : STATE_TYPE := "00000101";
CONSTANT s16 : STATE_TYPE := "00000100";
CONSTANT s17 : STATE_TYPE := "00001100";
CONSTANT s24 : STATE_TYPE := "00001101";
CONSTANT s25 : STATE_TYPE := "00001111";
CONSTANT s271 : STATE_TYPE := "00001110";
CONSTANT s273 : STATE_TYPE := "00001010";
CONSTANT s304 : STATE_TYPE := "00001011";
CONSTANT s307 : STATE_TYPE := "00001001";
CONSTANT s177 : STATE_TYPE := "00001000";
CONSTANT s180 : STATE_TYPE := "00011000";
CONSTANT s181 : STATE_TYPE := "00011001";
CONSTANT s182 : STATE_TYPE := "00011011";
CONSTANT s183 : STATE_TYPE := "00011010";
CONSTANT s184 : STATE_TYPE := "00011110";
CONSTANT s185 : STATE_TYPE := "00011111";
CONSTANT s186 : STATE_TYPE := "00011101";
CONSTANT s187 : STATE_TYPE := "00011100";
CONSTANT s188 : STATE_TYPE := "00010100";
CONSTANT s189 : STATE_TYPE := "00010101";
CONSTANT s190 : STATE_TYPE := "00010111";
CONSTANT s191 : STATE_TYPE := "00010110";
CONSTANT s192 : STATE_TYPE := "00010010";
CONSTANT s193 : STATE_TYPE := "00010011";
CONSTANT s377 : STATE_TYPE := "00010001";
CONSTANT s381 : STATE_TYPE := "00010000";
CONSTANT s378 : STATE_TYPE := "00110000";
CONSTANT s382 : STATE_TYPE := "00110001";
CONSTANT s379 : STATE_TYPE := "00110011";
CONSTANT s383 : STATE_TYPE := "00110010";
CONSTANT s384 : STATE_TYPE := "00110110";
CONSTANT s380 : STATE_TYPE := "00110111";
CONSTANT s385 : STATE_TYPE := "00110101";
CONSTANT s386 : STATE_TYPE := "00110100";
CONSTANT s387 : STATE_TYPE := "00111100";
CONSTANT s388 : STATE_TYPE := "00111101";
CONSTANT s389 : STATE_TYPE := "00111111";
CONSTANT s391 : STATE_TYPE := "00111110";
CONSTANT s392 : STATE_TYPE := "00111010";
CONSTANT s390 : STATE_TYPE := "00111011";
CONSTANT s393 : STATE_TYPE := "00111001";
CONSTANT s394 : STATE_TYPE := "00111000";
CONSTANT s395 : STATE_TYPE := "00101000";
CONSTANT s396 : STATE_TYPE := "00101001";
CONSTANT s397 : STATE_TYPE := "00101011";
CONSTANT s398 : STATE_TYPE := "00101010";
CONSTANT s399 : STATE_TYPE := "00101110";
CONSTANT s400 : STATE_TYPE := "00101111";
CONSTANT s401 : STATE_TYPE := "00101101";
CONSTANT s526 : STATE_TYPE := "00101100";
CONSTANT s527 : STATE_TYPE := "00100100";
CONSTANT s528 : STATE_TYPE := "00100101";
CONSTANT s529 : STATE_TYPE := "00100111";
CONSTANT s530 : STATE_TYPE := "00100110";
CONSTANT s531 : STATE_TYPE := "00100010";
CONSTANT s544 : STATE_TYPE := "00100011";
CONSTANT s545 : STATE_TYPE := "00100001";
CONSTANT s546 : STATE_TYPE := "00100000";
CONSTANT s547 : STATE_TYPE := "01100000";
CONSTANT s549 : STATE_TYPE := "01100001";
CONSTANT s550 : STATE_TYPE := "01100011";
CONSTANT s404 : STATE_TYPE := "01100010";
CONSTANT s556 : STATE_TYPE := "01100110";
CONSTANT s557 : STATE_TYPE := "01100111";
CONSTANT s579 : STATE_TYPE := "01100101";
CONSTANT s201 : STATE_TYPE := "01100100";
CONSTANT s202 : STATE_TYPE := "01101100";
CONSTANT s210 : STATE_TYPE := "01101101";
CONSTANT s211 : STATE_TYPE := "01101111";
CONSTANT s215 : STATE_TYPE := "01101110";
CONSTANT s217 : STATE_TYPE := "01101010";
CONSTANT s218 : STATE_TYPE := "01101011";
CONSTANT s222 : STATE_TYPE := "01101001";
CONSTANT s223 : STATE_TYPE := "01101000";
CONSTANT s224 : STATE_TYPE := "01111000";
CONSTANT s225 : STATE_TYPE := "01111001";
CONSTANT s226 : STATE_TYPE := "01111011";
CONSTANT s243 : STATE_TYPE := "01111010";
CONSTANT s244 : STATE_TYPE := "01111110";
CONSTANT s247 : STATE_TYPE := "01111111";
CONSTANT s344 : STATE_TYPE := "01111101";
CONSTANT s343 : STATE_TYPE := "01111100";
CONSTANT s250 : STATE_TYPE := "01110100";
CONSTANT s251 : STATE_TYPE := "01110101";
CONSTANT s351 : STATE_TYPE := "01110111";
CONSTANT s361 : STATE_TYPE := "01110110";
CONSTANT s360 : STATE_TYPE := "01110010";
CONSTANT s403 : STATE_TYPE := "01110011";
CONSTANT s406 : STATE_TYPE := "01110001";
CONSTANT s407 : STATE_TYPE := "01110000";
CONSTANT s409 : STATE_TYPE := "01010000";
CONSTANT s412 : STATE_TYPE := "01010001";
CONSTANT s413 : STATE_TYPE := "01010011";
CONSTANT s416 : STATE_TYPE := "01010010";
CONSTANT s418 : STATE_TYPE := "01010110";
CONSTANT s510 : STATE_TYPE := "01010111";
CONSTANT s553 : STATE_TYPE := "01010101";
CONSTANT s555 : STATE_TYPE := "01010100";
CONSTANT s558 : STATE_TYPE := "01011100";
CONSTANT s560 : STATE_TYPE := "01011101";
CONSTANT s561 : STATE_TYPE := "01011111";
CONSTANT s563 : STATE_TYPE := "01011110";
CONSTANT s564 : STATE_TYPE := "01011010";
CONSTANT s565 : STATE_TYPE := "01011011";
CONSTANT s566 : STATE_TYPE := "01011001";
CONSTANT s266 : STATE_TYPE := "01011000";
CONSTANT s301 : STATE_TYPE := "01001000";
CONSTANT s302 : STATE_TYPE := "01001001";
CONSTANT RES : STATE_TYPE := "01001011";
CONSTANT s511 : STATE_TYPE := "01001010";
CONSTANT s559 : STATE_TYPE := "01001110";
CONSTANT s562 : STATE_TYPE := "01001111";
CONSTANT s567 : STATE_TYPE := "01001101";
CONSTANT s568 : STATE_TYPE := "01001100";
CONSTANT s569 : STATE_TYPE := "01000100";
CONSTANT s570 : STATE_TYPE := "01000101";
CONSTANT s571 : STATE_TYPE := "01000111";
CONSTANT s572 : STATE_TYPE := "01000110";
CONSTANT s573 : STATE_TYPE := "01000010";
CONSTANT s574 : STATE_TYPE := "01000011";
CONSTANT s548 : STATE_TYPE := "01000001";
CONSTANT s551 : STATE_TYPE := "01000000";
CONSTANT s552 : STATE_TYPE := "11000000";
CONSTANT s575 : STATE_TYPE := "11000001";
CONSTANT s576 : STATE_TYPE := "11000011";
CONSTANT s577 : STATE_TYPE := "11000010";
CONSTANT s578 : STATE_TYPE := "11000110";
 
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
-- Declare any pre-registered internal signals
signal d_o_cld : std_logic_vector ( 7 downto 0 );
signal rd_o_cld : std_logic ;
signal sync_o_cld : std_logic ;
signal wr_n_o_cld : std_logic ;
signal wr_o_cld : std_logic ;
SIGNAL d_o_cld : std_logic_vector ( 7 DOWNTO 0 );
SIGNAL rd_o_cld : std_logic ;
SIGNAL sync_o_cld : std_logic ;
SIGNAL wr_n_o_cld : std_logic ;
SIGNAL wr_o_cld : std_logic ;
 
begin
BEGIN
 
-----------------------------------------------------------------
clocked_proc : process (
clocked_proc : PROCESS (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
BEGIN
IF (rst_rst_n_i = '0') THEN
current_state <= RES;
-- Default Reset Values
d_o_cld <= X"00";
343,7 → 307,7
sync_o_cld <= '0';
wr_n_o_cld <= '1';
wr_o_cld <= '0';
reg_F <= "00110100";
reg_F <= "00000100";
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_rb_in <= "00";
357,11 → 321,8
zw_b2 <= X"00";
zw_b3 <= X"00";
zw_b4 <= X"00";
zw_bit <= '0';
zw_irq <= '0';
zw_nmi <= '0';
zw_so <= '0';
elsif (clk_clk_i'event and clk_clk_i = '1') then
ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
current_state <= next_state;
-- Default Assignment To Internals
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
378,9 → 339,6
zw_b2 <= zw_b2;
zw_b3 <= zw_b3;
zw_b4 <= zw_b4;
zw_bit <= zw_bit;
zw_irq <= zw_irq;
zw_nmi <= zw_nmi;
zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
389,25 → 347,15
wr_o_cld <= sig_WR;
 
-- Combined Actions
case current_state is
when FETCH =>
CASE current_state IS
WHEN FETCH =>
zw_REG_OP <= d_i;
if ((d_i = X"00") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((nmi_i = '1') and (rdy_i = '1')) then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
zw_nmi <= '0';
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
zw_irq <= '0';
elsif ((d_i = X"69" or
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
sig_PC <= adr_sp_i;
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
sig_PC <= adr_sp_i;
ELSIF ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
414,16 → 362,17
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
d_i = X"71") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"06" or
zw_b1(0) <= reg_F(7);
ELSIF ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
d_i = X"1E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"90" or
ELSIF ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
430,43 → 379,45
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
d_i = X"70") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
zw_b3 <= adr_nxt_pc_i (15 downto 8);
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"18") and (rdy_i = '1')) then
elsif ((d_i = X"D8") and (rdy_i = '1')) then
elsif ((d_i = X"58") and (rdy_i = '1')) then
reg_F(2) <= '0';
elsif ((d_i = X"B8") and (rdy_i = '1')) then
elsif ((d_i = X"E0" or
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
d_i = X"EC") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C0" or
ELSIF ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
d_i = X"CC") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C6" or
ELSIF ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
d_i = X"DE") AND (rdy_i = '1')) THEN
zw_b4 <= X"FF";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"88") and (rdy_i = '1')) then
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"49" or
ELSIF ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
497,33 → 448,33
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
d_i = X"D1") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E6" or
ELSIF ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
d_i = X"FE") AND (rdy_i = '1')) THEN
zw_b4 <= X"01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"20") and (rdy_i = '1')) then
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A9" or
ELSIF ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
530,64 → 481,64
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
d_i = X"B1") AND (rdy_i = '1')) THEN
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A2" or
ELSIF ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
d_i = X"BE") AND (rdy_i = '1')) THEN
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A0" or
ELSIF ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
d_i = X"BC") AND (rdy_i = '1')) THEN
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"46" or
ELSIF ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
d_i = X"5E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"48") and (rdy_i = '1')) then
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"08") and (rdy_i = '1')) then
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"68") and (rdy_i = '1')) then
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"28") and (rdy_i = '1')) then
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"26" or
ELSIF ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
d_i = X"3E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"66" or
ELSIF ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
d_i = X"7E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"40") and (rdy_i = '1')) then
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"60") and (rdy_i = '1')) then
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"E9" or
ELSIF ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
594,96 → 545,96
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
d_i = X"F1") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"38") and (rdy_i = '1')) then
elsif ((d_i = X"F8") and (rdy_i = '1')) then
elsif ((d_i = X"78") and (rdy_i = '1')) then
reg_F(2) <= '1';
elsif ((d_i = X"85" or
zw_b1(0) <= reg_F(7);
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") and (rdy_i = '1')) then
d_i = X"91") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"86" or
ELSIF ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
d_i = X"8E") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"84" or
ELSIF ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
d_i = X"8C") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "01";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "10";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"98") and (rdy_i = '1')) then
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
reg_sel_reg <= "00";
reg_sel_rb_in <= "01";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "00";
reg_sel_rb_in <= "10";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "11";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
end if;
when s0001 =>
if (rdy_i = '1') then
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s0101 =>
if (rdy_i = '1') then
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
reg_sel_pc_in <= '0';
690,9 → 641,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s0201 =>
if (rdy_i = '1') then
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
reg_sel_pc_in <= '0';
699,25 → 650,27
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s0301 =>
if (rdy_i = '1') then
END IF;
WHEN s3 =>
sig_PC <= adr_pc_i;
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s0401 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
725,7 → 678,7
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
733,9 → 686,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s1001 =>
if (rdy_i = '1') then
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
reg_sel_pc_in <= '0';
742,9 → 695,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s1101 =>
if (rdy_i = '1') then
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
reg_sel_pc_in <= '0';
751,17 → 704,18
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s1201 =>
if (rdy_i = '1') then
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s1301 =>
if (rdy_i = '1') then
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
reg_sel_pc_in <= '0';
768,9 → 722,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s1501 =>
if (rdy_i = '1') then
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
778,156 → 732,179
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s1601 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
END IF;
WHEN s271 =>
IF (rdy_i = '1' and
zw_REG_OP = X"4C") THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "01";
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6C") THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
zw_b1 <= d_i;
end if;
when s1602 =>
if (rdy_i = '1') then
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
zw_b2 <= d_i;
end if;
when s1603 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
END IF;
WHEN s304 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "01";
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when s1604 =>
if (rdy_i = '1') then
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2601 =>
if (rdy_i = '1' and
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
zw_REG_OP = X"84")) THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
zw_REG_OP = X"94")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
zw_REG_OP = X"8C")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s2605 =>
if (rdy_i = '1') then
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s2604 =>
if (rdy_i = '1') then
END IF;
WHEN s182 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s2603 =>
if (rdy_i = '1') then
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s2602 =>
if (rdy_i = '1') then
END IF;
WHEN s184 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s185 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s2606 =>
if (rdy_i = '1') then
END IF;
WHEN s186 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s2607 =>
if (rdy_i = '1') then
END IF;
WHEN s187 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s188 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s2608 =>
if (rdy_i = '1') then
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s2609 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s2610 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s2611 =>
END IF;
WHEN s190 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s1901 =>
if (rdy_i = '1') then
WHEN s191 =>
sig_PC <= zw_b3 & zw_b1;
WHEN s192 =>
sig_PC <= d_i & zw_b1;
WHEN s193 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s377 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s1902 =>
END IF;
WHEN s381 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s2001 =>
if (rdy_i = '1') then
WHEN s378 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s2002 =>
END IF;
WHEN s382 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s2102 =>
if (rdy_i = '1') then
WHEN s383 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s2103 =>
if (rdy_i = '1') then
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
935,142 → 912,156
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2202 =>
if (rdy_i = '1') then
END IF;
WHEN s385 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s2203 =>
if (rdy_i = '1') then
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7 downto 6) <= d_i(7 downto 6);
reg_F(3 downto 0) <= d_i(3 downto 0);
reg_F <= d_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2301 =>
if (rdy_i = '1') then
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s2302 =>
if (rdy_i = '1') then
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s2303 =>
if (rdy_i = '1') then
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
reg_F <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "01";
end if;
when s2304 =>
if (rdy_i = '1') then
reg_sel_pc_val <= "11";
END IF;
WHEN s391 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s2305 =>
if (rdy_i = '1') then
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2401 =>
if (rdy_i = '1') then
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s2402 =>
if (rdy_i = '1') then
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s2403 =>
if (rdy_i = '1') then
END IF;
WHEN s394 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
end if;
when s2404 =>
if (rdy_i = '1') then
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s2405 =>
if (rdy_i = '1') then
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s1701 =>
if (rdy_i = '1') then
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s1703 =>
END IF;
WHEN s399 =>
sig_PC <= adr_sp_i;
when s1704 =>
WHEN s400 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "01";
when s1705 =>
if (rdy_i = '1') then
reg_sel_pc_val <= "11";
WHEN s401 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s0901 =>
if (rdy_i = '1') then
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s0902 =>
END IF;
WHEN s527 =>
sig_PC <= adr_sp_i;
when s0903 =>
WHEN s528 =>
sig_PC <= adr_sp_i;
when s9901 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s9903 =>
WHEN s529 =>
sig_PC <= X"FFFE";
WHEN s530 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s531 =>
IF (rdy_i = '1') THEN
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
END IF;
WHEN s544 =>
sig_PC <= adr_sp_i;
WHEN s545 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s9904 =>
if (rdy_i = '1') then
WHEN s546 =>
sig_PC <= adr_pc_i;
WHEN s547 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
end if;
when s9905 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "01";
end if;
when s9906 =>
reg_F(2) <= '1';
reg_F(5) <= '1';
if (rdy_i = '1') then
reg_sel_pc_val <= "11";
END IF;
WHEN s549 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s9902 =>
END IF;
WHEN s550 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s2801 =>
if (rdy_i = '1') then
WHEN s404 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
1079,9 → 1070,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2901 =>
if (rdy_i = '1') then
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
1090,9 → 1081,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s3001 =>
if (rdy_i = '1') then
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
1102,9 → 1093,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s3101 =>
if (rdy_i = '1') then
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
1113,20 → 1104,20
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s1801 =>
if (rdy_i = '1' and
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
sig_PC <= X"00" & d_i;
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1134,12 → 1125,12
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1147,12 → 1138,12
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1160,15 → 1151,15
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1179,9 → 1170,9
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1189,15 → 1180,15
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
zw_REG_OP = X"D5")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
1206,88 → 1197,93
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
zw_REG_OP = X"CC")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
zw_REG_OP = X"DD")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
zw_REG_OP = X"D9")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
zw_REG_OP = X"D1")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
zw_REG_OP = X"C1")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s1803 =>
if (rdy_i = '1') then
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s1805 =>
if (rdy_i = '1') then
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s1806 =>
if (rdy_i = '1') then
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s1802 =>
if (rdy_i = '1') then
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s1804 =>
if (rdy_i = '1') then
END IF;
WHEN s218 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s1808 =>
if (rdy_i = '1') then
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s1807 =>
if (rdy_i = '1') then
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s1810 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1295,10 → 1291,10
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1306,10 → 1302,10
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1317,13 → 1313,13
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1334,7 → 1330,7
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1342,13 → 1338,13
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s1809 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1356,11 → 1352,11
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1368,11 → 1364,11
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1380,14 → 1376,14
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
1398,8 → 1394,8
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1407,53 → 1403,53
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
end if;
when s1401 =>
if (rdy_i = '1' and
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
zw_REG_OP = X"E6")) THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
zw_REG_OP = X"F6")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
zw_REG_OP = X"EE")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
zw_REG_OP = X"FE")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s1403 =>
if (rdy_i = '1') then
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s1404 =>
if (rdy_i = '1') then
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s1402 =>
if (rdy_i = '1') then
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s1405 =>
if (rdy_i = '1') then
END IF;
WHEN s344 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
end if;
when s1406 =>
if (rdy_i = '1') then
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
zw_b1 <= d_alu_i;
end if;
when s1408 =>
END IF;
WHEN s251 =>
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
1461,17 → 1457,17
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s0801 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s0803 =>
if (rdy_i = '1') then
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
1480,89 → 1476,89
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s0802 =>
if (rdy_i = '1') then
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s0601 =>
if (rdy_i = '1' and
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
zw_REG_OP = X"5E")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
zw_REG_OP = X"46")) THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
zw_REG_OP = X"56")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
zw_REG_OP = X"4E")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s0603 =>
if (rdy_i = '1') then
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s0604 =>
if (rdy_i = '1') then
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s0602 =>
if (rdy_i = '1') then
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s0605 =>
if (rdy_i = '1') then
END IF;
WHEN s412 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
end if;
when s0607 =>
if (rdy_i = '1' and
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
zw_REG_OP = X"1E")) THEN
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
zw_REG_OP = X"5E")) THEN
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
zw_REG_OP = X"3E")) THEN
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
zw_REG_OP = X"7E")) THEN
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
end if;
when s0608 =>
END IF;
WHEN s418 =>
sig_PC <= adr_pc_i;
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
1571,194 → 1567,166
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s0501 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_alu(7);
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(NOT zw_alu(7) AND (q_a_i(7)) AND (d_i(7)));
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
zw_alu(0));
reg_F(0) <= zw_alu(8);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(0) <= zw_alu(9) OR
(zw_alu1(4) AND zw_alu(8) AND zw_alu(5)) OR
(zw_alu(8) AND zw_alu(7)) OR
(zw_alu(8) AND zw_alu(6));
reg_F(1) <= (NOT(zw_alu(4) OR
zw_alu(8) OR zw_alu(7) OR zw_alu(6) OR zw_alu(5) OR
zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)) OR
(zw_alu(4) AND
zw_alu(8) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5) AND
NOT(zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0))));
reg_F(6) <= (zw_alu2(5) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
reg_F(7) <= zw_alu2(5);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s0503 =>
if (rdy_i = '1') then
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s0505 =>
if (rdy_i = '1') then
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s0506 =>
if (rdy_i = '1') then
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s0502 =>
if (rdy_i = '1') then
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s0504 =>
if (rdy_i = '1') then
END IF;
WHEN s561 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s0507 =>
if (rdy_i = '1') then
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s0509 =>
if (rdy_i = '1' AND
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_alu(7);
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(NOT zw_alu(7) AND (q_a_i(7)) AND (d_i(7)));
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
zw_alu(0));
reg_F(0) <= zw_alu(8);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= zw_alu(9) OR
(zw_alu1(4) AND zw_alu(8) AND zw_alu(5)) OR
(zw_alu(8) AND zw_alu(7)) OR
(zw_alu(8) AND zw_alu(6));
reg_F(1) <= (NOT(zw_alu(4) OR
zw_alu(8) OR zw_alu(7) OR zw_alu(6) OR zw_alu(5) OR
zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)) OR
(zw_alu(4) AND
zw_alu(8) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5) AND
NOT(zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0))));
reg_F(6) <= (zw_alu2(5) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
reg_F(7) <= zw_alu2(5);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
end if;
when s0510 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_alu(7);
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(NOT zw_alu(7) AND (q_a_i(7)) AND (d_i(7)));
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
zw_alu(0));
reg_F(0) <= zw_alu(8);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= zw_alu(9) OR
(zw_alu1(4) AND zw_alu(8) AND zw_alu(5)) OR
(zw_alu(8) AND zw_alu(7)) OR
(zw_alu(8) AND zw_alu(6));
reg_F(1) <= (NOT(zw_alu(4) OR
zw_alu(8) OR zw_alu(7) OR zw_alu(6) OR zw_alu(5) OR
zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)) OR
(zw_alu(4) AND
zw_alu(8) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5) AND
NOT(zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0))));
reg_F(6) <= (zw_alu2(5) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
reg_F(7) <= zw_alu2(5);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s0508 =>
if (rdy_i = '1') then
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s0701 =>
zw_b3 <= adr_nxt_pc_i (15 downto 8);
if (rdy_i = '1' and (
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
1766,285 → 1734,1527
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "10";
zw_b2 <= d_i;
end if;
when s0702 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
end if;
when s0703 =>
if (rdy_i = '1') then
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2501 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
END IF;
WHEN RES =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_alu(7);
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
(NOT zw_alu(7) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
zw_alu(0));
reg_F(0) <= zw_alu(8);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(0) <= (zw_alu2(4));
reg_F(1) <= NOT(zw_alu2(3) OR zw_alu2(2) OR zw_alu2(1) OR zw_alu2(0) OR
zw_alu1(3) OR zw_alu1(2) OR zw_alu1(1) OR zw_alu1(0));
reg_F(6) <= (zw_alu2(3) XOR q_a_i(7)) AND ((q_a_i(7) XOR d_i(7)));
reg_F(7) <= zw_alu2(6);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2503 =>
if (rdy_i = '1') then
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
end if;
when s2505 =>
if (rdy_i = '1') then
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s2506 =>
if (rdy_i = '1') then
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s2502 =>
if (rdy_i = '1') then
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s2504 =>
if (rdy_i = '1') then
END IF;
WHEN s570 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
end if;
when s2507 =>
if (rdy_i = '1') then
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s2508 =>
if (rdy_i = '1') then
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s2509 =>
if (rdy_i = '1' AND
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_alu(7);
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
(NOT zw_alu(7) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
zw_alu(0));
reg_F(0) <= zw_alu(8);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= (zw_alu2(4));
reg_F(1) <= NOT(zw_alu2(3) OR zw_alu2(2) OR zw_alu2(1) OR zw_alu2(0) OR
zw_alu1(3) OR zw_alu1(2) OR zw_alu1(1) OR zw_alu1(0));
reg_F(6) <= (zw_alu2(3) XOR q_a_i(7)) AND ((q_a_i(7) XOR d_i(7)));
reg_F(7) <= zw_alu2(6);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
end if;
when s2510 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_alu(7);
reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
(NOT zw_alu(7) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR
zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR
zw_alu(0));
reg_F(0) <= zw_alu(8);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= (zw_alu2(4));
reg_F(1) <= NOT(zw_alu2(3) OR zw_alu2(2) OR zw_alu2(1) OR zw_alu2(0) OR
zw_alu1(3) OR zw_alu1(2) OR zw_alu1(1) OR zw_alu1(0));
reg_F(6) <= (zw_alu2(3) XOR q_a_i(7)) AND ((q_a_i(7) XOR d_i(7)));
reg_F(7) <= zw_alu2(6);
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2701 =>
if (rdy_i = '1') then
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
end if;
when s2702 =>
END IF;
WHEN s551 =>
sig_PC <= adr_sp_i;
when s2703 =>
WHEN s552 =>
sig_PC <= adr_sp_i;
when s2704 =>
if (nmi_i = '1') then
sig_PC <= X"FFFA";
else
sig_PC <= X"FFFE";
end if;
when s2707 =>
reg_F(2) <= '1';
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2706 =>
if (rdy_i = '1') then
sig_PC <= X"FFFB";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "01";
zw_b1 <= d_i;
end if;
when s2705 =>
if (rdy_i = '1') then
WHEN s575 =>
IF (rdy_i = '1') THEN
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "01";
reg_sel_pc_val <= "11";
reg_F(2) <= '1';
zw_b1 <= d_i;
end if;
when s0905 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "01";
zw_b1 <= d_i;
end if;
when s0907 =>
reg_F(2) <= '1';
if (rdy_i = '1') then
END IF;
WHEN s576 =>
IF (NMI_i = '1') THEN
sig_PC <= X"FFFA";
ELSE
sig_PC <= X"FFFE";
END IF;
WHEN s577 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s0906 =>
if (rdy_i = '1') then
END IF;
WHEN s578 =>
IF (rdy_i = '1') THEN
sig_PC <= X"FFFB";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "01";
reg_sel_pc_val <= "11";
reg_F(2) <= '1';
zw_b1 <= d_i;
end if;
when s0904 =>
if (nmi_i = '1') then
sig_PC <= X"FFFA";
else
sig_PC <= X"FFFE";
end if;
when RES =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
when RES7 =>
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when others =>
null;
end case;
end if;
end process clocked_proc;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
nextstate_proc : PROCESS (
adr_nxt_pc_i,
current_state,
d_i,
irq_n_i,
nmi_i,
rdy_i,
reg_F,
zw_REG_OP,
zw_b2,
zw_b3
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
WHEN FETCH =>
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
next_state <= s548;
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
next_state <= s548;
ELSIF ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") AND (rdy_i = '1')) THEN
next_state <= s510;
ELSIF ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") AND (rdy_i = '1')) THEN
next_state <= s266;
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
next_state <= s351;
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
next_state <= s526;
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
next_state <= s12;
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
next_state <= s16;
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
next_state <= s17;
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
next_state <= s24;
ELSIF ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") AND (rdy_i = '1')) THEN
next_state <= s226;
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") AND (rdy_i = '1')) THEN
next_state <= s226;
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
next_state <= s271;
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
next_state <= s397;
ELSIF ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
next_state <= s1;
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
next_state <= s377;
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
next_state <= s378;
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
next_state <= s379;
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
next_state <= s380;
ELSIF ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
next_state <= s387;
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
next_state <= s390;
ELSIF ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") AND (rdy_i = '1')) THEN
next_state <= s511;
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
next_state <= s2;
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
next_state <= s5;
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
next_state <= s3;
ELSIF ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") AND (rdy_i = '1')) THEN
next_state <= s177;
ELSIF ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") AND (rdy_i = '1')) THEN
next_state <= s177;
ELSIF ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") AND (rdy_i = '1')) THEN
next_state <= s177;
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
next_state <= s404;
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
next_state <= s556;
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
next_state <= s557;
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
next_state <= s579;
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF (rdy_i = '1') THEN
next_state <= s1;
ELSE
next_state <= FETCH;
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s1;
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s2;
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s5;
END IF;
WHEN s3 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s3;
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s4;
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s12;
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s16;
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s17;
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s24;
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s25;
END IF;
WHEN s271 =>
IF (rdy_i = '1' and
zw_REG_OP = X"4C") THEN
next_state <= s307;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6C") THEN
next_state <= s273;
ELSE
next_state <= s271;
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
next_state <= s304;
ELSE
next_state <= s273;
END IF;
WHEN s304 =>
IF (rdy_i = '1') THEN
next_state <= s307;
ELSE
next_state <= s304;
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s307;
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) THEN
next_state <= s184;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) THEN
next_state <= s185;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) THEN
next_state <= s183;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
next_state <= s182;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
next_state <= s180;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
next_state <= s181;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
next_state <= s186;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
next_state <= s185;
ELSE
next_state <= s177;
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
next_state <= s191;
ELSE
next_state <= s180;
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
next_state <= s189;
ELSE
next_state <= s181;
END IF;
WHEN s182 =>
IF (rdy_i = '1') THEN
next_state <= s191;
ELSE
next_state <= s182;
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
next_state <= s187;
ELSE
next_state <= s183;
END IF;
WHEN s184 =>
next_state <= FETCH;
WHEN s185 =>
IF (rdy_i = '1') THEN
next_state <= s190;
ELSE
next_state <= s185;
END IF;
WHEN s186 =>
IF (rdy_i = '1') THEN
next_state <= s188;
ELSE
next_state <= s186;
END IF;
WHEN s187 =>
next_state <= FETCH;
WHEN s188 =>
IF (rdy_i = '1') THEN
next_state <= s192;
ELSE
next_state <= s188;
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
next_state <= s191;
ELSE
next_state <= s189;
END IF;
WHEN s190 =>
next_state <= FETCH;
WHEN s191 =>
next_state <= s193;
WHEN s192 =>
next_state <= s193;
WHEN s193 =>
next_state <= FETCH;
WHEN s377 =>
IF (rdy_i = '1') THEN
next_state <= s381;
ELSE
next_state <= s377;
END IF;
WHEN s381 =>
next_state <= FETCH;
WHEN s378 =>
IF (rdy_i = '1') THEN
next_state <= s382;
ELSE
next_state <= s378;
END IF;
WHEN s382 =>
next_state <= FETCH;
WHEN s379 =>
IF (rdy_i = '1') THEN
next_state <= s383;
ELSE
next_state <= s379;
END IF;
WHEN s383 =>
IF (rdy_i = '1') THEN
next_state <= s384;
ELSE
next_state <= s383;
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s384;
END IF;
WHEN s380 =>
IF (rdy_i = '1') THEN
next_state <= s385;
ELSE
next_state <= s380;
END IF;
WHEN s385 =>
IF (rdy_i = '1') THEN
next_state <= s386;
ELSE
next_state <= s385;
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s386;
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
next_state <= s388;
ELSE
next_state <= s387;
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
next_state <= s389;
ELSE
next_state <= s388;
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
next_state <= s391;
ELSE
next_state <= s389;
END IF;
WHEN s391 =>
IF (rdy_i = '1') THEN
next_state <= s392;
ELSE
next_state <= s391;
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s392;
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
next_state <= s393;
ELSE
next_state <= s390;
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
next_state <= s394;
ELSE
next_state <= s393;
END IF;
WHEN s394 =>
IF (rdy_i = '1') THEN
next_state <= s395;
ELSE
next_state <= s394;
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
next_state <= s396;
ELSE
next_state <= s395;
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s396;
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
next_state <= s398;
ELSE
next_state <= s397;
END IF;
WHEN s398 =>
IF (rdy_i = '1') THEN
next_state <= s399;
ELSE
next_state <= s398;
END IF;
WHEN s399 =>
next_state <= s400;
WHEN s400 =>
next_state <= s401;
WHEN s401 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s401;
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
next_state <= s527;
ELSE
next_state <= s526;
END IF;
WHEN s527 =>
next_state <= s528;
WHEN s528 =>
next_state <= s529;
WHEN s529 =>
next_state <= s531;
WHEN s530 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s530;
END IF;
WHEN s531 =>
IF (rdy_i = '1') THEN
next_state <= s530;
ELSE
next_state <= s531;
END IF;
WHEN s544 =>
next_state <= s550;
WHEN s545 =>
next_state <= s546;
WHEN s546 =>
next_state <= s547;
WHEN s547 =>
IF (rdy_i = '1') THEN
next_state <= s549;
ELSE
next_state <= s547;
END IF;
WHEN s549 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s549;
END IF;
WHEN s550 =>
next_state <= s545;
WHEN s404 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s404;
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s556;
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s557;
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s579;
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
next_state <= s224;
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) THEN
next_state <= s217;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) THEN
next_state <= s202;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) THEN
next_state <= s210;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) THEN
next_state <= s211;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) THEN
next_state <= s215;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) THEN
next_state <= s218;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
next_state <= s217;
ELSE
next_state <= s201;
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
next_state <= s224;
ELSE
next_state <= s202;
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
next_state <= s225;
ELSE
next_state <= s210;
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
next_state <= s225;
ELSE
next_state <= s211;
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
next_state <= s223;
ELSE
next_state <= s215;
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
next_state <= s224;
ELSE
next_state <= s217;
END IF;
WHEN s218 =>
IF (rdy_i = '1') THEN
next_state <= s222;
ELSE
next_state <= s218;
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
next_state <= s202;
ELSE
next_state <= s222;
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
next_state <= s225;
ELSE
next_state <= s223;
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s224;
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s224;
ELSE
next_state <= s225;
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) THEN
next_state <= s343;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) THEN
next_state <= s247;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) THEN
next_state <= s243;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) THEN
next_state <= s244;
ELSE
next_state <= s226;
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
next_state <= s343;
ELSE
next_state <= s243;
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
next_state <= s344;
ELSE
next_state <= s244;
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
next_state <= s343;
ELSE
next_state <= s247;
END IF;
WHEN s344 =>
IF (rdy_i = '1') THEN
next_state <= s343;
ELSE
next_state <= s344;
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
next_state <= s250;
ELSE
next_state <= s343;
END IF;
WHEN s250 =>
IF (rdy_i = '1') THEN
next_state <= s251;
ELSE
next_state <= s250;
END IF;
WHEN s251 =>
next_state <= FETCH;
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
next_state <= s361;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
next_state <= s360;
ELSE
next_state <= s351;
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s361;
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
next_state <= s361;
ELSE
next_state <= s360;
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) THEN
next_state <= s407;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) THEN
next_state <= s413;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) THEN
next_state <= s409;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) THEN
next_state <= s406;
ELSE
next_state <= s403;
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
next_state <= s413;
ELSE
next_state <= s406;
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
next_state <= s412;
ELSE
next_state <= s407;
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
next_state <= s413;
ELSE
next_state <= s409;
END IF;
WHEN s412 =>
IF (rdy_i = '1') THEN
next_state <= s413;
ELSE
next_state <= s412;
END IF;
WHEN s413 =>
IF (rdy_i = '1') THEN
next_state <= s416;
ELSE
next_state <= s413;
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) THEN
next_state <= s418;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) THEN
next_state <= s418;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) THEN
next_state <= s418;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) THEN
next_state <= s418;
ELSE
next_state <= s416;
END IF;
WHEN s418 =>
next_state <= FETCH;
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
next_state <= s565;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
next_state <= s560;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
next_state <= s553;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
next_state <= s555;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
next_state <= s555;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
next_state <= s558;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
next_state <= s561;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s510;
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
next_state <= s565;
ELSE
next_state <= s553;
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
next_state <= s564;
ELSE
next_state <= s555;
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
next_state <= s566;
ELSE
next_state <= s558;
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
next_state <= s565;
ELSE
next_state <= s560;
END IF;
WHEN s561 =>
IF (rdy_i = '1') THEN
next_state <= s563;
ELSE
next_state <= s561;
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
next_state <= s553;
ELSE
next_state <= s563;
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s565;
ELSE
next_state <= s564;
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s565;
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
next_state <= s564;
ELSE
next_state <= s566;
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s301;
ELSE
next_state <= s266;
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s302;
ELSE
next_state <= s301;
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s302;
END IF;
WHEN RES =>
next_state <= s544;
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
next_state <= s574;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
next_state <= s569;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
next_state <= s559;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
next_state <= s562;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
next_state <= s567;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
next_state <= s568;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
next_state <= s570;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s511;
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
next_state <= s574;
ELSE
next_state <= s559;
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
next_state <= s573;
ELSE
next_state <= s562;
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
next_state <= s573;
ELSE
next_state <= s567;
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
next_state <= s571;
ELSE
next_state <= s568;
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
next_state <= s574;
ELSE
next_state <= s569;
END IF;
WHEN s570 =>
IF (rdy_i = '1') THEN
next_state <= s572;
ELSE
next_state <= s570;
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
next_state <= s573;
ELSE
next_state <= s571;
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
next_state <= s559;
ELSE
next_state <= s572;
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s574;
ELSE
next_state <= s573;
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s574;
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
next_state <= s551;
ELSE
next_state <= s548;
END IF;
WHEN s551 =>
next_state <= s552;
WHEN s552 =>
next_state <= s576;
WHEN s575 =>
IF (rdy_i = '1') THEN
next_state <= s577;
ELSE
next_state <= s575;
END IF;
WHEN s576 =>
IF (NMI_i = '1') THEN
next_state <= s578;
ELSE
next_state <= s575;
END IF;
WHEN s577 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s577;
END IF;
WHEN s578 =>
IF (rdy_i = '1') THEN
next_state <= s577;
ELSE
next_state <= s578;
END IF;
WHEN OTHERS =>
next_state <= RES;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
current_state,
2066,11 → 3276,14
reg_sel_sp_as,
reg_sel_sp_in,
sig_PC,
zw_ALU,
zw_ALU1,
zw_ALU2,
zw_ALU3,
zw_ALU4,
zw_ALU5,
zw_ALU6,
zw_REG_OP,
zw_alu,
zw_alu1,
zw_alu2,
zw_alu3,
zw_b1,
zw_b2,
zw_b3,
2077,7 → 3290,7
zw_b4
)
-----------------------------------------------------------------
begin
BEGIN
-- Default Assignment
a_o <= sig_PC;
adr_o <= X"0000";
2084,8 → 3297,6
ch_a_o <= X"00";
ch_b_o <= X"00";
d_regs_in_o <= X"00";
int_fetch_o <= '0';
int_reg_2flag_o <= reg_F(2);
ld_o <= "00";
ld_pc_o <= '0';
ld_sp_o <= '0';
2105,30 → 3316,24
sig_RWn <= '1';
sig_SYNC <= '0';
sig_WR <= '0';
zw_alu <= "00" & X"00";
zw_alu1 <= "00" & X"00";
zw_alu2 <= "00" & X"00";
zw_alu3 <= "00" & X"00";
zw_alu4 <= "00" & X"00";
zw_ninebits4 <= '0' & X"00";
zw_ALU <= '0' & X"00";
zw_ALU1 <= '0' & X"0";
zw_ALU2 <= '0' & X"0";
zw_ALU3 <= '0' & X"0";
zw_ALU4 <= '0' & X"0";
zw_ALU5 <= X"0";
zw_ALU6 <= X"0";
 
-- Combined Actions
case current_state is
when FETCH =>
CASE current_state IS
WHEN FETCH =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= NOT (rdy_i);
int_fetch_o <= '1';
if ((d_i = X"00") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0901;
elsif ((nmi_i = '1') and (rdy_i = '1')) then
next_state <= s2701;
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
next_state <= s2701;
elsif ((d_i = X"69" or
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
2135,18 → 3340,16
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
d_i = X"71") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0501;
elsif ((d_i = X"06" or
ELSIF ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
d_i = X"1E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0601;
elsif ((d_i = X"90" or
ELSIF ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
2153,59 → 3356,51
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
d_i = X"70") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0701;
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0801;
elsif ((d_i = X"18") and (rdy_i = '1')) then
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1001;
elsif ((d_i = X"D8") and (rdy_i = '1')) then
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1101;
elsif ((d_i = X"58") and (rdy_i = '1')) then
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1201;
elsif ((d_i = X"B8") and (rdy_i = '1')) then
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1301;
elsif ((d_i = X"E0" or
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
d_i = X"EC") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1801;
elsif ((d_i = X"C0" or
ELSIF ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
d_i = X"CC") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1801;
elsif ((d_i = X"C6" or
ELSIF ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
d_i = X"DE") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1401;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1501;
elsif ((d_i = X"88") and (rdy_i = '1')) then
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1501;
elsif ((d_i = X"49" or
ELSIF ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
2236,35 → 3431,29
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
d_i = X"D1") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1801;
elsif ((d_i = X"E6" or
ELSIF ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
d_i = X"FE") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1401;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1501;
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1501;
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1601;
elsif ((d_i = X"20") and (rdy_i = '1')) then
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1701;
elsif ((d_i = X"A9" or
ELSIF ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
2271,76 → 3460,63
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
d_i = X"B1") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1801;
elsif ((d_i = X"A2" or
ELSIF ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
d_i = X"BE") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1801;
elsif ((d_i = X"A0" or
ELSIF ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
d_i = X"BC") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1801;
elsif ((d_i = X"46" or
ELSIF ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
d_i = X"5E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0601;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0001;
elsif ((d_i = X"48") and (rdy_i = '1')) then
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1901;
elsif ((d_i = X"08") and (rdy_i = '1')) then
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2001;
elsif ((d_i = X"68") and (rdy_i = '1')) then
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2101;
elsif ((d_i = X"28") and (rdy_i = '1')) then
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2201;
elsif ((d_i = X"26" or
ELSIF ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
d_i = X"3E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0601;
elsif ((d_i = X"66" or
ELSIF ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
d_i = X"7E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0601;
elsif ((d_i = X"40") and (rdy_i = '1')) then
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2301;
elsif ((d_i = X"60") and (rdy_i = '1')) then
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2401;
elsif ((d_i = X"E9" or
ELSIF ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
2347,224 → 3523,155
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
d_i = X"F1") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2501;
elsif ((d_i = X"38") and (rdy_i = '1')) then
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0101;
elsif ((d_i = X"F8") and (rdy_i = '1')) then
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0201;
elsif ((d_i = X"78") and (rdy_i = '1')) then
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0301;
elsif ((d_i = X"85" or
ELSIF ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") and (rdy_i = '1')) then
d_i = X"91") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2601;
elsif ((d_i = X"86" or
ELSIF ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
d_i = X"8E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2601;
elsif ((d_i = X"84" or
ELSIF ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
d_i = X"8C") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2601;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0401;
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2801;
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2901;
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s3001;
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s3101;
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0401;
elsif ((d_i = X"98") and (rdy_i = '1')) then
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0401;
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0401;
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0401;
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0401;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0001;
else
next_state <= FETCH;
end if;
when s0001 =>
if (rdy_i = '1') then
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s0001;
end if;
when s0101 =>
if (rdy_i = '1') then
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s0101;
end if;
when s0201 =>
if (rdy_i = '1') then
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s0201;
end if;
when s0301 =>
if (rdy_i = '1') then
END IF;
WHEN s3 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s0301;
end if;
when s0401 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
adr_o <= X"01" & d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s0401;
end if;
when s1001 =>
if (rdy_i = '1') then
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s1001;
end if;
when s1101 =>
if (rdy_i = '1') then
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s1101;
end if;
when s1201 =>
if (rdy_i = '1') then
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s1201;
end if;
when s1301 =>
if (rdy_i = '1') then
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s1301;
end if;
when s1501 =>
if (rdy_i = '1') then
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s1501;
end if;
when s1601 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
ld_pc_o <= '1';
next_state <= s1604;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
next_state <= s1602;
else
next_state <= s1601;
end if;
when s1602 =>
if (rdy_i = '1') then
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1603;
else
next_state <= s1602;
end if;
when s1603 =>
if (rdy_i = '1') then
next_state <= s1604;
else
next_state <= s1603;
end if;
when s1604 =>
if (rdy_i = '1') then
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s1604;
end if;
when s2601 =>
if (rdy_i = '1' and
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
zw_REG_OP = X"84")) THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
2571,72 → 3678,65
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2611;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
zw_REG_OP = X"94")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s2602;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
zw_REG_OP = X"8C")) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2603;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s2604;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
next_state <= s2604;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
next_state <= s2605;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s2606;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
next_state <= s2602;
else
next_state <= s2601;
end if;
when s2605 =>
if (rdy_i = '1') then
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
next_state <= s2608;
else
next_state <= s2605;
end if;
when s2604 =>
if (rdy_i = '1') then
END IF;
WHEN s182 =>
sig_RWn <= '1';
sig_RD <= '1';
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2609;
else
next_state <= s2604;
end if;
when s2603 =>
if (rdy_i = '1') then
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
2643,12 → 3743,11
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2611;
else
next_state <= s2603;
end if;
when s2602 =>
if (rdy_i = '1') then
END IF;
WHEN s184 =>
sig_SYNC <= '1';
WHEN s185 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
2655,61 → 3754,39
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2611;
else
next_state <= s2602;
end if;
when s2606 =>
if (rdy_i = '1') then
next_state <= s2607;
else
next_state <= s2606;
end if;
when s2607 =>
if (rdy_i = '1') then
END IF;
WHEN s187 =>
sig_SYNC <= '1';
WHEN s188 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
next_state <= s2610;
else
next_state <= s2607;
end if;
when s2608 =>
if (rdy_i = '1') then
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2609;
else
next_state <= s2608;
end if;
when s2609 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
next_state <= s2611;
else
next_state <= s2609;
end if;
when s2610 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2611;
else
next_state <= s2610;
end if;
when s2611 =>
END IF;
WHEN s190 =>
sig_SYNC <= '1';
next_state <= FETCH;
when s1901 =>
if (rdy_i = '1') then
WHEN s191 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
WHEN s192 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
WHEN s193 =>
sig_SYNC <= '1';
WHEN s377 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
2716,172 → 3793,98
sig_D_OUT <= q_a_i;
ld_o <= "11";
ld_sp_o <= '1';
next_state <= s1902;
else
next_state <= s1901;
end if;
when s1902 =>
END IF;
WHEN s381 =>
sig_SYNC <= '1';
next_state <= FETCH;
when s2001 =>
if (rdy_i = '1') then
WHEN s378 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"30";
sig_D_OUT <= reg_F;
ld_o <= "11";
ld_sp_o <= '1';
next_state <= s2002;
else
next_state <= s2001;
end if;
when s2002 =>
END IF;
WHEN s382 =>
sig_SYNC <= '1';
next_state <= FETCH;
when s2101 =>
if (rdy_i = '1') then
WHEN s379 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
next_state <= s2102;
else
next_state <= s2101;
end if;
when s2102 =>
if (rdy_i = '1') then
next_state <= s2103;
else
next_state <= s2102;
end if;
when s2103 =>
if (rdy_i = '1') then
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s2103;
end if;
when s2201 =>
if (rdy_i = '1') then
END IF;
WHEN s380 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
next_state <= s2202;
else
next_state <= s2201;
end if;
when s2202 =>
if (rdy_i = '1') then
next_state <= s2203;
else
next_state <= s2202;
end if;
when s2203 =>
if (rdy_i = '1') then
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s2203;
end if;
when s2301 =>
if (rdy_i = '1') then
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
next_state <= s2302;
else
next_state <= s2301;
end if;
when s2302 =>
if (rdy_i = '1') then
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
next_state <= s2303;
else
next_state <= s2302;
end if;
when s2303 =>
if (rdy_i = '1') then
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
next_state <= s2304;
else
next_state <= s2303;
end if;
when s2304 =>
if (rdy_i = '1') then
next_state <= s2305;
else
next_state <= s2304;
end if;
when s2305 =>
if (rdy_i = '1') then
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s2305;
end if;
when s2401 =>
if (rdy_i = '1') then
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
next_state <= s2402;
else
next_state <= s2401;
end if;
when s2402 =>
if (rdy_i = '1') then
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
next_state <= s2403;
else
next_state <= s2402;
end if;
when s2403 =>
if (rdy_i = '1') then
next_state <= s2404;
else
next_state <= s2403;
end if;
when s2404 =>
if (rdy_i = '1') then
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2405;
else
next_state <= s2404;
end if;
when s2405 =>
if (rdy_i = '1') then
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s2405;
end if;
when s1701 =>
if (rdy_i = '1') then
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
next_state <= s1702;
else
next_state <= s1701;
end if;
when s1702 =>
if (rdy_i = '1') then
END IF;
WHEN s398 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
next_state <= s1703;
else
next_state <= s1702;
end if;
when s1703 =>
END IF;
WHEN s399 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
2888,21 → 3891,15
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
next_state <= s1704;
when s1704 =>
next_state <= s1705;
when s1705 =>
if (rdy_i = '1') then
WHEN s401 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s1705;
end if;
when s0901 =>
if (rdy_i = '1') then
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
2909,12 → 3906,9
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_nxt_pc_i (15 downto 8);
next_state <= s0902;
else
next_state <= s0901;
end if;
when s0902 =>
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s527 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
2921,124 → 3915,86
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
next_state <= s0903;
when s0903 =>
WHEN s528 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR
("001" & '1' & X"0");
next_state <= s0904;
when s9901 =>
sig_D_OUT <= reg_F OR X"10";
WHEN s530 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s544 =>
ld_o <= "11";
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
next_state <= s9902;
else
next_state <= s9901;
end if;
when s9903 =>
WHEN s545 =>
adr_o <= X"FFFB";
ld_o <= "11";
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
next_state <= s9904;
else
next_state <= s9903;
end if;
when s9904 =>
WHEN s546 =>
ld_o <= "11";
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
next_state <= s9905;
else
next_state <= s9904;
end if;
when s9905 =>
if (rdy_i = '1') then
next_state <= s9906;
else
next_state <= s9905;
end if;
when s9906 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
WHEN s549 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s9906;
end if;
when s9902 =>
END IF;
WHEN s550 =>
ld_o <= "11";
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
next_state <= s9903;
else
next_state <= s9902;
end if;
when s2801 =>
if (rdy_i = '1') then
WHEN s404 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
load_regs_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s2801;
end if;
when s2901 =>
if (rdy_i = '1') then
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s2901;
end if;
when s3001 =>
if (rdy_i = '1') then
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
load_regs_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s3001;
end if;
when s3101 =>
if (rdy_i = '1') then
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s3101;
end if;
when s1801 =>
if (rdy_i = '1' and
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1810;
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i OR q_a_i;
3046,13 → 4002,12
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i XOR q_a_i;
3060,13 → 4015,12
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i AND q_a_i;
3074,24 → 4028,22
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
elsif ((rdy_i = '1' and
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
ld_o <= "11";
ld_pc_o <= '1';
zw_ALU <= unsigned ("00" & d_regs_out_i) + unsigned ("00" & NOT (d_i)) + 1;
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i;
3099,17 → 4051,15
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
zw_REG_OP = X"D5")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s1802;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
3118,718 → 4068,503
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
zw_REG_OP = X"CC")) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1803;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
zw_REG_OP = X"DD")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s1805;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
zw_REG_OP = X"D9")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
next_state <= s1805;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
zw_REG_OP = X"D1")) THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
next_state <= s1806;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
zw_REG_OP = X"C1")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s1804;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
next_state <= s1802;
else
next_state <= s1801;
end if;
when s1803 =>
if (rdy_i = '1') then
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1810;
else
next_state <= s1803;
end if;
when s1805 =>
if (rdy_i = '1') then
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1809;
else
next_state <= s1805;
end if;
when s1806 =>
if (rdy_i = '1') then
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
next_state <= s1807;
else
next_state <= s1806;
end if;
when s1802 =>
if (rdy_i = '1') then
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1810;
else
next_state <= s1802;
end if;
when s1804 =>
if (rdy_i = '1') then
next_state <= s1808;
else
next_state <= s1804;
end if;
when s1808 =>
if (rdy_i = '1') then
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
next_state <= s1803;
else
next_state <= s1808;
end if;
when s1807 =>
if (rdy_i = '1') then
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1809;
else
next_state <= s1807;
end if;
when s1810 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ("00" & d_regs_out_i) + unsigned ("00" & NOT (d_i)) + 1;
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s1810;
end if;
when s1809 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ("00" & d_regs_out_i) + unsigned ("00" & NOT (d_i)) + 1;
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s1810;
else
next_state <= s1809;
end if;
when s1401 =>
if (rdy_i = '1' and
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
zw_REG_OP = X"E6")) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1406;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
zw_REG_OP = X"F6")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s1402;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
zw_REG_OP = X"EE")) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1403;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
zw_REG_OP = X"FE")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s1404;
else
next_state <= s1401;
end if;
when s1403 =>
if (rdy_i = '1') then
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1406;
else
next_state <= s1403;
end if;
when s1404 =>
if (rdy_i = '1') then
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1405;
else
next_state <= s1404;
end if;
when s1402 =>
if (rdy_i = '1') then
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s1406;
else
next_state <= s1402;
end if;
when s1405 =>
if (rdy_i = '1') then
next_state <= s1406;
else
next_state <= s1405;
end if;
when s1406 =>
if (rdy_i = '1') then
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= zw_b4;
next_state <= s1407;
else
next_state <= s1406;
end if;
when s1407 =>
if (rdy_i = '1') then
END IF;
WHEN s250 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_b1;
next_state <= s1408;
else
next_state <= s1407;
end if;
when s1408 =>
END IF;
WHEN s251 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
when s0801 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0803;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0802;
else
next_state <= s0801;
end if;
when s0803 =>
if (rdy_i = '1') then
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s0803;
end if;
when s0802 =>
if (rdy_i = '1') then
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0803;
else
next_state <= s0802;
end if;
when s0601 =>
if (rdy_i = '1' and
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
zw_REG_OP = X"5E")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s0604;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
zw_REG_OP = X"46")) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0606;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
zw_REG_OP = X"56")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s0602;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
zw_REG_OP = X"4E")) THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0603;
else
next_state <= s0601;
end if;
when s0603 =>
if (rdy_i = '1') then
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0606;
else
next_state <= s0603;
end if;
when s0604 =>
if (rdy_i = '1') then
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0605;
else
next_state <= s0604;
end if;
when s0602 =>
if (rdy_i = '1') then
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0606;
else
next_state <= s0602;
end if;
when s0605 =>
if (rdy_i = '1') then
next_state <= s0606;
else
next_state <= s0605;
end if;
when s0606 =>
if (rdy_i = '1') then
next_state <= s0607;
else
next_state <= s0606;
end if;
when s0607 =>
if (rdy_i = '1' and
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
zw_REG_OP = X"1E")) THEN
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
next_state <= s0608;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
zw_REG_OP = X"5E")) THEN
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
next_state <= s0608;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
zw_REG_OP = X"3E")) THEN
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
next_state <= s0608;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
zw_REG_OP = X"7E")) THEN
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
next_state <= s0608;
else
next_state <= s0607;
end if;
when s0608 =>
END IF;
WHEN s418 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
next_state <= FETCH;
when s0501 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0510;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_alu(7 downto 0);
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s0502;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0503;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s0505;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
next_state <= s0505;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
next_state <= s0506;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s0504;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_alu3(7 downto 0);
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_alu3(7 downto 4) <= unsigned (zw_alu2(3 downto 0)) +
unsigned (zw_alu(8 downto 5));
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_alu3(3 downto 0) <= unsigned (zw_alu1(3 downto 0)) +
unsigned (zw_alu(3 downto 0));
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_alu2(3 downto 0) <= '0' &
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
zw_alu1(4);
zw_alu2(5) <= (zw_alu1(4) AND zw_alu(8) AND (NOT(zw_alu(5)) OR NOT(zw_alu(6)) OR NOT(zw_alu(7)))) OR
(NOT(zw_alu1(4)) AND zw_alu(8)) OR
(zw_alu1(4) AND NOT(zw_alu(8)) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5));
zw_alu2(6) <= zw_alu(9) OR
(zw_alu(8) AND zw_alu(7)) OR
(zw_alu(8) AND zw_alu(6));
zw_alu2(4) <= (zw_alu(8) AND NOT(zw_alu(7)) AND NOT(zw_alu(6)) AND zw_alu(5));
zw_alu1(3 downto 0) <= '0' & ((zw_alu1(4))) & ((zw_alu1(4))) & '0';
zw_alu1(4) <= zw_alu(4) OR
(zw_alu(3) AND zw_alu(2)) OR
(zw_alu(3) AND zw_alu(1));
zw_alu(9 downto 5) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4));
zw_alu(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) +
reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s0501;
end if;
when s0503 =>
if (rdy_i = '1') then
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0510;
else
next_state <= s0503;
end if;
when s0505 =>
if (rdy_i = '1') then
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0509;
else
next_state <= s0505;
end if;
when s0506 =>
if (rdy_i = '1') then
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
next_state <= s0508;
else
next_state <= s0506;
end if;
when s0502 =>
if (rdy_i = '1') then
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0510;
else
next_state <= s0502;
end if;
when s0504 =>
if (rdy_i = '1') then
next_state <= s0507;
else
next_state <= s0504;
end if;
when s0507 =>
if (rdy_i = '1') then
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
next_state <= s0503;
else
next_state <= s0507;
end if;
when s0509 =>
if (rdy_i = '1' AND
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_alu(7 downto 0);
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1' AND
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_alu3(7 downto 0);
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_alu3(7 downto 4) <= unsigned (zw_alu2(3 downto 0)) +
unsigned (zw_alu(8 downto 5));
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_alu3(3 downto 0) <= unsigned (zw_alu1(3 downto 0)) +
unsigned (zw_alu(3 downto 0));
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_alu2(3 downto 0) <= '0' &
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
zw_alu1(4);
zw_alu2(5) <= (zw_alu1(4) AND zw_alu(8) AND (NOT(zw_alu(5)) OR NOT(zw_alu(6)) OR NOT(zw_alu(7)))) OR
(NOT(zw_alu1(4)) AND zw_alu(8)) OR
(zw_alu1(4) AND NOT(zw_alu(8)) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5));
zw_alu2(6) <= zw_alu(9) OR
(zw_alu(8) AND zw_alu(7)) OR
(zw_alu(8) AND zw_alu(6));
zw_alu2(4) <= (zw_alu(8) AND NOT(zw_alu(7)) AND NOT(zw_alu(6)) AND zw_alu(5));
zw_alu1(3 downto 0) <= '0' & ((zw_alu1(4))) & ((zw_alu1(4))) & '0';
zw_alu1(4) <= zw_alu(4) OR
(zw_alu(3) AND zw_alu(2)) OR
(zw_alu(3) AND zw_alu(1));
zw_alu(9 downto 5) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4));
zw_alu(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) +
reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s0510;
else
next_state <= s0509;
end if;
when s0510 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_alu(7 downto 0);
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_alu3(7 downto 0);
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_alu3(7 downto 4) <= unsigned (zw_alu2(3 downto 0)) +
unsigned (zw_alu(8 downto 5));
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_alu3(3 downto 0) <= unsigned (zw_alu1(3 downto 0)) +
unsigned (zw_alu(3 downto 0));
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_alu2(3 downto 0) <= '0' &
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
(zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) &
zw_alu1(4);
zw_alu2(5) <= (zw_alu1(4) AND zw_alu(8) AND (NOT(zw_alu(5)) OR NOT(zw_alu(6)) OR NOT(zw_alu(7)))) OR
(NOT(zw_alu1(4)) AND zw_alu(8)) OR
(zw_alu1(4) AND NOT(zw_alu(8)) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5));
zw_alu2(6) <= zw_alu(9) OR
(zw_alu(8) AND zw_alu(7)) OR
(zw_alu(8) AND zw_alu(6));
zw_alu2(4) <= (zw_alu(8) AND NOT(zw_alu(7)) AND NOT(zw_alu(6)) AND zw_alu(5));
zw_alu1(3 downto 0) <= '0' & ((zw_alu1(4))) & ((zw_alu1(4))) & '0';
zw_alu1(4) <= zw_alu(4) OR
(zw_alu(3) AND zw_alu(2)) OR
(zw_alu(3) AND zw_alu(1));
zw_alu(9 downto 5) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4));
zw_alu(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) +
reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s0510;
end if;
when s0508 =>
if (rdy_i = '1') then
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0509;
else
next_state <= s0508;
end if;
when s0701 =>
if (rdy_i = '1' and (
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
3837,282 → 4572,196
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1') then
ELSIF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0702;
else
next_state <= s0701;
end if;
when s0702 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1') then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7)
& zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7)
& zw_b2(6 downto 0));
ELSIF (rdy_i = '1') THEN
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s0703;
else
next_state <= s0702;
end if;
when s0703 =>
if (rdy_i = '1') then
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s0703;
end if;
when s2501 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
END IF;
WHEN RES =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_pc_o <= '1';
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2510;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
reg_F(3) = '0') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_alu(7 downto 0);
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s2502;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2503;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s2505;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
next_state <= s2505;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
next_state <= s2506;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
next_state <= s2504;
elsif (rdy_i = '1' and
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
reg_F(3) = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_alu(7 downto 0);
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU(7 downto 4) <= unsigned ((zw_alu2(3 downto 0))) -
unsigned (zw_alu3(7 downto 4));
zw_ALU(3 downto 0) <= unsigned ((zw_alu1(3 downto 0))) -
unsigned (zw_alu3(3 downto 0));
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU3(7 downto 0) <= '0' &
(NOT zw_alu2(4)) &
(NOT zw_alu2(4)) &
'0' &
'0' &
(NOT zw_alu1(4)) &
(NOT zw_alu1(4)) &
'0';
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_alu2(5) <= (zw_alu1(4) AND zw_alu2(3) AND (NOT(zw_alu2(0)) OR NOT(zw_alu2(1)) OR NOT(zw_alu2(2)))) OR
(NOT(zw_alu1(4)) AND zw_alu2(3)) OR
(zw_alu1(4) AND NOT(zw_alu2(3)) AND zw_alu2(2) AND zw_alu2(1) AND zw_alu2(0));
zw_alu2(6) <= (zw_alu2(3));
zw_alu2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT(d_i(7 downto 4))) +
zw_alu1(4);
zw_alu1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT(d_i(3 downto 0))) +
reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s2501;
end if;
when s2503 =>
if (rdy_i = '1') then
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2510;
else
next_state <= s2503;
end if;
when s2505 =>
if (rdy_i = '1') then
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2509;
else
next_state <= s2505;
end if;
when s2506 =>
if (rdy_i = '1') then
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
next_state <= s2507;
else
next_state <= s2506;
end if;
when s2502 =>
if (rdy_i = '1') then
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2510;
else
next_state <= s2502;
end if;
when s2504 =>
if (rdy_i = '1') then
next_state <= s2508;
else
next_state <= s2504;
end if;
when s2507 =>
if (rdy_i = '1') then
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
next_state <= s2509;
else
next_state <= s2507;
end if;
when s2508 =>
if (rdy_i = '1') then
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
next_state <= s2503;
else
next_state <= s2508;
end if;
when s2509 =>
if (rdy_i = '1' AND
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_alu(7 downto 0);
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1' AND
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_alu(7 downto 0);
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU(7 downto 4) <= unsigned ((zw_alu2(3 downto 0))) -
unsigned (zw_alu3(7 downto 4));
zw_ALU(3 downto 0) <= unsigned ((zw_alu1(3 downto 0))) -
unsigned (zw_alu3(3 downto 0));
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU3(7 downto 0) <= '0' &
(NOT zw_alu2(4)) &
(NOT zw_alu2(4)) &
'0' &
'0' &
(NOT zw_alu1(4)) &
(NOT zw_alu1(4)) &
'0';
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_alu2(5) <= (zw_alu1(4) AND zw_alu2(3) AND (NOT(zw_alu2(0)) OR NOT(zw_alu2(1)) OR NOT(zw_alu2(2)))) OR
(NOT(zw_alu1(4)) AND zw_alu2(3)) OR
(zw_alu1(4) AND NOT(zw_alu2(3)) AND zw_alu2(2) AND zw_alu2(1) AND zw_alu2(0));
zw_alu2(6) <= (zw_alu2(3));
zw_alu2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT(d_i(7 downto 4))) +
zw_alu1(4);
zw_alu1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT(d_i(3 downto 0))) +
reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s2510;
else
next_state <= s2509;
end if;
when s2510 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_alu(7 downto 0);
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_alu(7 downto 0);
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU(7 downto 4) <= unsigned ((zw_alu2(3 downto 0))) -
unsigned (zw_alu3(7 downto 4));
zw_ALU(3 downto 0) <= unsigned ((zw_alu1(3 downto 0))) -
unsigned (zw_alu3(3 downto 0));
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU3(7 downto 0) <= '0' &
(NOT zw_alu2(4)) &
(NOT zw_alu2(4)) &
'0' &
'0' &
(NOT zw_alu1(4)) &
(NOT zw_alu1(4)) &
'0';
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_alu2(5) <= (zw_alu1(4) AND zw_alu2(3) AND (NOT(zw_alu2(0)) OR NOT(zw_alu2(1)) OR NOT(zw_alu2(2)))) OR
(NOT(zw_alu1(4)) AND zw_alu2(3)) OR
(zw_alu1(4) AND NOT(zw_alu2(3)) AND zw_alu2(2) AND zw_alu2(1) AND zw_alu2(0));
zw_alu2(6) <= (zw_alu2(3));
zw_alu2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT(d_i(7 downto 4))) +
zw_alu1(4);
zw_alu1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT(d_i(3 downto 0))) +
reg_F(0);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s2510;
end if;
when s2701 =>
if (rdy_i = '1') then
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
4119,11 → 4768,8
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
next_state <= s2702;
else
next_state <= s2701;
end if;
when s2702 =>
END IF;
WHEN s551 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
4130,89 → 4776,28
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
next_state <= s2703;
when s2703 =>
WHEN s552 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= (reg_F AND X"EF");
next_state <= s2704;
when s2704 =>
if (nmi_i = '1') then
next_state <= s2706;
else
next_state <= s2705;
end if;
when s2707 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
sig_D_OUT <= reg_F;
WHEN s576 =>
IF (NMI_i = '1') THEN
rst_nmi_o <= '1';
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s2707;
end if;
when s2706 =>
if (rdy_i = '1') then
next_state <= s2707;
else
next_state <= s2706;
end if;
when s2705 =>
if (rdy_i = '1') then
next_state <= s2707;
else
next_state <= s2705;
end if;
when s0905 =>
if (rdy_i = '1') then
next_state <= s0907;
else
next_state <= s0905;
end if;
when s0907 =>
if (rdy_i = '1') then
END IF;
WHEN s577 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
next_state <= FETCH;
else
next_state <= s0907;
end if;
when s0906 =>
if (rdy_i = '1') then
next_state <= s0907;
else
next_state <= s0906;
end if;
when s0904 =>
if (nmi_i = '1') then
rst_nmi_o <= '1';
next_state <= s0906;
else
next_state <= s0905;
end if;
when RES =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
next_state <= RES7;
when RES7 =>
ld_o <= "11";
ld_pc_o <= '1';
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
next_state <= s9901;
when others =>
next_state <= RES;
end case;
end process nextstate_proc;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
-- Concurrent Statements
-- Clocked output assignments
4221,4 → 4806,4
sync_o <= sync_o_cld;
wr_n_o <= wr_n_o_cld;
wr_o <= wr_o_cld;
end fsm;
END fsm;
/trunk/rtl/vhdl/core.vhd
1,311 → 1,291
-- VHDL Entity r6502_tc.core.symbol
-- VHDL Entity R6502_TC.Core.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 09:42:07 11.09.2018
-- by - eda.UNKNOWN (ENTW1)
-- at - 14:13:52 08.03.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity core is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
ENTITY Core IS
PORT(
clk_clk_i : IN std_logic;
d_i : IN std_logic_vector (7 DOWNTO 0);
irq_n_i : IN std_logic;
nmi_n_i : IN std_logic;
rdy_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
d_o : OUT std_logic_vector (7 DOWNTO 0);
rd_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
);
 
-- Declarations
 
end core ;
END Core ;
 
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.20 2013/07/24 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version
-- 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: struct.bd,v $
-- <<-- more -->>
-- Title: Core
-- Path: R6502_TC/Core/struct
-- Edited: by eda on 08 Feb 2010
--
-- VHDL Architecture r6502_tc.core.struct
-- VHDL Architecture R6502_TC.Core.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 11:46:25 11.09.2018
-- by - eda.UNKNOWN (ENTW1)
-- at - 14:13:53 08.03.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
library r6502_tc;
LIBRARY R6502_TC;
 
architecture struct of core is
ARCHITECTURE struct OF Core IS
 
-- Architecture declarations
 
-- Internal signal declarations
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
signal adr_o_i : std_logic_vector(15 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal adr_sp_o_i : std_logic_vector(15 downto 0);
signal ch_a_o_i : std_logic_vector(7 downto 0);
signal ch_b_o_i : std_logic_vector(7 downto 0);
signal d_alu_n_o_i : std_logic;
signal d_alu_o_i : std_logic_vector(7 downto 0);
signal d_alu_or_o_i : std_logic;
signal d_regs_in_o_i : std_logic_vector(7 downto 0);
signal d_regs_out_o_i : std_logic_vector(7 downto 0);
signal ld_o_i : std_logic_vector(1 downto 0);
signal ld_pc_o_i : std_logic;
signal ld_sp_o_i : std_logic;
signal load_regs_o_i : std_logic;
signal nmi_o_i : std_logic;
signal offset_o_i : std_logic_vector(15 downto 0);
signal q_a_o_i : std_logic_vector(7 downto 0);
signal q_x_o_i : std_logic_vector(7 downto 0);
signal q_y_o_i : std_logic_vector(7 downto 0);
signal reg_0flag_o_i : std_logic;
signal reg_1flag_o_i : std_logic;
signal reg_7flag_o_i : std_logic;
signal rst_nmi_o_i : std_logic;
signal sel_pc_in_o_i : std_logic;
signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
signal sel_reg_o_i : std_logic_vector(1 downto 0);
signal sel_sp_as_o_i : std_logic;
signal sel_sp_in_o_i : std_logic;
SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL adr_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL adr_sp_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL ch_a_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL ch_b_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL d_alu_n_o_i : std_logic;
SIGNAL d_alu_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL d_alu_or_o_i : std_logic;
SIGNAL d_regs_in_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL ld_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL ld_pc_o_i : std_logic;
SIGNAL ld_sp_o_i : std_logic;
SIGNAL load_regs_o_i : std_logic;
SIGNAL nmi_o_i : std_logic;
SIGNAL offset_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL q_a_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL q_x_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL q_y_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL reg_0flag_o_i : std_logic;
SIGNAL reg_1flag_o_i : std_logic;
SIGNAL reg_7flag_o_i : std_logic;
SIGNAL rst_nmi_o_i : std_logic;
SIGNAL sel_pc_in_o_i : std_logic;
SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_rb_in_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_reg_o_i : std_logic_vector(1 DOWNTO 0);
SIGNAL sel_sp_as_o_i : std_logic;
SIGNAL sel_sp_in_o_i : std_logic;
 
 
-- Component Declarations
component fsm_execution_unit
port (
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic ;
nmi_i : in std_logic ;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic ;
reg_0flag_i : in std_logic ;
reg_1flag_i : in std_logic ;
reg_7flag_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
int_fetch_o : out std_logic ;
int_reg_2flag_o : out std_logic ;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic ;
ld_sp_o : out std_logic ;
load_regs_o : out std_logic ;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic ;
rst_nmi_o : out std_logic ;
sel_pc_in_o : out std_logic ;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic ;
sel_sp_in_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
COMPONENT FSM_Execution_Unit
PORT (
adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_sp_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic ;
d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );
irq_n_i : IN std_logic ;
nmi_i : IN std_logic ;
q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );
rdy_i : IN std_logic ;
reg_0flag_i : IN std_logic ;
reg_1flag_i : IN std_logic ;
reg_7flag_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
so_n_i : IN std_logic ;
a_o : OUT std_logic_vector (15 DOWNTO 0);
adr_o : OUT std_logic_vector (15 DOWNTO 0);
ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );
ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );
ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );
ld_pc_o : OUT std_logic ;
ld_sp_o : OUT std_logic ;
load_regs_o : OUT std_logic ;
offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );
rd_o : OUT std_logic ;
rst_nmi_o : OUT std_logic ;
sel_pc_in_o : OUT std_logic ;
sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_sp_as_o : OUT std_logic ;
sel_sp_in_o : OUT std_logic ;
sync_o : OUT std_logic ;
wr_n_o : OUT std_logic ;
wr_o : OUT std_logic
);
end component;
component fsm_intnmi
port (
clk_clk_i : in std_logic ;
nmi_n_i : in std_logic ;
rst_nmi_i : in std_logic ;
rst_rst_n_i : in std_logic ;
nmi_o : out std_logic
END COMPONENT;
COMPONENT FSM_NMI
PORT (
clk_clk_i : IN std_logic ;
nmi_n_i : IN std_logic ;
rst_nmi_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
nmi_o : OUT std_logic
);
end component;
component reg_pc
port (
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic ;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic ;
sel_pc_in_i : in std_logic ;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
END COMPONENT;
COMPONENT RegBank_AXY
PORT (
clk_clk_i : IN std_logic ;
d_regs_in_i : IN std_logic_vector (7 DOWNTO 0);
load_regs_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0);
sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0);
sel_reg_i : IN std_logic_vector (1 DOWNTO 0);
d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0);
q_a_o : OUT std_logic_vector (7 DOWNTO 0);
q_x_o : OUT std_logic_vector (7 DOWNTO 0);
q_y_o : OUT std_logic_vector (7 DOWNTO 0)
);
end component;
component reg_sp
port (
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic ;
ld_low_i : in std_logic ;
ld_sp_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_sp_as_i : in std_logic ;
sel_sp_in_i : in std_logic ;
adr_sp_o : out std_logic_vector (15 downto 0)
END COMPONENT;
COMPONENT Reg_PC
PORT (
adr_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic ;
ld_i : IN std_logic_vector (1 DOWNTO 0);
ld_pc_i : IN std_logic ;
offset_i : IN std_logic_vector (15 DOWNTO 0);
rst_rst_n_i : IN std_logic ;
sel_pc_in_i : IN std_logic ;
sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0);
adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0);
adr_pc_o : OUT std_logic_vector (15 DOWNTO 0)
);
end component;
component regbank_axy
port (
clk_clk_i : in std_logic ;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
d_regs_out_o : out std_logic_vector (7 downto 0);
q_a_o : out std_logic_vector (7 downto 0);
q_x_o : out std_logic_vector (7 downto 0);
q_y_o : out std_logic_vector (7 downto 0)
END COMPONENT;
COMPONENT Reg_SP
PORT (
adr_low_i : IN std_logic_vector (7 DOWNTO 0);
clk_clk_i : IN std_logic ;
ld_low_i : IN std_logic ;
ld_sp_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
sel_sp_as_i : IN std_logic ;
sel_sp_in_i : IN std_logic ;
adr_sp_o : OUT std_logic_vector (15 DOWNTO 0)
);
end component;
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
for all : fsm_execution_unit use entity r6502_tc.fsm_execution_unit;
for all : fsm_intnmi use entity r6502_tc.fsm_intnmi;
for all : reg_pc use entity r6502_tc.reg_pc;
for all : reg_sp use entity r6502_tc.reg_sp;
for all : regbank_axy use entity r6502_tc.regbank_axy;
FOR ALL : FSM_Execution_Unit USE ENTITY R6502_TC.FSM_Execution_Unit;
FOR ALL : FSM_NMI USE ENTITY R6502_TC.FSM_NMI;
FOR ALL : RegBank_AXY USE ENTITY R6502_TC.RegBank_AXY;
FOR ALL : Reg_PC USE ENTITY R6502_TC.Reg_PC;
FOR ALL : Reg_SP USE ENTITY R6502_TC.Reg_SP;
-- pragma synthesis_on
 
 
begin
BEGIN
 
-- ModuleWare code(v1.12) for instance 'U_11' of 'add'
u_11combo_proc: process (ch_a_o_i, ch_b_o_i)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
variable temp_carry : std_logic;
begin
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i)
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & ch_a_o_i;
temp_din1 := '0' & ch_b_o_i;
temp_carry := '0';
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
d_alu_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8);
d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
reg_0flag_o_i <= temp_sum(8) ;
end process u_11combo_proc;
END PROCESS u_11combo_proc;
 
-- ModuleWare code(v1.12) for instance 'U_8' of 'inv'
reg_1flag_o_i <= not(d_alu_or_o_i);
-- ModuleWare code(v1.9) for instance 'U_8' of 'inv'
reg_1flag_o_i <= NOT(d_alu_or_o_i);
 
-- ModuleWare code(v1.12) for instance 'U_9' of 'inv'
reg_7flag_o_i <= not(d_alu_n_o_i);
-- ModuleWare code(v1.9) for instance 'U_9' of 'inv'
reg_7flag_o_i <= NOT(d_alu_n_o_i);
 
-- ModuleWare code(v1.12) for instance 'U_10' of 'inv'
d_alu_n_o_i <= not(d_alu_o_i(7));
-- ModuleWare code(v1.9) for instance 'U_10' of 'inv'
d_alu_n_o_i <= NOT(d_alu_o_i(7));
 
-- ModuleWare code(v1.12) for instance 'U_7' of 'por'
d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
-- ModuleWare code(v1.9) for instance 'U_7' of 'por'
d_alu_or_o_i <= d_alu_o_i(0) OR d_alu_o_i(1) OR d_alu_o_i(2) OR d_alu_o_i(3) OR d_alu_o_i(4) OR d_alu_o_i(5) OR d_alu_o_i(6) OR d_alu_o_i(7);
 
-- Instance port mappings.
U_4 : fsm_execution_unit
port map (
adr_nxt_pc_i => adr_nxt_pc_o_i,
adr_pc_i => adr_pc_o_i,
adr_sp_i => adr_sp_o_i,
clk_clk_i => clk_clk_i,
d_alu_i => d_alu_o_i,
d_i => d_i,
d_regs_out_i => d_regs_out_o_i,
irq_n_i => irq_n_i,
nmi_i => nmi_o_i,
q_a_i => q_a_o_i,
q_x_i => q_x_o_i,
q_y_i => q_y_o_i,
rdy_i => rdy_i,
reg_0flag_i => reg_0flag_o_i,
reg_1flag_i => reg_1flag_o_i,
reg_7flag_i => reg_7flag_o_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
a_o => a_o,
adr_o => adr_o_i,
ch_a_o => ch_a_o_i,
ch_b_o => ch_b_o_i,
d_o => d_o,
d_regs_in_o => d_regs_in_o_i,
int_fetch_o => open,
int_reg_2flag_o => open,
ld_o => ld_o_i,
ld_pc_o => ld_pc_o_i,
ld_sp_o => ld_sp_o_i,
load_regs_o => load_regs_o_i,
offset_o => offset_o_i,
rd_o => rd_o,
rst_nmi_o => rst_nmi_o_i,
sel_pc_in_o => sel_pc_in_o_i,
sel_pc_val_o => sel_pc_val_o_i,
sel_rb_in_o => sel_rb_in_o_i,
sel_rb_out_o => sel_rb_out_o_i,
sel_reg_o => sel_reg_o_i,
sel_sp_as_o => sel_sp_as_o_i,
sel_sp_in_o => sel_sp_in_o_i,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
U_4 : FSM_Execution_Unit
PORT MAP (
adr_nxt_pc_i => adr_nxt_pc_o_i,
adr_pc_i => adr_pc_o_i,
adr_sp_i => adr_sp_o_i,
clk_clk_i => clk_clk_i,
d_alu_i => d_alu_o_i,
d_i => d_i,
d_regs_out_i => d_regs_out_o_i,
irq_n_i => irq_n_i,
nmi_i => nmi_o_i,
q_a_i => q_a_o_i,
q_x_i => q_x_o_i,
q_y_i => q_y_o_i,
rdy_i => rdy_i,
reg_0flag_i => reg_0flag_o_i,
reg_1flag_i => reg_1flag_o_i,
reg_7flag_i => reg_7flag_o_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
a_o => a_o,
adr_o => adr_o_i,
ch_a_o => ch_a_o_i,
ch_b_o => ch_b_o_i,
d_o => d_o,
d_regs_in_o => d_regs_in_o_i,
ld_o => ld_o_i,
ld_pc_o => ld_pc_o_i,
ld_sp_o => ld_sp_o_i,
load_regs_o => load_regs_o_i,
offset_o => offset_o_i,
rd_o => rd_o,
rst_nmi_o => rst_nmi_o_i,
sel_pc_in_o => sel_pc_in_o_i,
sel_pc_val_o => sel_pc_val_o_i,
sel_rb_in_o => sel_rb_in_o_i,
sel_rb_out_o => sel_rb_out_o_i,
sel_reg_o => sel_reg_o_i,
sel_sp_as_o => sel_sp_as_o_i,
sel_sp_in_o => sel_sp_in_o_i,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
U_6 : fsm_intnmi
port map (
U_6 : FSM_NMI
PORT MAP (
clk_clk_i => clk_clk_i,
nmi_n_i => nmi_n_i,
rst_nmi_i => rst_nmi_o_i,
312,8 → 292,22
rst_rst_n_i => rst_rst_n_i,
nmi_o => nmi_o_i
);
U_0 : reg_pc
port map (
U_2 : RegBank_AXY
PORT MAP (
clk_clk_i => clk_clk_i,
d_regs_in_i => d_regs_in_o_i,
load_regs_i => load_regs_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_rb_in_i => sel_rb_in_o_i,
sel_rb_out_i => sel_rb_out_o_i,
sel_reg_i => sel_reg_o_i,
d_regs_out_o => d_regs_out_o_i,
q_a_o => q_a_o_i,
q_x_o => q_x_o_i,
q_y_o => q_y_o_i
);
U_0 : Reg_PC
PORT MAP (
adr_i => adr_o_i,
clk_clk_i => clk_clk_i,
ld_i => ld_o_i,
325,8 → 319,8
adr_nxt_pc_o => adr_nxt_pc_o_i,
adr_pc_o => adr_pc_o_i
);
U_1 : reg_sp
port map (
U_1 : Reg_SP
PORT MAP (
adr_low_i => adr_o_i(7 DOWNTO 0),
clk_clk_i => clk_clk_i,
ld_low_i => ld_o_i(0),
336,19 → 330,5
sel_sp_in_i => sel_sp_in_o_i,
adr_sp_o => adr_sp_o_i
);
U_2 : regbank_axy
port map (
clk_clk_i => clk_clk_i,
d_regs_in_i => d_regs_in_o_i,
load_regs_i => load_regs_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_rb_in_i => sel_rb_in_o_i,
sel_rb_out_i => sel_rb_out_o_i,
sel_reg_i => sel_reg_o_i,
d_regs_out_o => d_regs_out_o_i,
q_a_o => q_a_o_i,
q_x_o => q_x_o_i,
q_y_o => q_y_o_i
);
 
end struct;
END struct;
/trunk/rtl/vhdl/fsm_nmi.vhd
0,0 → 1,167
-- VHDL Entity R6502_TC.FSM_NMI.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 18:40:01 08.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY FSM_NMI IS
PORT(
clk_clk_i : IN std_logic;
nmi_n_i : IN std_logic;
rst_nmi_i : IN std_logic;
rst_rst_n_i : IN std_logic;
nmi_o : OUT std_logic
);
 
-- Declarations
 
END FSM_NMI ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
 
-- scantara2003@yahoo.de
 
-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
 
--
 
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
 
-- the Free Software Foundation, either version 3 of the License, or any later version.
 
--
 
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
 
--
 
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
 
--
 
-- CVS Revisins History
 
--
 
-- $Log: fsm.sm,v $
 
-- <<-- more -->>
 
-- Title: FSM for NMI
 
-- Path: R6502_TC/FSM_NMI/fsm
 
-- Edited: by eda on 08 Feb 2010
 
--
-- VHDL Architecture R6502_TC.FSM_NMI.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 18:40:01 08.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE fsm OF FSM_NMI IS
 
SUBTYPE STATE_TYPE IS
std_logic_vector(1 DOWNTO 0);
-- Hard encoding
CONSTANT idle : STATE_TYPE := "00";
CONSTANT idle1 : STATE_TYPE := "01";
CONSTANT idle2 : STATE_TYPE := "11";
CONSTANT IMP : STATE_TYPE := "10";
 
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
-- Declare any pre-registered internal signals
SIGNAL nmi_o_cld : std_logic ;
 
BEGIN
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
BEGIN
IF (rst_rst_n_i = '0') THEN
current_state <= idle;
-- Default Reset Values
nmi_o_cld <= '0';
ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
current_state <= next_state;
-- Default Assignment To Internals
nmi_o_cld <= '0';
 
-- Combined Actions
CASE current_state IS
WHEN IMP =>
nmi_o_cld <= '1';
IF (rst_nmi_i = '1') THEN
nmi_o_cld <= '0';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
current_state,
nmi_n_i,
rst_nmi_i
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
WHEN idle =>
IF (nmi_n_i = '1') THEN
next_state <= idle1;
ELSE
next_state <= idle;
END IF;
WHEN idle1 =>
IF (nmi_n_i = '0') THEN
next_state <= idle2;
ELSE
next_state <= idle1;
END IF;
WHEN idle2 =>
IF (nmi_n_i = '0') THEN
next_state <= IMP;
ELSE
next_state <= idle;
END IF;
WHEN IMP =>
IF (rst_nmi_i = '1') THEN
next_state <= idle;
ELSE
next_state <= IMP;
END IF;
WHEN OTHERS =>
next_state <= idle;
END CASE;
END PROCESS nextstate_proc;
-- Concurrent Statements
-- Clocked output assignments
nmi_o <= nmi_o_cld;
END fsm;
trunk/rtl/vhdl/fsm_nmi.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/vhdl/regbank_axy.vhd =================================================================== --- trunk/rtl/vhdl/regbank_axy.vhd (revision 26) +++ trunk/rtl/vhdl/regbank_axy.vhd (revision 25) @@ -1,196 +1,186 @@ --- VHDL Entity r6502_tc.regbank_axy.symbol +-- VHDL Entity R6502_TC.RegBank_AXY.symbol -- -- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 11:41:39 11.09.2018 +-- by - eda.UNKNOWN (ENTW1) +-- at - 18:39:49 08.02.2010 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -entity regbank_axy is - port( - clk_clk_i : in std_logic; - d_regs_in_i : in std_logic_vector (7 downto 0); - load_regs_i : in std_logic; - rst_rst_n_i : in std_logic; - sel_rb_in_i : in std_logic_vector (1 downto 0); - sel_rb_out_i : in std_logic_vector (1 downto 0); - sel_reg_i : in std_logic_vector (1 downto 0); - d_regs_out_o : out std_logic_vector (7 downto 0); - q_a_o : out std_logic_vector (7 downto 0); - q_x_o : out std_logic_vector (7 downto 0); - q_y_o : out std_logic_vector (7 downto 0) +ENTITY RegBank_AXY IS + PORT( + clk_clk_i : IN std_logic; + d_regs_in_i : IN std_logic_vector (7 DOWNTO 0); + load_regs_i : IN std_logic; + rst_rst_n_i : IN std_logic; + sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0); + sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0); + sel_reg_i : IN std_logic_vector (1 DOWNTO 0); + d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0); + q_a_o : OUT std_logic_vector (7 DOWNTO 0); + q_x_o : OUT std_logic_vector (7 DOWNTO 0); + q_y_o : OUT std_logic_vector (7 DOWNTO 0) ); -- Declarations -end regbank_axy ; +END RegBank_AXY ; --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.5 2013/07/24 11:11:00 jens --- - Changing the title block and internal revision history --- - Change mux 3-1 to mux 4-1 for vendors like Xilinx --- --- Revision 1.3 2009/01/04 10:20:50 eda --- Changes for cosmetic issues only --- --- Revision 1.2 2009/01/04 09:23:12 eda --- - Delete unused nets and blocks --- - Rename blocks --- - Re-arrage FSM symbols in block FSM_Execution_Unit --- --- Revision 1.1 2009/01/03 16:36:48 eda --- Production Release --- --- +-- Jens-D. Gutschmidt Project: R6502_TC +-- scantara2003@yahoo.de +-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- CVS Revisins History +-- +-- $Log: struct.bd,v $ +-- <<-- more -->> +-- Title: Register Bank for register A, X and Y +-- Path: R6502_TC/RegBank_AXY/struct +-- Edited: by eda on 08 Feb 2010 -- --- VHDL Architecture r6502_tc.regbank_axy.struct +-- VHDL Architecture R6502_TC.RegBank_AXY.struct -- -- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 11:44:39 11.09.2018 +-- by - eda.UNKNOWN (ENTW1) +-- at - 18:39:49 08.02.2010 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -architecture struct of regbank_axy is +ARCHITECTURE struct OF RegBank_AXY IS -- Architecture declarations -- Internal signal declarations - signal ld : std_logic_vector(2 downto 0); - signal load1_o_i : std_logic; - signal load2_o_i : std_logic; - signal load_o_i : std_logic; - signal q_mux_o_i : std_logic_vector(7 downto 0); - signal val_zero : std_logic_vector(7 downto 0); + SIGNAL ld : std_logic_vector(2 DOWNTO 0); + SIGNAL load1_o_i : std_logic; + SIGNAL load2_o_i : std_logic; + SIGNAL load_o_i : std_logic; + SIGNAL q_mux_o_i : std_logic_vector(7 DOWNTO 0); + SIGNAL val_zero : std_logic_vector(7 DOWNTO 0); -- Implicit buffer signal declarations - signal q_a_o_internal : std_logic_vector (7 downto 0); - signal q_x_o_internal : std_logic_vector (7 downto 0); - signal q_y_o_internal : std_logic_vector (7 downto 0); + SIGNAL q_a_o_internal : std_logic_vector (7 DOWNTO 0); + SIGNAL q_x_o_internal : std_logic_vector (7 DOWNTO 0); + SIGNAL q_y_o_internal : std_logic_vector (7 DOWNTO 0); - -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' - signal mw_U_0reg_cval : std_logic_vector(7 downto 0); + -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff' + SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0); - -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' - signal mw_U_4reg_cval : std_logic_vector(7 downto 0); + -- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff' + SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0); - -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'adff' - signal mw_U_5reg_cval : std_logic_vector(7 downto 0); + -- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff' + SIGNAL mw_U_5reg_cval : std_logic_vector(7 DOWNTO 0); -begin +BEGIN - -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' + -- ModuleWare code(v1.9) for instance 'U_0' of 'adff' q_a_o_internal <= mw_U_0reg_cval; - u_0seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then + u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i) + BEGIN + IF (rst_rst_n_i = '0') THEN mw_U_0reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load_o_i = '1') then + ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN + IF (load_o_i = '1') THEN mw_U_0reg_cval <= q_mux_o_i; - end if; - end if; - end process u_0seq_proc; + END IF; + END IF; + END PROCESS u_0seq_proc; - -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' + -- ModuleWare code(v1.9) for instance 'U_4' of 'adff' q_x_o_internal <= mw_U_4reg_cval; - u_4seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then + u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i) + BEGIN + IF (rst_rst_n_i = '0') THEN mw_U_4reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load1_o_i = '1') then + ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN + IF (load1_o_i = '1') THEN mw_U_4reg_cval <= q_mux_o_i; - end if; - end if; - end process u_4seq_proc; + END IF; + END IF; + END PROCESS u_4seq_proc; - -- ModuleWare code(v1.12) for instance 'U_5' of 'adff' + -- ModuleWare code(v1.9) for instance 'U_5' of 'adff' q_y_o_internal <= mw_U_5reg_cval; - u_5seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then + u_5seq_proc: PROCESS (clk_clk_i, rst_rst_n_i) + BEGIN + IF (rst_rst_n_i = '0') THEN mw_U_5reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load2_o_i = '1') then + ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN + IF (load2_o_i = '1') THEN mw_U_5reg_cval <= q_mux_o_i; - end if; - end if; - end process u_5seq_proc; + END IF; + END IF; + END PROCESS u_5seq_proc; - -- ModuleWare code(v1.12) for instance 'U_6' of 'and' - load_o_i <= load_regs_i and ld(0); + -- ModuleWare code(v1.9) for instance 'U_6' of 'and' + load_o_i <= load_regs_i AND ld(0); - -- ModuleWare code(v1.12) for instance 'U_7' of 'and' - load1_o_i <= load_regs_i and ld(1); + -- ModuleWare code(v1.9) for instance 'U_7' of 'and' + load1_o_i <= load_regs_i AND ld(1); - -- ModuleWare code(v1.12) for instance 'U_8' of 'and' - load2_o_i <= load_regs_i and ld(2); + -- ModuleWare code(v1.9) for instance 'U_8' of 'and' + load2_o_i <= load_regs_i AND ld(2); - -- ModuleWare code(v1.12) for instance 'U_2' of 'constval' + -- ModuleWare code(v1.9) for instance 'U_11' of 'constval' val_zero <= "00000000"; - -- ModuleWare code(v1.12) for instance 'U_1' of 'decoder1' - u_1combo_proc: process (sel_reg_i) - begin - ld <= (others => '0'); - case sel_reg_i is - when "00" => ld(0) <= '1'; - when "01" => ld(1) <= '1'; - when "10" => ld(2) <= '1'; - when others => ld <= (others => '0'); - end case; - end process u_1combo_proc; + -- ModuleWare code(v1.9) for instance 'U_1' of 'decoder1' + u_1combo_proc: PROCESS (sel_reg_i) + BEGIN + ld <= (OTHERS => '0'); + CASE sel_reg_i IS + WHEN "00" => ld(0) <= '1'; + WHEN "01" => ld(1) <= '1'; + WHEN "10" => ld(2) <= '1'; + WHEN OTHERS => ld <= (OTHERS => '0'); + END CASE; + END PROCESS u_1combo_proc; - -- ModuleWare code(v1.12) for instance 'U_3' of 'mux' - u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal, + -- ModuleWare code(v1.9) for instance 'U_2' of 'mux' + u_2combo_proc: PROCESS(q_a_o_internal, q_x_o_internal, q_y_o_internal, + val_zero, sel_rb_out_i) + BEGIN + CASE sel_rb_out_i IS + WHEN "00" => d_regs_out_o <= q_a_o_internal; + WHEN "01" => d_regs_out_o <= q_x_o_internal; + WHEN "10" => d_regs_out_o <= q_y_o_internal; + WHEN "11" => d_regs_out_o <= val_zero; + WHEN OTHERS => d_regs_out_o <= (OTHERS => 'X'); + END CASE; + END PROCESS u_2combo_proc; + + -- ModuleWare code(v1.9) for instance 'U_3' of 'mux' + u_3combo_proc: PROCESS(q_a_o_internal, q_y_o_internal, q_x_o_internal, d_regs_in_i, sel_rb_in_i) - begin - case sel_rb_in_i is - when "00" => q_mux_o_i <= q_a_o_internal; - when "01" => q_mux_o_i <= q_y_o_internal; - when "10" => q_mux_o_i <= q_x_o_internal; - when "11" => q_mux_o_i <= d_regs_in_i; - when others => q_mux_o_i <= (others => 'X'); - end case; - end process u_3combo_proc; + BEGIN + CASE sel_rb_in_i IS + WHEN "00" => q_mux_o_i <= q_a_o_internal; + WHEN "01" => q_mux_o_i <= q_y_o_internal; + WHEN "10" => q_mux_o_i <= q_x_o_internal; + WHEN "11" => q_mux_o_i <= d_regs_in_i; + WHEN OTHERS => q_mux_o_i <= (OTHERS => 'X'); + END CASE; + END PROCESS u_3combo_proc; - -- ModuleWare code(v1.12) for instance 'U_9' of 'mux' - u_9combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal, - val_zero, sel_rb_out_i) - begin - case sel_rb_out_i is - when "00" => d_regs_out_o <= q_a_o_internal; - when "01" => d_regs_out_o <= q_x_o_internal; - when "10" => d_regs_out_o <= q_y_o_internal; - when "11" => d_regs_out_o <= val_zero; - when others => d_regs_out_o <= (others => 'X'); - end case; - end process u_9combo_proc; - -- Instance port mappings. -- Implicit buffered output assignments @@ -198,4 +188,4 @@ q_x_o <= q_x_o_internal; q_y_o <= q_y_o_internal; -end struct; +END struct;
/trunk/TO_DO_list.txt
1,10 → 1,3
(September 15th 2018)
- (WORKING) Performance improvements
- (WORKING) Creating test strategy for RDY signal
- (DONE) Working on reported Bugs/Requests: Branches, Interrupts, ADC/SBC
- (DONE) Verifying all interrupts
- (90%) Finish working for Specification of cpu65C02_tc
 
(March 15th 2010)
- (DONE) Bug fix for wrong interrupt sequences in IRQ and NMI. Tested by
simulation with RTI and in a real environment by customer.

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