Subversion Repositories cpu6502_true_cycle

/trunk/TO_DO_list.txt

/trunk/asm/readme.txt

/trunk/doc/6502 IP Core Specification_V0_6.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/doc/6502 IP Core Specification_V0_6.pdf

trunk/doc/6502 IP Core Specification_V0_6.pdf Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/HTML.rar =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/HTML.rar =================================================================== --- trunk/doc/HTML.rar (revision 25) +++ trunk/doc/HTML.rar (nonexistent)

trunk/doc/HTML.rar Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/6502 IP Core Specification_V0_7.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/6502 IP Core Specification_V0_7.pdf =================================================================== --- trunk/doc/6502 IP Core Specification_V0_7.pdf (nonexistent) +++ trunk/doc/6502 IP Core Specification_V0_7.pdf (revision 26)

trunk/doc/6502 IP Core Specification_V0_7.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/HTML_r6502_tc.7z =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/HTML_r6502_tc.7z =================================================================== --- trunk/doc/HTML_r6502_tc.7z (nonexistent) +++ trunk/doc/HTML_r6502_tc.7z (revision 26)

trunk/doc/HTML_r6502_tc.7z Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/errata.txt =================================================================== --- trunk/doc/errata.txt (revision 25) +++ trunk/doc/errata.txt (revision 26) @@ -1,5 +1,16 @@ -v1.11 BETA 2013/07/24 +v1.4 2018/09/15 FUNCTIONALITY: + no errata reported/opened + +TIMING: + no errata reported/opened + +SIGNALING: + no errata reported/opened + + +v1.4 BETA 2013/07/24 +FUNCTIONALITY: - ADC and SBC in decimal mode (all op codes - seems to use a formula different from a real R6502.

/trunk/doc/src/6502_opcodes_cycles_testet_V0_9_DRAFT.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/doc/src/6502_opcodes_cycles_testet_V0_9_DRAFT.doc

trunk/doc/src/6502_opcodes_cycles_testet_V0_9_DRAFT.doc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/src/6502 IP Core Specification_V0_6.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/6502 IP Core Specification_V0_6.doc =================================================================== --- trunk/doc/src/6502 IP Core Specification_V0_6.doc (revision 25) +++ trunk/doc/src/6502 IP Core Specification_V0_6.doc (nonexistent)

trunk/doc/src/6502 IP Core Specification_V0_6.doc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/rtl/vhdl/fsm_nmi.vhd =================================================================== --- trunk/rtl/vhdl/fsm_nmi.vhd (revision 25) +++ trunk/rtl/vhdl/fsm_nmi.vhd (nonexistent) @@ -1,167 +0,0 @@ --- VHDL Entity R6502_TC.FSM_NMI.symbol --- --- Created: --- by - eda.UNKNOWN (ENTW1) --- at - 18:40:01 08.02.2010 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -ENTITY FSM_NMI IS - PORT( - clk_clk_i : IN std_logic; - nmi_n_i : IN std_logic; - rst_nmi_i : IN std_logic; - rst_rst_n_i : IN std_logic; - nmi_o : OUT std_logic - ); - --- Declarations - -END FSM_NMI ; - --- Jens-D. Gutschmidt Project: R6502_TC - --- scantara2003@yahoo.de - --- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG - --- - --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - --- the Free Software Foundation, either version 3 of the License, or any later version. - --- - --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - --- - --- You should have received a copy of the GNU General Public License along with this program. If not, see . - --- - --- CVS Revisins History - --- - --- $Log: fsm.sm,v $ - --- <<-- more -->> - --- Title: FSM for NMI - --- Path: R6502_TC/FSM_NMI/fsm - --- Edited: by eda on 08 Feb 2010 - --- --- VHDL Architecture R6502_TC.FSM_NMI.fsm --- --- Created: --- by - eda.UNKNOWN (ENTW1) --- at - 18:40:01 08.02.2010 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -ARCHITECTURE fsm OF FSM_NMI IS - - SUBTYPE STATE_TYPE IS - std_logic_vector(1 DOWNTO 0); - - -- Hard encoding - CONSTANT idle : STATE_TYPE := "00"; - CONSTANT idle1 : STATE_TYPE := "01"; - CONSTANT idle2 : STATE_TYPE := "11"; - CONSTANT IMP : STATE_TYPE := "10"; - - -- Declare current and next state signals - SIGNAL current_state : STATE_TYPE; - SIGNAL next_state : STATE_TYPE; - - -- Declare any pre-registered internal signals - SIGNAL nmi_o_cld : std_logic ; - -BEGIN - - ----------------------------------------------------------------- - clocked_proc : PROCESS ( - clk_clk_i, - rst_rst_n_i - ) - ----------------------------------------------------------------- - BEGIN - IF (rst_rst_n_i = '0') THEN - current_state <= idle; - -- Default Reset Values - nmi_o_cld <= '0'; - ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN - current_state <= next_state; - -- Default Assignment To Internals - nmi_o_cld <= '0'; - - -- Combined Actions - CASE current_state IS - WHEN IMP => - nmi_o_cld <= '1'; - IF (rst_nmi_i = '1') THEN - nmi_o_cld <= '0'; - END IF; - WHEN OTHERS => - NULL; - END CASE; - END IF; - END PROCESS clocked_proc; - - ----------------------------------------------------------------- - nextstate_proc : PROCESS ( - current_state, - nmi_n_i, - rst_nmi_i - ) - ----------------------------------------------------------------- - BEGIN - CASE current_state IS - WHEN idle => - IF (nmi_n_i = '1') THEN - next_state <= idle1; - ELSE - next_state <= idle; - END IF; - WHEN idle1 => - IF (nmi_n_i = '0') THEN - next_state <= idle2; - ELSE - next_state <= idle1; - END IF; - WHEN idle2 => - IF (nmi_n_i = '0') THEN - next_state <= IMP; - ELSE - next_state <= idle; - END IF; - WHEN IMP => - IF (rst_nmi_i = '1') THEN - next_state <= idle; - ELSE - next_state <= IMP; - END IF; - WHEN OTHERS => - next_state <= idle; - END CASE; - END PROCESS nextstate_proc; - - -- Concurrent Statements - -- Clocked output assignments - nmi_o <= nmi_o_cld; -END fsm;

trunk/rtl/vhdl/fsm_nmi.vhd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/rtl/vhdl/core.vhd =================================================================== --- trunk/rtl/vhdl/core.vhd (revision 25) +++ trunk/rtl/vhdl/core.vhd (revision 26) @@ -1,291 +1,311 @@ --- VHDL Entity R6502_TC.Core.symbol +-- VHDL Entity r6502_tc.core.symbol -- -- Created: --- by - eda.UNKNOWN (ENTW1) --- at - 14:13:52 08.03.2010 +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 09:42:07 11.09.2018 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -ENTITY Core IS - PORT( - clk_clk_i : IN std_logic; - d_i : IN std_logic_vector (7 DOWNTO 0); - irq_n_i : IN std_logic; - nmi_n_i : IN std_logic; - rdy_i : IN std_logic; - rst_rst_n_i : IN std_logic; - so_n_i : IN std_logic; - a_o : OUT std_logic_vector (15 DOWNTO 0); - d_o : OUT std_logic_vector (7 DOWNTO 0); - rd_o : OUT std_logic; - sync_o : OUT std_logic; - wr_n_o : OUT std_logic; - wr_o : OUT std_logic +entity core is + port( + clk_clk_i : in std_logic; + d_i : in std_logic_vector (7 downto 0); + irq_n_i : in std_logic; + nmi_n_i : in std_logic; + rdy_i : in std_logic; + rst_rst_n_i : in std_logic; + so_n_i : in std_logic; + a_o : out std_logic_vector (15 downto 0); + d_o : out std_logic_vector (7 downto 0); + rd_o : out std_logic; + sync_o : out std_logic; + wr_n_o : out std_logic; + wr_o : out std_logic ); -- Declarations -END Core ; +end core ; --- Jens-D. Gutschmidt Project: R6502_TC --- scantara2003@yahoo.de --- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version --- 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A --- PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- CVS Revisins History --- --- $Log: struct.bd,v $ --- <<-- more -->> --- Title: Core --- Path: R6502_TC/Core/struct --- Edited: by eda on 08 Feb 2010 +-- (C) 2008 - 2018 Jens Gutschmidt +-- (email: opencores@vivare-services.com) +-- +-- Versions: +-- Revision 1.20 2013/07/24 11:11:00 jens +-- - Changing the title block and internal revision history +-- +-- Revision 1.6 2009/01/04 10:20:47 eda +-- Changes for cosmetic issues only +-- +-- Revision 1.5 2009/01/04 09:23:10 eda +-- - Delete unused nets and blocks +-- - Rename blocks +-- +-- Revision 1.4 2009/01/03 16:53:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.3 2009/01/03 16:42:02 eda +-- - Unused nets and blocks deleted +-- - Renamed blocks +-- +-- Revision 1.2 2008/12/31 19:31:24 eda +-- Production Release +-- +-- -- --- VHDL Architecture R6502_TC.Core.struct +-- VHDL Architecture r6502_tc.core.struct -- -- Created: --- by - eda.UNKNOWN (ENTW1) --- at - 14:13:53 08.03.2010 +-- by - eda.UNKNOWN (ENTW-7HPZ200) +-- at - 11:46:25 11.09.2018 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) -- +-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -LIBRARY R6502_TC; +library r6502_tc; -ARCHITECTURE struct OF Core IS +architecture struct of core is -- Architecture declarations -- Internal signal declarations - SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0); - SIGNAL adr_o_i : std_logic_vector(15 DOWNTO 0); - SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0); - SIGNAL adr_sp_o_i : std_logic_vector(15 DOWNTO 0); - SIGNAL ch_a_o_i : std_logic_vector(7 DOWNTO 0); - SIGNAL ch_b_o_i : std_logic_vector(7 DOWNTO 0); - SIGNAL d_alu_n_o_i : std_logic; - SIGNAL d_alu_o_i : std_logic_vector(7 DOWNTO 0); - SIGNAL d_alu_or_o_i : std_logic; - SIGNAL d_regs_in_o_i : std_logic_vector(7 DOWNTO 0); - SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0); - SIGNAL ld_o_i : std_logic_vector(1 DOWNTO 0); - SIGNAL ld_pc_o_i : std_logic; - SIGNAL ld_sp_o_i : std_logic; - SIGNAL load_regs_o_i : std_logic; - SIGNAL nmi_o_i : std_logic; - SIGNAL offset_o_i : std_logic_vector(15 DOWNTO 0); - SIGNAL q_a_o_i : std_logic_vector(7 DOWNTO 0); - SIGNAL q_x_o_i : std_logic_vector(7 DOWNTO 0); - SIGNAL q_y_o_i : std_logic_vector(7 DOWNTO 0); - SIGNAL reg_0flag_o_i : std_logic; - SIGNAL reg_1flag_o_i : std_logic; - SIGNAL reg_7flag_o_i : std_logic; - SIGNAL rst_nmi_o_i : std_logic; - SIGNAL sel_pc_in_o_i : std_logic; - SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0); - SIGNAL sel_rb_in_o_i : std_logic_vector(1 DOWNTO 0); - SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0); - SIGNAL sel_reg_o_i : std_logic_vector(1 DOWNTO 0); - SIGNAL sel_sp_as_o_i : std_logic; - SIGNAL sel_sp_in_o_i : std_logic; + signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0); + signal adr_o_i : std_logic_vector(15 downto 0); + signal adr_pc_o_i : std_logic_vector(15 downto 0); + signal adr_sp_o_i : std_logic_vector(15 downto 0); + signal ch_a_o_i : std_logic_vector(7 downto 0); + signal ch_b_o_i : std_logic_vector(7 downto 0); + signal d_alu_n_o_i : std_logic; + signal d_alu_o_i : std_logic_vector(7 downto 0); + signal d_alu_or_o_i : std_logic; + signal d_regs_in_o_i : std_logic_vector(7 downto 0); + signal d_regs_out_o_i : std_logic_vector(7 downto 0); + signal ld_o_i : std_logic_vector(1 downto 0); + signal ld_pc_o_i : std_logic; + signal ld_sp_o_i : std_logic; + signal load_regs_o_i : std_logic; + signal nmi_o_i : std_logic; + signal offset_o_i : std_logic_vector(15 downto 0); + signal q_a_o_i : std_logic_vector(7 downto 0); + signal q_x_o_i : std_logic_vector(7 downto 0); + signal q_y_o_i : std_logic_vector(7 downto 0); + signal reg_0flag_o_i : std_logic; + signal reg_1flag_o_i : std_logic; + signal reg_7flag_o_i : std_logic; + signal rst_nmi_o_i : std_logic; + signal sel_pc_in_o_i : std_logic; + signal sel_pc_val_o_i : std_logic_vector(1 downto 0); + signal sel_rb_in_o_i : std_logic_vector(1 downto 0); + signal sel_rb_out_o_i : std_logic_vector(1 downto 0); + signal sel_reg_o_i : std_logic_vector(1 downto 0); + signal sel_sp_as_o_i : std_logic; + signal sel_sp_in_o_i : std_logic; -- Component Declarations - COMPONENT FSM_Execution_Unit - PORT ( - adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0); - adr_pc_i : IN std_logic_vector (15 DOWNTO 0); - adr_sp_i : IN std_logic_vector (15 DOWNTO 0); - clk_clk_i : IN std_logic ; - d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 ); - d_i : IN std_logic_vector ( 7 DOWNTO 0 ); - d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 ); - irq_n_i : IN std_logic ; - nmi_i : IN std_logic ; - q_a_i : IN std_logic_vector ( 7 DOWNTO 0 ); - q_x_i : IN std_logic_vector ( 7 DOWNTO 0 ); - q_y_i : IN std_logic_vector ( 7 DOWNTO 0 ); - rdy_i : IN std_logic ; - reg_0flag_i : IN std_logic ; - reg_1flag_i : IN std_logic ; - reg_7flag_i : IN std_logic ; - rst_rst_n_i : IN std_logic ; - so_n_i : IN std_logic ; - a_o : OUT std_logic_vector (15 DOWNTO 0); - adr_o : OUT std_logic_vector (15 DOWNTO 0); - ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 ); - ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 ); - d_o : OUT std_logic_vector ( 7 DOWNTO 0 ); - d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 ); - ld_o : OUT std_logic_vector ( 1 DOWNTO 0 ); - ld_pc_o : OUT std_logic ; - ld_sp_o : OUT std_logic ; - load_regs_o : OUT std_logic ; - offset_o : OUT std_logic_vector ( 15 DOWNTO 0 ); - rd_o : OUT std_logic ; - rst_nmi_o : OUT std_logic ; - sel_pc_in_o : OUT std_logic ; - sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 ); - sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 ); - sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 ); - sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 ); - sel_sp_as_o : OUT std_logic ; - sel_sp_in_o : OUT std_logic ; - sync_o : OUT std_logic ; - wr_n_o : OUT std_logic ; - wr_o : OUT std_logic + component fsm_execution_unit + port ( + adr_nxt_pc_i : in std_logic_vector (15 downto 0); + adr_pc_i : in std_logic_vector (15 downto 0); + adr_sp_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic ; + d_alu_i : in std_logic_vector ( 7 downto 0 ); + d_i : in std_logic_vector ( 7 downto 0 ); + d_regs_out_i : in std_logic_vector ( 7 downto 0 ); + irq_n_i : in std_logic ; + nmi_i : in std_logic ; + q_a_i : in std_logic_vector ( 7 downto 0 ); + q_x_i : in std_logic_vector ( 7 downto 0 ); + q_y_i : in std_logic_vector ( 7 downto 0 ); + rdy_i : in std_logic ; + reg_0flag_i : in std_logic ; + reg_1flag_i : in std_logic ; + reg_7flag_i : in std_logic ; + rst_rst_n_i : in std_logic ; + so_n_i : in std_logic ; + a_o : out std_logic_vector (15 downto 0); + adr_o : out std_logic_vector (15 downto 0); + ch_a_o : out std_logic_vector ( 7 downto 0 ); + ch_b_o : out std_logic_vector ( 7 downto 0 ); + d_o : out std_logic_vector ( 7 downto 0 ); + d_regs_in_o : out std_logic_vector ( 7 downto 0 ); + int_fetch_o : out std_logic ; + int_reg_2flag_o : out std_logic ; + ld_o : out std_logic_vector ( 1 downto 0 ); + ld_pc_o : out std_logic ; + ld_sp_o : out std_logic ; + load_regs_o : out std_logic ; + offset_o : out std_logic_vector ( 15 downto 0 ); + rd_o : out std_logic ; + rst_nmi_o : out std_logic ; + sel_pc_in_o : out std_logic ; + sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); + sel_reg_o : out std_logic_vector ( 1 downto 0 ); + sel_sp_as_o : out std_logic ; + sel_sp_in_o : out std_logic ; + sync_o : out std_logic ; + wr_n_o : out std_logic ; + wr_o : out std_logic ); - END COMPONENT; - COMPONENT FSM_NMI - PORT ( - clk_clk_i : IN std_logic ; - nmi_n_i : IN std_logic ; - rst_nmi_i : IN std_logic ; - rst_rst_n_i : IN std_logic ; - nmi_o : OUT std_logic + end component; + component fsm_intnmi + port ( + clk_clk_i : in std_logic ; + nmi_n_i : in std_logic ; + rst_nmi_i : in std_logic ; + rst_rst_n_i : in std_logic ; + nmi_o : out std_logic ); - END COMPONENT; - COMPONENT RegBank_AXY - PORT ( - clk_clk_i : IN std_logic ; - d_regs_in_i : IN std_logic_vector (7 DOWNTO 0); - load_regs_i : IN std_logic ; - rst_rst_n_i : IN std_logic ; - sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0); - sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0); - sel_reg_i : IN std_logic_vector (1 DOWNTO 0); - d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0); - q_a_o : OUT std_logic_vector (7 DOWNTO 0); - q_x_o : OUT std_logic_vector (7 DOWNTO 0); - q_y_o : OUT std_logic_vector (7 DOWNTO 0) + end component; + component reg_pc + port ( + adr_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic ; + ld_i : in std_logic_vector (1 downto 0); + ld_pc_i : in std_logic ; + offset_i : in std_logic_vector (15 downto 0); + rst_rst_n_i : in std_logic ; + sel_pc_in_i : in std_logic ; + sel_pc_val_i : in std_logic_vector (1 downto 0); + adr_nxt_pc_o : out std_logic_vector (15 downto 0); + adr_pc_o : out std_logic_vector (15 downto 0) ); - END COMPONENT; - COMPONENT Reg_PC - PORT ( - adr_i : IN std_logic_vector (15 DOWNTO 0); - clk_clk_i : IN std_logic ; - ld_i : IN std_logic_vector (1 DOWNTO 0); - ld_pc_i : IN std_logic ; - offset_i : IN std_logic_vector (15 DOWNTO 0); - rst_rst_n_i : IN std_logic ; - sel_pc_in_i : IN std_logic ; - sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0); - adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0); - adr_pc_o : OUT std_logic_vector (15 DOWNTO 0) + end component; + component reg_sp + port ( + adr_low_i : in std_logic_vector (7 downto 0); + clk_clk_i : in std_logic ; + ld_low_i : in std_logic ; + ld_sp_i : in std_logic ; + rst_rst_n_i : in std_logic ; + sel_sp_as_i : in std_logic ; + sel_sp_in_i : in std_logic ; + adr_sp_o : out std_logic_vector (15 downto 0) ); - END COMPONENT; - COMPONENT Reg_SP - PORT ( - adr_low_i : IN std_logic_vector (7 DOWNTO 0); - clk_clk_i : IN std_logic ; - ld_low_i : IN std_logic ; - ld_sp_i : IN std_logic ; - rst_rst_n_i : IN std_logic ; - sel_sp_as_i : IN std_logic ; - sel_sp_in_i : IN std_logic ; - adr_sp_o : OUT std_logic_vector (15 DOWNTO 0) + end component; + component regbank_axy + port ( + clk_clk_i : in std_logic ; + d_regs_in_i : in std_logic_vector (7 downto 0); + load_regs_i : in std_logic ; + rst_rst_n_i : in std_logic ; + sel_rb_in_i : in std_logic_vector (1 downto 0); + sel_rb_out_i : in std_logic_vector (1 downto 0); + sel_reg_i : in std_logic_vector (1 downto 0); + d_regs_out_o : out std_logic_vector (7 downto 0); + q_a_o : out std_logic_vector (7 downto 0); + q_x_o : out std_logic_vector (7 downto 0); + q_y_o : out std_logic_vector (7 downto 0) ); - END COMPONENT; + end component; -- Optional embedded configurations -- pragma synthesis_off - FOR ALL : FSM_Execution_Unit USE ENTITY R6502_TC.FSM_Execution_Unit; - FOR ALL : FSM_NMI USE ENTITY R6502_TC.FSM_NMI; - FOR ALL : RegBank_AXY USE ENTITY R6502_TC.RegBank_AXY; - FOR ALL : Reg_PC USE ENTITY R6502_TC.Reg_PC; - FOR ALL : Reg_SP USE ENTITY R6502_TC.Reg_SP; + for all : fsm_execution_unit use entity r6502_tc.fsm_execution_unit; + for all : fsm_intnmi use entity r6502_tc.fsm_intnmi; + for all : reg_pc use entity r6502_tc.reg_pc; + for all : reg_sp use entity r6502_tc.reg_sp; + for all : regbank_axy use entity r6502_tc.regbank_axy; -- pragma synthesis_on -BEGIN +begin - -- ModuleWare code(v1.9) for instance 'U_11' of 'add' - u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i) - VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0); - VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0); - VARIABLE temp_sum : unsigned(8 DOWNTO 0); - VARIABLE temp_carry : std_logic; - BEGIN + -- ModuleWare code(v1.12) for instance 'U_11' of 'add' + u_11combo_proc: process (ch_a_o_i, ch_b_o_i) + variable temp_din0 : std_logic_vector(8 downto 0); + variable temp_din1 : std_logic_vector(8 downto 0); + variable temp_sum : unsigned(8 downto 0); + variable temp_carry : std_logic; + begin temp_din0 := '0' & ch_a_o_i; temp_din1 := '0' & ch_b_o_i; temp_carry := '0'; temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; - d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8); + d_alu_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8); reg_0flag_o_i <= temp_sum(8) ; - END PROCESS u_11combo_proc; + end process u_11combo_proc; - -- ModuleWare code(v1.9) for instance 'U_8' of 'inv' - reg_1flag_o_i <= NOT(d_alu_or_o_i); + -- ModuleWare code(v1.12) for instance 'U_8' of 'inv' + reg_1flag_o_i <= not(d_alu_or_o_i); - -- ModuleWare code(v1.9) for instance 'U_9' of 'inv' - reg_7flag_o_i <= NOT(d_alu_n_o_i); + -- ModuleWare code(v1.12) for instance 'U_9' of 'inv' + reg_7flag_o_i <= not(d_alu_n_o_i); - -- ModuleWare code(v1.9) for instance 'U_10' of 'inv' - d_alu_n_o_i <= NOT(d_alu_o_i(7)); + -- ModuleWare code(v1.12) for instance 'U_10' of 'inv' + d_alu_n_o_i <= not(d_alu_o_i(7)); - -- ModuleWare code(v1.9) for instance 'U_7' of 'por' - d_alu_or_o_i <= d_alu_o_i(0) OR d_alu_o_i(1) OR d_alu_o_i(2) OR d_alu_o_i(3) OR d_alu_o_i(4) OR d_alu_o_i(5) OR d_alu_o_i(6) OR d_alu_o_i(7); + -- ModuleWare code(v1.12) for instance 'U_7' of 'por' + d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7); -- Instance port mappings. - U_4 : FSM_Execution_Unit - PORT MAP ( - adr_nxt_pc_i => adr_nxt_pc_o_i, - adr_pc_i => adr_pc_o_i, - adr_sp_i => adr_sp_o_i, - clk_clk_i => clk_clk_i, - d_alu_i => d_alu_o_i, - d_i => d_i, - d_regs_out_i => d_regs_out_o_i, - irq_n_i => irq_n_i, - nmi_i => nmi_o_i, - q_a_i => q_a_o_i, - q_x_i => q_x_o_i, - q_y_i => q_y_o_i, - rdy_i => rdy_i, - reg_0flag_i => reg_0flag_o_i, - reg_1flag_i => reg_1flag_o_i, - reg_7flag_i => reg_7flag_o_i, - rst_rst_n_i => rst_rst_n_i, - so_n_i => so_n_i, - a_o => a_o, - adr_o => adr_o_i, - ch_a_o => ch_a_o_i, - ch_b_o => ch_b_o_i, - d_o => d_o, - d_regs_in_o => d_regs_in_o_i, - ld_o => ld_o_i, - ld_pc_o => ld_pc_o_i, - ld_sp_o => ld_sp_o_i, - load_regs_o => load_regs_o_i, - offset_o => offset_o_i, - rd_o => rd_o, - rst_nmi_o => rst_nmi_o_i, - sel_pc_in_o => sel_pc_in_o_i, - sel_pc_val_o => sel_pc_val_o_i, - sel_rb_in_o => sel_rb_in_o_i, - sel_rb_out_o => sel_rb_out_o_i, - sel_reg_o => sel_reg_o_i, - sel_sp_as_o => sel_sp_as_o_i, - sel_sp_in_o => sel_sp_in_o_i, - sync_o => sync_o, - wr_n_o => wr_n_o, - wr_o => wr_o + U_4 : fsm_execution_unit + port map ( + adr_nxt_pc_i => adr_nxt_pc_o_i, + adr_pc_i => adr_pc_o_i, + adr_sp_i => adr_sp_o_i, + clk_clk_i => clk_clk_i, + d_alu_i => d_alu_o_i, + d_i => d_i, + d_regs_out_i => d_regs_out_o_i, + irq_n_i => irq_n_i, + nmi_i => nmi_o_i, + q_a_i => q_a_o_i, + q_x_i => q_x_o_i, + q_y_i => q_y_o_i, + rdy_i => rdy_i, + reg_0flag_i => reg_0flag_o_i, + reg_1flag_i => reg_1flag_o_i, + reg_7flag_i => reg_7flag_o_i, + rst_rst_n_i => rst_rst_n_i, + so_n_i => so_n_i, + a_o => a_o, + adr_o => adr_o_i, + ch_a_o => ch_a_o_i, + ch_b_o => ch_b_o_i, + d_o => d_o, + d_regs_in_o => d_regs_in_o_i, + int_fetch_o => open, + int_reg_2flag_o => open, + ld_o => ld_o_i, + ld_pc_o => ld_pc_o_i, + ld_sp_o => ld_sp_o_i, + load_regs_o => load_regs_o_i, + offset_o => offset_o_i, + rd_o => rd_o, + rst_nmi_o => rst_nmi_o_i, + sel_pc_in_o => sel_pc_in_o_i, + sel_pc_val_o => sel_pc_val_o_i, + sel_rb_in_o => sel_rb_in_o_i, + sel_rb_out_o => sel_rb_out_o_i, + sel_reg_o => sel_reg_o_i, + sel_sp_as_o => sel_sp_as_o_i, + sel_sp_in_o => sel_sp_in_o_i, + sync_o => sync_o, + wr_n_o => wr_n_o, + wr_o => wr_o ); - U_6 : FSM_NMI - PORT MAP ( + U_6 : fsm_intnmi + port map ( clk_clk_i => clk_clk_i, nmi_n_i => nmi_n_i, rst_nmi_i => rst_nmi_o_i, @@ -292,22 +312,8 @@ rst_rst_n_i => rst_rst_n_i, nmi_o => nmi_o_i ); - U_2 : RegBank_AXY - PORT MAP ( - clk_clk_i => clk_clk_i, - d_regs_in_i => d_regs_in_o_i, - load_regs_i => load_regs_o_i, - rst_rst_n_i => rst_rst_n_i, - sel_rb_in_i => sel_rb_in_o_i, - sel_rb_out_i => sel_rb_out_o_i, - sel_reg_i => sel_reg_o_i, - d_regs_out_o => d_regs_out_o_i, - q_a_o => q_a_o_i, - q_x_o => q_x_o_i, - q_y_o => q_y_o_i - ); - U_0 : Reg_PC - PORT MAP ( + U_0 : reg_pc + port map ( adr_i => adr_o_i, clk_clk_i => clk_clk_i, ld_i => ld_o_i, @@ -319,8 +325,8 @@ adr_nxt_pc_o => adr_nxt_pc_o_i, adr_pc_o => adr_pc_o_i ); - U_1 : Reg_SP - PORT MAP ( + U_1 : reg_sp + port map ( adr_low_i => adr_o_i(7 DOWNTO 0), clk_clk_i => clk_clk_i, ld_low_i => ld_o_i(0), @@ -330,5 +336,19 @@ sel_sp_in_i => sel_sp_in_o_i, adr_sp_o => adr_sp_o_i ); + U_2 : regbank_axy + port map ( + clk_clk_i => clk_clk_i, + d_regs_in_i => d_regs_in_o_i, + load_regs_i => load_regs_o_i, + rst_rst_n_i => rst_rst_n_i, + sel_rb_in_i => sel_rb_in_o_i, + sel_rb_out_i => sel_rb_out_o_i, + sel_reg_i => sel_reg_o_i, + d_regs_out_o => d_regs_out_o_i, + q_a_o => q_a_o_i, + q_x_o => q_x_o_i, + q_y_o => q_y_o_i + ); -END struct; +end struct;

/trunk/rtl/vhdl/fsm_execution_unit.vhd