URL
https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk
Subversion Repositories cpu_lecture
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Rev 2 → Rev 3
/cpu_lecture/trunk/Makefile
0,0 → 1,44
PROJECT=avr_core |
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# the vhdl source files (except testbench) |
# |
FILES += src/*.vhd |
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# the testbench sources and binary. |
# |
SIMFILES = test/test_tb.vhd test/RAMB4_S4_S4.vhd |
SIMTOP = testbench |
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# When to stop the simulation |
# |
# GHDL_SIM_OPT = --assert-level=error |
GHDL_SIM_OPT = --stop-time=40us |
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SIMDIR = simu |
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FLAGS = --ieee=synopsys --warn-no-vital-generic -fexplicit --std=93c |
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all: |
make compile |
make run 2>& 1 | grep -v std_logic_arith |
make view |
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compile: |
@mkdir -p simu |
@echo ----------------------------------------------------------------- |
ghdl -i $(FLAGS) --workdir=simu --work=work $(SIMFILES) $(FILES) |
@echo |
@echo ----------------------------------------------------------------- |
ghdl -m $(FLAGS) --workdir=simu --work=work $(SIMTOP) |
@echo |
@mv $(SIMTOP) simu/$(SIMTOP) |
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run: |
@$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz |
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view: |
gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | gtkwave --vcd gtkwave.save |
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clean: |
ghdl --clean --workdir=simu |
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