URL
https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk
Subversion Repositories cpu_lecture
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- This comparison shows the changes necessary to convert path
/
- from Rev 22 to Rev 23
- ↔ Reverse comparison
Rev 22 → Rev 23
/cpu_lecture/trunk/src/io.vhd
167,17 → 167,29
if (I_CLR = '1') then |
L_INTVEC <= "000000"; |
else |
if (L_RX_INT_ENABLED and U_RX_READY) = '1' then |
if (L_INTVEC(5) = '0') then -- no interrupt pending |
L_INTVEC <= "101011"; -- _VECTOR(11) |
end if; |
elsif (L_TX_INT_ENABLED and not U_TX_BUSY) = '1' then |
if (L_INTVEC(5) = '0') then -- no interrupt pending |
L_INTVEC <= "101100"; -- _VECTOR(12) |
end if; |
else -- no interrupt |
L_INTVEC <= "000000"; |
end if; |
case L_INTVEC is |
when "101011" => -- vector 11 interrupt pending. |
if (L_RX_INT_ENABLED and U_RX_READY) = '0' then |
L_INTVEC <= "000000"; |
end if; |
|
when "101100" => -- vector 12 interrupt pending. |
if (L_TX_INT_ENABLED and not U_TX_BUSY) = '0' then |
L_INTVEC <= "000000"; |
end if; |
|
when others => |
-- no interrupt is pending. |
-- We accept a new interrupt. |
-- |
if (L_RX_INT_ENABLED and U_RX_READY) = '1' then |
L_INTVEC <= "101011"; -- _VECTOR(11) |
elsif (L_TX_INT_ENABLED and not U_TX_BUSY) = '1' then |
L_INTVEC <= "101100"; -- _VECTOR(12) |
else |
L_INTVEC <= "000000"; -- no interrupt |
end if; |
end case; |
end if; |
end if; |
end process; |
/cpu_lecture/trunk/src/opc_deco.vhd
460,6 → 460,7
Q_IMM(6) <= '1'; |
Q_AMOD <= AMOD_iiSP; |
Q_RD_M <= I_T0; |
Q_WE_F <= not I_T0; -- I flag |
Q_WE_XYZS <= not I_T0; |
if (I_T0 = '0') then |
Q_PC_OP <= PC_LD_S; |