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URL https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk

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    /cpu_lecture/trunk
    from Rev 8 to Rev 9
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Rev 8 → Rev 9

/html/09_Toolchain_Setup.html
82,7 → 82,7
 
<P><br>
 
<P><img src="GTKWave.png">
<P><img src="GTKWave.PNG">
 
<P><br>
 
93,21 → 93,6
 
<pre class="vhdl">
 
156 00000095: (uart_puts):
157 95: 01AC movw r20, r24
158 96: C003 rjmp 0x9A ; 0x134 <uart_puts+0xa>
159 97: 9B5D sbis 0x0b, 5 ; 11
160 98: CFFE rjmp 0x97 ; 0x12e <uart_puts+0x4>
161 99: B92C out 0x0c, r18 ; 12
162 9A: 01FC movw r30, r24
163 9B: 9601 adiw r24, 0x01 ; 1
164 9C: 9124 lpm r18, Z
165 9D: 2322 and r18, r18
166 9E: F7C1 brne 0x97 ; 0x12e <uart_puts+0x4>
167 9F: 1B84 sub r24, r20
168 A0: 0B95 sbc r25, r21
169 A1: 9701 sbiw r24, 0x01 ; 1
170 A2: 9508 ret
<pre class="filename">
app/hello.lss1
</pre></pre>
157,141 → 142,202
3 #include "stdint.h"
4 #include "string.h"
5
6 const char * hex_file = 0;
7 const char * vhdl_file = 0;
6 uint8_t buffer[0x10000]; // 64 k is max. for Intel hex.
7 uint8_t slice [0x10000]; // 16 k is max. for Xilinx bram
8
9 uint8_t buffer[0x10000];
10
11 //-----------------------------------------------------------------------------
12 uint32_t
13 get_byte(const char * cp)
14 {
15 uint32_t value;
16 const char cc[3] = { cp[0], cp[1], 0 };
17 const int cnt = sscanf(cc, "%X", &value);
18 assert(cnt == 1);
19 return value;
20 }
21 //-----------------------------------------------------------------------------
22 void
23 read_file(FILE * in)
24 {
25 memset(buffer, 0xFF, sizeof(buffer));
26 char line[200];
27 for (;;)
28 {
29 const char * s = fgets(line, sizeof(line) - 2, in);
30 if (s == 0) return;
31 assert(*s++ == ':');
32 const uint32_t len = get_byte(s);
33 const uint32_t ah = get_byte(s + 2);
34 const uint32_t al = get_byte(s + 4);
35 const uint32_t rectype = get_byte(s + 6);
36 const char * d = s + 8;
37 const uint32_t addr = ah << 8 | al;
38
39 uint32_t csum = len + ah + al + rectype;
40 assert((addr + len) <= 0x10000);
41 for (uint32_t l = 0; l < len; ++l)
42 {
43 const uint32_t byte = get_byte(d);
44 d += 2;
45 buffer[addr + l] = byte;
46 csum += byte;
47 }
48
49 csum = 0xFF & -csum;
50 const uint32_t sum = get_byte(d);
51 assert(sum == csum);
52 }
53 }
54 //-----------------------------------------------------------------------------
55 void
56 write_vector(FILE * out, bool odd, uint32_t mem, uint32_t v)
57 {
58 const uint8_t * base = buffer;
59
60 // total memory is 2 even bytes, 2 odd bytes, 2 even bytes, ...
61 //
62 if (odd) base += 2;
63
64 // total memory is 4 kByte organized into 8 memories.
65 // thus each of the 16 vectors covers 256 bytes.
66 //
67 base += v*256;
68
69 // memories 0 and 1 are the low byte of the opcode while
70 // memories 2 and 3 are the high byte.
71 //
72 if (mem >= 2) ++base;
73
74 const char * px = odd ? "po" : "pe";
75 fprintf(out, "constant %s_%u_%2.2X : BIT_VECTOR := X\"", px, mem, v);
76 for (int32_t d = 63; d >= 0; --d)
77 {
78 uint32_t q = base[4*d];
79 if (mem & 1) q >>= 4; // high nibble
80 else q &= 0x0F; // low nibble
81 fprintf(out, "%X", q);
82 }
83
84 fprintf(out, "\";\r\n");
85 }
86 //-----------------------------------------------------------------------------
87 void
88 write_mem(FILE * out, bool odd, uint32_t mem)
89 {
90 const char * px = odd ? "po" : "pe";
91
92 fprintf(out, "-- content of %s_%u --------------------------------------"
93 "--------------------------------------------\r\n", px, mem);
94
95 for (uint32_t v = 0; v < 16; ++v)
96 write_vector(out, odd, mem, v);
97
98 fprintf(out, "\r\n");
99 }
100 //-----------------------------------------------------------------------------
101 void
102 write_file(FILE * out)
103 {
104 fprintf(out,
105 "\r\n"
106 "library IEEE;\r\n"
107 "use IEEE.STD_LOGIC_1164.all;\r\n"
108 "\r\n"
109 "package prog_mem_content is\r\n"
110 "\r\n");
111
112 for (uint32_t m = 0; m < 4; ++m)
113 write_mem(out, false, m);
114
115 for (uint32_t m = 0; m < 4; ++m)
116 write_mem(out, true, m);
117
118 fprintf(out,
119 "end prog_mem_content;\r\n"
120 "\r\n");
121 }
122 //-----------------------------------------------------------------------------
123 int
124 main(int argc, char * argv[])
125 {
126 if (argc > 1) hex_file = argv[1];
127 if (argc > 2) vhdl_file = argv[2];
128
129 FILE * in = stdin;
130 if (hex_file) in = fopen(hex_file, "r");
131 assert(in);
132 read_file(in);
133 fclose(in);
134
135 FILE * out = stdout;
136 if (vhdl_file) out = fopen(vhdl_file, "w");
137 write_file(out);
138 assert(out);
139 }
140 //-----------------------------------------------------------------------------
9 //-----------------------------------------------------------------------------
10 //
11 // get a byte (from cp pointing into Intel hex file).
12 //
13 uint32_t
14 get_byte(const char * cp)
15 {
16 uint32_t value;
17 const char cc[3] = { cp[0], cp[1], 0 };
18 const int cnt = sscanf(cc, "%X", &value);
19 assert(cnt == 1);
20 return value;
21 }
22 //-----------------------------------------------------------------------------
23 //
24 // read an Intel hex file into buffer
25 void
26 read_file(FILE * in)
27 {
28 memset(buffer, 0xFF, sizeof(buffer));
29 char line[200];
30 for (;;)
31 {
32 const char * s = fgets(line, sizeof(line) - 2, in);
33 if (s == 0) return;
34 assert(*s++ == ':');
35 const uint32_t len = get_byte(s);
36 const uint32_t ah = get_byte(s + 2);
37 const uint32_t al = get_byte(s + 4);
38 const uint32_t rectype = get_byte(s + 6);
39 const char * d = s + 8;
40 const uint32_t addr = ah << 8 | al;
41
42 uint32_t csum = len + ah + al + rectype;
43 assert((addr + len) <= 0x10000);
44 for (uint32_t l = 0; l < len; ++l)
45 {
46 const uint32_t byte = get_byte(d);
47 d += 2;
48 buffer[addr + l] = byte;
49 csum += byte;
50 }
51
52 csum = 0xFF & -csum;
53 const uint32_t sum = get_byte(d);
54 assert(sum == csum);
55 }
56 }
57 //-----------------------------------------------------------------------------
58 //
59 // copy a slice from buffer into slice.
60 // buffer is organized as 32-bit x items.
61 // slice is organized as bits x items.
62 //
63 void copy_slice(uint32_t slice_num, uint32_t port_bits, uint32_t mem_bits)
64 {
65 assert(mem_bits == 0x1000 || mem_bits == 0x4000);
66
67 const uint32_t items = mem_bits/port_bits;
68 const uint32_t mask = (1 << port_bits) - 1;
69 const uint8_t * src = buffer;
70
71 memset(slice, 0, sizeof(slice));
72
73 for (uint32_t i = 0; i < items; ++i)
74 {
75 // read one 32-bit value;
76 const uint32_t v0 = *src++;
77 const uint32_t v1 = *src++;
78 const uint32_t v2 = *src++;
79 const uint32_t v3 = *src++;
80 const uint32_t v = (v3 << 24 |
81 v2 << 16 |
82 v1 << 8 |
83 v0 ) >> (slice_num*port_bits) & mask;
84
85 if (port_bits == 16)
86 {
87 assert(v < 0x10000);
88 slice[2*i] = v;
89 slice[2*i + 1] = v >> 8;
90 }
91 else if (port_bits == 8)
92 {
93 assert(v < 0x100);
94 slice[i] = v;
95 }
96 else if (port_bits == 4)
97 {
98 assert(v < 0x10);
99 slice[i >> 1] |= v << (4*(i & 1));
100 }
101 else if (port_bits == 2)
102 {
103 assert(v < 0x04);
104 slice[i >> 2] |= v << (2*(i & 3));
105 }
106 else if (port_bits == 1)
107 {
108 assert(v < 0x02);
109 slice[i >> 3] |= v << ((i & 7));
110 }
111 else assert(0 && "Bad aspect ratio.");
112 }
113 }
114 //-----------------------------------------------------------------------------
115 //
116 // write one initialization vector
117 //
118 void
119 write_vector(FILE * out, uint32_t mem, uint32_t vec, const uint8_t * data)
120 {
121 fprintf(out, "constant p%u_%2.2X : BIT_VECTOR := X\"", mem, vec);
122 for (int32_t d = 31; d >= 0; --d)
123 fprintf(out, "%2.2X", data[d]);
124
125 fprintf(out, "\";\r\n");
126 }
127 //-----------------------------------------------------------------------------
128 //
129 // write one memory
130 //
131 void
132 write_mem(FILE * out, uint32_t mem, uint32_t bytes)
133 {
134 fprintf(out, "-- content of p_%u --------------------------------------"
135 "--------------------------------------------\r\n", mem);
136
137 const uint8_t * src = slice;
138 for (uint32_t v = 0; v < bytes/32; ++v)
139 write_vector(out, mem, v, src + 32*v);
140
141 fprintf(out, "\r\n");
142 }
143 //-----------------------------------------------------------------------------
144 //
145 // write the entire memory_contents file.
146 //
147 void
148 write_file(FILE * out, uint32_t bits)
149 {
150 fprintf(out,
151 "\r\n"
152 "library IEEE;\r\n"
153 "use IEEE.STD_LOGIC_1164.all;\r\n"
154 "\r\n"
155 "package prog_mem_content is\r\n"
156 "\r\n");
157
158 const uint32_t mems = 16/bits;
159
160 for (uint32_t m = 0; m < 2*mems; ++m)
161 {
162 copy_slice(m, bits, 0x1000);
163 write_mem(out, m, 0x200);
164 }
165
166 fprintf(out,
167 "end prog_mem_content;\r\n"
168 "\r\n");
169 }
170 //-----------------------------------------------------------------------------
171 int
172 main(int argc, char * argv[])
173 {
174 uint32_t bits = 4;
175 const char * prog = *argv++; --argc;
176
177 if (argc && !strcmp(*argv, "-1")) { bits = 1; ++argv; --argc; }
178 else if (argc && !strcmp(*argv, "-2")) { bits = 2; ++argv; --argc; }
179 else if (argc && !strcmp(*argv, "-4")) { bits = 4; ++argv; --argc; }
180 else if (argc && !strcmp(*argv, "-8")) { bits = 8; ++argv; --argc; }
181 else if (argc && !strcmp(*argv, "-16")) { bits = 16; ++argv; --argc; }
182
183 const char * hex_file = 0;
184 const char * vhdl_file = 0;
185
186 if (argc) { hex_file = *argv++; --argc; }
187 if (argc) { vhdl_file = *argv++; --argc; }
188 assert(argc == 0);
189
190 FILE * in = stdin;
191 if (hex_file) in = fopen(hex_file, "r");
192 assert(in);
193 read_file(in);
194 fclose(in);
195
196 FILE * out = stdout;
197 if (vhdl_file) out = fopen(vhdl_file, "w");
198 write_file(out, bits);
199 assert(out);
200 }
201 //-----------------------------------------------------------------------------
<pre class="filename">
tools/make_mem.cc
</pre></pre>
572,14 → 618,14
 
# Compile and link hello.c.
avr-gcc -Wall -Os -fpack-struct -fshort-enums -funsigned-char -funsigned-bitfields -mmcu=atmega8 \
-DF_CPU=33333333UL -MMD -MP -MF"main.d" -MT"main.d" -c -o"main.o" "main.c"
avr-gcc -Wl,-Map,AVR_FPGA.map -mmcu=atmega8 -o"AVR_FPGA.elf" ./main.o
-DF_CPU=25000000UL -c -o"hello.o" "hello.c"
avr-gcc -Wl,-Map,hello.map -mmcu=atmega8 -o"hello.elf" ./hello.o
 
# Create an opcode listing.
avr-objdump -h -S AVR_FPGA.elf >"AVR_FPGA.lss"
avr-objdump -h -S hello.elf >"hello.lss"
 
# Create intel hex file.
avr-objcopy -R .eeprom -O ihex AVR_FPGA.elf "AVR_FPGA.hex"
avr-objcopy -R .eeprom -O ihex hello.elf "hello.hex"
 
</pre>
<P>
903,42 → 949,44
6
7 # the testbench sources and binary.
8 #
9 SIMFILES = test/test_tb.vhd test/RAMB4_S4_S4.vhd
10 SIMTOP = testbench
11
12 # When to stop the simulation
13 #
14 # GHDL_SIM_OPT = --assert-level=error
15 GHDL_SIM_OPT = --stop-time=40us
16
17 SIMDIR = simu
9 SIMFILES = test/test_tb.vhd
10 SIMFILES += test/RAMB4_S4_S4.vhd
11 SIMFILES += test/RAM32X1S.vhd
12 SIMTOP = testbench
13
14 # When to stop the simulation
15 #
16 # GHDL_SIM_OPT = --assert-level=error
17 GHDL_SIM_OPT = --stop-time=40us
18
19 FLAGS = --ieee=synopsys --warn-no-vital-generic -fexplicit --std=93c
19 SIMDIR = simu
20
21 all:
22 make compile
23 make run 2>& 1 | grep -v std_logic_arith
24 make view
25
26 compile:
27 @mkdir -p simu
28 @echo -----------------------------------------------------------------
29 ghdl -i $(FLAGS) --workdir=simu --work=work $(SIMFILES) $(FILES)
30 @echo
31 @echo -----------------------------------------------------------------
32 ghdl -m $(FLAGS) --workdir=simu --work=work $(SIMTOP)
33 @echo
34 @mv $(SIMTOP) simu/$(SIMTOP)
35
36 run:
37 @$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
38
39 view:
40 gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | gtkwave --vcd gtkwave.save
41
42 clean:
43 ghdl --clean --workdir=simu
44
21 FLAGS = --ieee=synopsys --warn-no-vital-generic -fexplicit --std=93c
22
23 all:
24 make compile
25 make run 2>& 1 | grep -v std_logic_arith
26 make view
27
28 compile:
29 @mkdir -p simu
30 @echo -----------------------------------------------------------------
31 ghdl -i $(FLAGS) --workdir=simu --work=work $(SIMFILES) $(FILES)
32 @echo
33 @echo -----------------------------------------------------------------
34 ghdl -m $(FLAGS) --workdir=simu --work=work $(SIMTOP)
35 @echo
36 @mv $(SIMTOP) simu/$(SIMTOP)
37
38 run:
39 @$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
40
41 view:
42 gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | gtkwave --vcd gtkwave.save
43
44 clean:
45 ghdl --clean --workdir=simu
46
<pre class="filename">
Makefile
</pre></pre>
999,7 → 1047,7
<pre class="vhdl">
 
1 NET I_CLK_100 PERIOD = 10 ns;
2 NET L_CLK PERIOD = 35 ns;
2 NET L_CLK PERIOD = 45 ns;
3
4 NET I_CLK_100 TNM_NET = I_CLK_100;
5 NET L_CLK TNM_NET = L_CLK;
1102,7 → 1150,7
 
<pre class="vhdl">
 
2 NET L_CLK PERIOD = 35 ns;
2 NET L_CLK PERIOD = 45 ns;
<pre class="filename">
src/avr_fpga.ucf
</pre></pre>

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