URL
https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk
Subversion Repositories cpu_lecture
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- This comparison shows the changes necessary to convert path
/cpu_lecture
- from Rev 24 to Rev 25
- ↔ Reverse comparison
Rev 24 → Rev 25
/trunk/src/uart.vhd
83,20 → 83,18
I_DATA : in std_logic_vector(7 downto 0); |
I_FLAG : in std_logic; |
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Q_TX : out std_logic; |
Q_FLAG : out std_logic); |
Q_TX_N : out std_logic; |
Q_BUSY : out std_logic); |
end component; |
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signal L_RX_OLD_FLAG : std_logic; |
signal L_RX_READY : std_logic; |
signal L_TX_FLAG : std_logic; |
signal L_TX_FLAGQ : std_logic; |
signal L_TX_DATA : std_logic_vector(7 downto 0); |
signal L_RX_READY : std_logic; |
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begin |
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Q_RX_READY <= L_RX_READY; |
Q_TX_BUSY <= L_TX_FLAG xor L_TX_FLAGQ; |
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baud: baudgen |
generic map(CLOCK_FREQ => CLOCK_FREQ, |
123,13 → 121,15
I_DATA => L_TX_DATA, |
I_FLAG => L_TX_FLAG, |
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Q_TX => Q_TX, |
Q_FLAG => L_TX_FLAGQ); |
Q_TX_N => Q_TX, |
Q_BUSY => Q_TX_BUSY); |
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process(I_CLK) |
begin |
if (rising_edge(I_CLK)) then |
if (I_CLR = '1') then |
L_RX_OLD_FLAG <= R_RX_FLAG; |
L_RX_READY <= '0'; |
L_TX_FLAG <= '0'; |
L_TX_DATA <= X"33"; |
else |
142,11 → 142,10
L_TX_DATA <= I_TX_DATA; |
end if; |
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if (R_RX_FLAG /= L_RX_OLD_FLAG) then |
if (L_RX_OLD_FLAG /= R_RX_FLAG) then |
L_RX_OLD_FLAG <= R_RX_FLAG; |
L_RX_READY <= '1'; |
end if; |
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L_RX_OLD_FLAG <= R_RX_FLAG; |
end if; |
end if; |
end process; |
/trunk/src/uart_tx.vhd
34,17 → 34,17
port( I_CLK : in std_logic; |
I_CLR : in std_logic; -- RESET |
I_CE_1 : in std_logic; -- BAUD rate clock enable |
I_DATA : in std_logic_vector(7 downto 0); -- DATA to be sent |
I_DATA : in std_logic_vector(7 downto 0); -- DATA to send |
I_FLAG : in std_logic; -- toggle to send data |
Q_TX : out std_logic; -- Serial output line |
Q_FLAG : out std_logic); -- Transmitting Flag |
Q_TX_N : out std_logic; -- Serial output, active low |
Q_BUSY : out std_logic); -- Transmitter busy |
end uart_tx; |
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architecture Behavioral of uart_tx is |
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signal L_BUF : std_logic_vector(7 downto 0); |
signal L_BUF : std_logic_vector(8 downto 0); |
signal L_FLAG : std_logic; |
signal L_TODO : std_logic_vector(3 downto 0); -- bits to send |
signal L_FLAG : std_logic; |
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begin |
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51,29 → 51,28
process(I_CLK) |
begin |
if (rising_edge(I_CLK)) then |
if (I_CLR = '1') then |
Q_TX <= '1'; |
L_BUF <= "11111111"; |
if (I_CLR = '1') then -- reset |
Q_TX_N <= '1'; |
L_BUF <= "111111111"; |
L_TODO <= "0000"; |
L_FLAG <= I_FLAG; -- idle |
elsif (I_CE_1 = '1') then |
if (L_TODO /= "0000") then -- transmitting |
Q_TX <= L_BUF(0); -- next bit |
L_BUF <= '1' & L_BUF(7 downto 1); |
if (L_TODO = "0001") then |
L_FLAG <= I_FLAG; |
end if; |
L_FLAG <= I_FLAG; |
elsif (L_TODO = "0000") then -- idle |
if (L_FLAG /= I_FLAG) then -- new byte |
L_BUF <= I_DATA & '0'; -- 8 data / 1 start |
L_TODO <= "1100"; -- 11 bits to send |
L_FLAG <= I_FLAG; |
end if; |
else -- shifting |
if (I_CE_1 = '1') then |
Q_TX_N <= L_BUF(0); |
L_BUF <= '1' & L_BUF(8 downto 1); |
L_TODO <= L_TODO - "0001"; |
elsif (L_FLAG /= I_FLAG) then -- new byte |
Q_TX <= '0'; -- start bit |
L_BUF <= I_DATA; -- data bits |
L_TODO <= "1001"; |
end if; |
end if; |
end if; |
end process; |
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Q_FLAG <= L_FLAG; |
Q_BUSY <= '0' when (L_TODO = "0000") else '1'; |
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end Behavioral; |
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