URL
https://opencores.org/ocsvn/cryptography/cryptography/trunk
Subversion Repositories cryptography
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- This comparison shows the changes necessary to convert path
/cryptography
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/trunk/decryption/decryptor_tb.vhd
0,0 → 1,73
LIBRARY ieee ; |
USE ieee.std_logic_1164.all ; |
USE ieee.std_logic_arith.all ; |
USE ieee.std_logic_unsigned.all ; |
ENTITY decryptor_tb IS |
END ; |
|
ARCHITECTURE decryptor_tb_arch OF decryptor_tb IS |
SIGNAL clock : std_logic :='0' ; |
SIGNAL ciphertext : std_logic_vector (15 downto 0) ; |
SIGNAL ready_d : std_logic ; |
SIGNAL plaintext_d : std_logic_vector (15 downto 0) ; |
SIGNAL start_d : std_logic ; |
SIGNAL round_keys_d : std_logic_vector (15 downto 0) ; |
SIGNAL reset : std_logic ; |
COMPONENT decryptor |
PORT ( |
clock : in std_logic ; |
ciphertext : in std_logic_vector (15 downto 0) ; |
ready_d : out std_logic ; |
plaintext_d : out std_logic_vector (15 downto 0) ; |
start_d : in std_logic ; |
round_keys_d : in std_logic_vector (15 downto 0) ; |
reset : in std_logic ); |
END COMPONENT ; |
BEGIN |
DUT : decryptor |
PORT MAP ( |
clock => clock , |
ciphertext => ciphertext , |
ready_d => ready_d , |
plaintext_d => plaintext_d , |
start_d => start_d , |
round_keys_d => round_keys_d , |
reset => reset ) ; |
|
process |
begin |
reset<='1'; |
wait for 10 ns; |
start_d<='1'; |
reset<='0'; |
|
wait for 3000 ns; |
end process; |
|
|
process(clock) |
begin |
clock<= not clock after 10 ns; |
end process; |
|
process |
begin |
wait for 30 ns; |
ciphertext <="1111101011010000"; |
wait for 20 ns; |
ciphertext <="1100011100001101"; |
wait for 20 ns; |
ciphertext <="0110000001100010"; |
wait for 20 ns; |
ciphertext <="1001000101010111"; |
wait for 3000 ns; |
end process; |
|
process |
begin |
wait for 10 ns; |
round_keys_d <="0000000000000000"; |
wait for 3000 ns; |
end process; |
END ; |
|
/trunk/decryption/decryp.cr.mti
0,0 → 1,10
{G:/final crp project/decryption/decryptor.vhd} {1 {vcom -work work -2002 -explicit {G:/final crp project/decryption/decryptor.vhd} |
Model Technology ModelSim PE vcom 5.8c Compiler 2004.03 Mar 25 2004 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Loading package std_logic_arith |
-- Loading package std_logic_unsigned |
-- Compiling entity decryptor |
-- Compiling architecture arch_decryptor of decryptor |
|
} {} {}} |
/trunk/decryption/full_adder.vhd
0,0 → 1,40
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 11:41:01 10/09/2007 |
-- Design Name: |
-- Module Name: full_adder - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
|
|
entity full_adder is |
|
port ( a,b,c : in std_logic_vector (15 downto 0); |
sf,cf : out std_logic_vector (15 downto 0)); |
end full_adder; |
|
architecture Behavioral of full_adder is |
signal sig:std_logic_vector (15 downto 0); |
begin |
sf <= a xor b xor c; |
sig <= (a and b)or (a and c) or (b and c); |
cf <= (sig(14 downto 0) & '0'); |
end Behavioral; |
|
/trunk/decryption/work/_info
0,0 → 1,32
m255 |
cModel Technology |
dG:\crp project\encryption |
Edecryptor |
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90 |
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2 |
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2 |
w1232774504 |
dG:\final crp project\decryption |
FG:/final crp project/decryption/decryptor.vhd |
l0 |
L7 |
V]oM0ISo7Jo5MJ1^kdW1b?2 |
OE;C;5.8c;15 |
32 |
o-work work -2002 -explicit |
tExplicit T |
Aarch_decryptor |
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90 |
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2 |
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2 |
DE work decryptor ]oM0ISo7Jo5MJ1^kdW1b?2 |
l61 |
L22 |
V8[RafM2W<SBmK>_ffSOVF0 |
OE;C;5.8c;15 |
32 |
M3 ieee std_logic_1164 |
M2 ieee std_logic_arith |
M1 ieee std_logic_unsigned |
o-work work -2002 -explicit |
tExplicit T |
/trunk/decryption/work/decryptor/arch_decryptor.dat
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trunk/decryption/work/decryptor/arch_decryptor.dat
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Index: trunk/decryption/work/decryptor/arch_decryptor.psm
===================================================================
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Index: trunk/decryption/work/decryptor/arch_decryptor.psm
===================================================================
--- trunk/decryption/work/decryptor/arch_decryptor.psm (nonexistent)
+++ trunk/decryption/work/decryptor/arch_decryptor.psm (revision 4)
trunk/decryption/work/decryptor/arch_decryptor.psm
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+application/octet-stream
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Index: trunk/decryption/work/decryptor/_primary.dat
===================================================================
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Index: trunk/decryption/work/decryptor/_primary.dat
===================================================================
--- trunk/decryption/work/decryptor/_primary.dat (nonexistent)
+++ trunk/decryption/work/decryptor/_primary.dat (revision 4)
trunk/decryption/work/decryptor/_primary.dat
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+application/octet-stream
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Index: trunk/decryption/output wave/transcript
===================================================================
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Index: trunk/decryption/output wave/transcript
===================================================================
--- trunk/decryption/output wave/transcript (nonexistent)
+++ trunk/decryption/output wave/transcript (revision 4)
trunk/decryption/output wave/transcript
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+application/octet-stream
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Index: trunk/decryption/output wave/wave2.wlf
===================================================================
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Index: trunk/decryption/output wave/wave2.wlf
===================================================================
--- trunk/decryption/output wave/wave2.wlf (nonexistent)
+++ trunk/decryption/output wave/wave2.wlf (revision 4)
trunk/decryption/output wave/wave2.wlf
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/decryption/output wave/new value.wlf
===================================================================
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Index: trunk/decryption/output wave/new value.wlf
===================================================================
--- trunk/decryption/output wave/new value.wlf (nonexistent)
+++ trunk/decryption/output wave/new value.wlf (revision 4)
trunk/decryption/output wave/new value.wlf
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/decryption/decryptor.vhd.bak
===================================================================
--- trunk/decryption/decryptor.vhd.bak (nonexistent)
+++ trunk/decryption/decryptor.vhd.bak (revision 4)
@@ -0,0 +1,424 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity decryptor is
+
+port (
+ plaintext_d :out std_logic_vector(15 downto 0);-- 16 bit Plaintext output of decryptor
+ ready_d :out std_logic; -- 1 bit ready output of decryptor
+ ciphertext :in std_logic_vector(15 downto 0);-- 16 bit ciphertext input to decrytpor which is output of encryptor
+ round_keys_d:in std_logic_vector(15 downto 0);-- 16 bit roundkeys given to decryptor
+ start_d :in std_logic;
+ reset :in std_logic;
+ clock :in std_logic
+ );
+
+end decryptor;
+
+
+Architecture arch_decryptor of decryptor is
+
+component multiplier
+port( B :in std_logic_vector(15 downto 0);
+ Product :out std_logic_vector(15 downto 0)
+ );
+end component;
+-- constants for the plain text fsm
+
+constant idle:std_logic_vector(3 downto 0):= "0000";
+constant out_A :std_logic_vector(3 downto 0):= "0001";
+constant out_B :std_logic_vector(3 downto 0):= "0010";
+constant out_C :std_logic_vector(3 downto 0):= "0011";
+constant out_D :std_logic_vector(3 downto 0):= "0100";
+
+
+
+
+--ct1, ttemp and utemp are temprary registers to hold the values of t, u and C.
+--signal round_keys_d_saved:std_logic_vector(15 downto 0);
+signal ready_d_pre: std_logic; -- ready_d_pre is used to trigger the plaintext fsm (earlier version of ready_d)
+
+signal state:std_logic_vector(5 downto 0); --state of primary fsm
+signal state_out:std_logic_vector(3 downto 0); -- state of plaintext fsm
+
+signal sig3,sig4:integer range 0 TO 15;
+
+signal last_round ,cleanup : std_logic;
+signal A_final,B_final,C_final,D_final:std_logic_vector(15 downto 0);
+signal utemp1,ttemp1 :std_logic_vector(15 downto 0);-------a_new
+signal A, B, C, D :std_logic_vector(15 downto 0);
+signal product1,product2 : std_logic_vector(15 downto 0);
+---key constant------
+
+ constant p:std_logic_vector(15 downto 0):= "1011011111100001";
+ constant q:std_logic_vector(15 downto 0):= "1001111000110111";
+
+ type s_tp is array(43 downto 0) of std_logic_vector(15 downto 0);
+ signal s :s_tp;
+ type l_tp is array(42 downto 0) of std_logic_vector(15 downto 0);
+ signal l :l_tp;
+
+
+
+begin
+
+a1: multiplier port map (B,product1);
+b1: multiplier port map (D,product2);
+
+
+ sig3<=conv_integer(unsigned(utemp1(3 downto 0)));
+ sig4<=conv_integer(unsigned(ttemp1(3 downto 0)));
+
+
+ ----key algo----
+
+
+ s(0) <= P ; -- initialize constant array
+ l(0)<=(round_keys_d + s(0));
+ s(1)<=(l(0)+ s(0)+ q);
+ l(1)<=( l(0)+s(1));
+ s(2)<=(l(1)+ s(1)+ q);
+ l(2)<=( l(1)+s(2));
+ s(3)<=(l(2)+ s(2)+ q);
+ l(3)<=( l(2)+s(3));
+ s(4)<=(l(3)+ s(3)+ q);
+ l(4)<=( l(3)+s(4));
+ s(5)<=(l(4)+ s(4)+ q);
+ l(5)<=( l(4)+s(5));
+ s(6)<=(l(5)+ s(5)+ q);
+ l(6)<=( l(5)+s(6));
+ s(7)<=(l(6)+ s(6)+ q);
+ l(7)<=( l(6)+s(7));
+ s(8)<=(l(7)+ s(7)+ q);
+ l(8)<=( l(7)+s(8));
+ s(9)<=(l(8)+ s(8)+ q);
+ l(9)<=( l(8)+s(9));
+ s(10)<=(l(9)+ s(9)+ q);
+ l(10)<=( l(9)+s(10 ));
+ s(11)<=(l(10)+ s(10)+ q);
+ l(11)<=( l(10)+s(11));
+ s(12)<=(l(11)+ s(11)+ q);
+ l(12)<=( l(11)+s(12));
+ s(13)<=(l(12)+ s(12)+ q);
+ l(13)<=( l(12)+s(13));
+ s(14)<=(l(13)+ s(13)+ q);
+ l(14)<=( l(13)+s(14));
+ s(15)<=(l(14)+ s(14)+ q);
+ l(15)<=( l(14)+s(15));
+ s(16)<=(l(15)+ s(15)+ q);
+ l(16)<=( l(15)+s(16));
+ s(17)<=(l(16)+ s(16)+ q);
+ l(17)<=( l(16)+s(17));
+ s(18)<=(l(17)+ s(17)+ q);
+ l(18)<=( l(17)+s(18));
+ s(19)<=(l(18)+ s(18)+ q);
+ l(19)<=( l(18)+s(19));
+ s(20)<=(l(19)+ s(19)+ q);
+ l(20)<=( l(19)+s(20));
+ s(21)<=(l(20)+ s(20)+ q);
+ l(21)<=( l(20)+s(21));
+ s(22)<=(l(21)+ s(21)+ q);
+ l(22)<=( l(21)+s(22));
+ s(23)<=(l(22)+ s(22)+ q);
+ l(23)<=( l(22)+s(23));
+ s(24)<=(l(23)+ s(23)+ q);
+ l(24)<=( l(23)+s(24));
+ s(25)<=(l(24)+ s(24)+ q);
+ l(25)<=( l(24)+s(25));
+ s(26)<=(l(25)+ s(25)+ q);
+ l(26)<=( l(25)+s(26));
+ s(27)<=(l(26)+ s(26)+ q);
+ l(27)<=( l(26)+s(27));
+ s(28)<=(l(27)+ s(27)+ q);
+ l(28)<=( l(27)+s(28));
+ s(29)<=(l(28)+ s(28)+ q);
+ l(29)<=( l(23)+s(24));
+ s(30)<=(l(29)+ s(29)+ q);
+ l(30)<=( l(29)+s(30));
+ s(31)<=(l(30)+ s(30)+ q);
+ l(31)<=( l(30)+s(31));
+ s(32)<=(l(31)+ s(31)+ q);
+ l(32)<=( l(31)+s(32));
+ s(33)<=(l(32)+ s(32)+ q);
+ l(33)<=( l(32)+s(33));
+ s(34)<=(l(33)+ s(33)+ q);
+ l(34)<=( l(33)+s(34));
+ s(35)<=(l(34)+ s(34)+ q);
+ l(35)<=( l(34)+s(35));
+ s(36)<=(l(35)+ s(35)+ q);
+ l(36)<=( l(35)+s(36));
+ s(37)<=(l(36)+ s(36)+ q);
+ l(37)<=( l(36)+s(37));
+ s(38)<=(l(37)+ s(37)+ q);
+ l(38)<=( l(37)+s(38));
+ s(39)<=(l(38)+ s(38)+ q);
+ l(39)<=( l(33)+s(34));
+ s(40)<=(l(39)+ s(39)+ q);
+ l(40)<=( l(39)+s(40));
+ s(40)<=(l(39)+ s(39)+ q);
+ l(41)<=( l(40)+s(40));
+ s(41)<=(l(40)+ s(40)+ q);
+ l(42)<=( l(41)+s(41));
+ s(42)<=(l(41)+ s(41)+ q);
+ s(43)<=(l(42)+ s(42)+ q);
+
+
+
+process(clock,reset,ciphertext,sig3,sig4)
+
+
+variable tempA,tempB,tempC,tempD :std_logic_vector(15 downto 0);
+variable temp_AD,temp_BA,temp_CB,temp_DC :std_logic_vector(15 downto 0);
+VARIABLE t,u,t_pre,u_pre:std_logic_vector( 15 downto 0);--temporary VARIABLE used for calculation of A, C, t and u
+VARIABLE A_pre_2,C_pre_2,A_pre ,C_pre :std_logic_vector(15 downto 0);
+
+variable cnt: std_logic_vector(6 downto 0):="0000000";
+
+
+begin
+ if (reset='1') then
+
+ state <= "000001"; -- reset state
+ ready_d <= '0';
+
+ cnt :=(others=>'0');
+
+ A := (others=>'0');
+ B := (others=>'0');
+ C := (others=>'0');
+ D := (others=>'0');
+ ready_d <= '0';
+ TEMPA:=(others=>'0');
+ TEMPB:=(others=>'0');
+ TEMPC:=(others=>'0');
+ TEMPD:=(others=>'0');
+ temp_AD:= (others=>'0');
+ temp_BA:= (others=>'0');
+ temp_CB:= (others=>'0');
+ temp_DC:= (others=>'0');
+
+
+ elsif(clock'event and clock='1') then
+
+ case state is --synopsys parallel_case
+ when"000001"=>
+
+ if (start_d = '0') then
+ state <= "000001";
+ else
+ state <= "000010";
+ ready_d <= '1';
+ end if;
+
+
+ when "000010"=>
+
+ state <= "000011";
+ A := ciphertext;--read ciphertext into A
+ ready_d <= '0';
+
+ when "000011"=>
+
+ state <= "000100";
+ B := ciphertext; -- read ciphertext into B
+ ready_d <= '0';
+
+
+ when "000100"=>
+
+ state <= "000101";
+ C := ciphertext; -- read ciphertext into C
+ ready_d <= '0';
+
+
+ when "000101"=>
+
+ state <= "000110";
+ D := ciphertext;--assign ciphertext to D
+ A := A - s(42); -- Use round keys to calculate new value of A
+ C := C - s(43); -- read ciphertext - roundkeys into C
+ ready_d <= '0';
+
+
+ when "000110"=> -- begin calculation of plaintext loop from r downto 1
+ state <= "001000";
+ TEMPA:=A;
+ TEMPB:=B;
+ TEMPC:=C;
+ TEMPD:=D;
+ --swap the value of A, B ,C and D so that new value of A,B ,C AND D can be used.
+ temp_AD:= tempA xor tempD;
+ A:= temp_AD xor tempA;
+
+ temp_BA:= tempB xor tempA;
+ B:= temp_BA xor tempB;
+
+ temp_CB:= tempC xor tempB;
+ C:= temp_CB xor tempC;
+
+ temp_DC:= tempD xor tempC;
+ D:= temp_DC xor tempD;
+
+ ready_d <= '0';
+
+
+ when "001000"=>
+
+ STATE <="001001";
+
+
+ t_pre := product1;
+
+
+ u_pre := product2;
+
+ t:= t_pre(11 downto 0) & t_pre(15 downto 12);
+ ttemp1<=t;
+
+
+ u:= u_pre(11 downto 0)& u_pre(15 downto 12);
+ utemp1<=u;
+
+ ready_d <= '0';
+
+
+
+ when "001001"=>
+
+ state <= "001010";
+
+ for i in 1 to 20 loop
+ A_pre_2 := (A - s(2*i)); -- A = A-S[2i]
+ C_pre_2 := (C - s(2*i+1)); -- C = C - S[2i+1]
+ end loop ;
+ ready_d <= '0';
+
+ --sig3<=conv_integer(unsigned(u(3 downto 0)));
+ A_pre :=A_pre_2(sig3-1 downto 0) & A_pre_2(15 downto sig3);
+
+ A := (A_pre xor t); -- A = ((A-S[2i] >>>u) xor t
+ --sig4<=conv_integer(unsigned(t(3 downto 0)));
+ C_pre:=C_pre_2(sig4-1 downto 0)& C_pre_2(15 downto sig4);
+
+ C := (C_pre xor u); -- C = ((C-S[2i+1]>>>t) xor u
+
+ when "001010"=>
+
+ state <= "000001";
+ if(cnt<19 )then
+ cnt:=cnt+1 ;
+ state <="000110";
+ else
+ last_round <='1';
+ state<="001011";
+ cnt:="0000000" ;
+ end if;
+
+
+
+
+
+ when "001011"=>
+
+ state <= "001100";
+ D := D - s(1); -- Calculate final value of D
+ ready_d <= '0';
+
+
+
+ when "001100" =>
+
+ state <= "001101";
+ B := B - s(0); -- Calculate final value of B
+ ready_d <= '1'; -- set ready_d signal high as decryption process is over
+
+ cleanup<='1';
+ ready_d_pre <= '1';-- Assign ready_d_pre high which essentially starts up second FSM.
+
+ when "001101" =>
+
+ if(cleanup='1') then
+ A_final <= A;
+ B_final <= B;
+ C_final <= C;
+ D_final <= D;
+ else
+ A_final <= A_final ;
+ B_final <= B_final ;
+ C_final <= C_final ;
+ D_final <= D_final ;
+ end if;
+
+
+ when others=>
+ state <= "000001";
+ ready_d <= '1';
+ A := (others=>'0');
+ B := (others=>'0');
+ C := (others=>'0');
+ D := (others=>'0');
+
+ end case;
+ end if;
+end process;
+
+
+process(clock,reset,ready_d_pre,A_final,B_final,C_final,D_final)
+ begin
+ if (reset='1') then
+
+ state_out <= idle;
+ plaintext_d <= (others=>'0');
+
+ elsif (clock'event and clock='1') then
+
+ case state_out is --synopsys parallel_case
+ when idle=>
+
+ if (ready_d_pre='1') then
+ state_out <= out_A;
+ else
+ state_out <= idle;
+ plaintext_d <= (others=>'0');
+ end if;
+ when out_A=>
+
+ state_out <= out_B;
+ plaintext_d <= A_final; -- Output plaintext as A
+
+
+ when out_B=>
+
+ state_out <= out_C;
+ plaintext_d <= B_final; -- Output plaintext as B
+
+ when out_C=>
+
+ state_out <= out_D;
+ plaintext_d <= C_final; -- Output plaintext as C
+
+ when out_D=>
+
+ state_out <= idle;
+ plaintext_d <= D_final; -- Output plaintext as D
+
+ when others=>
+
+ state_out <= idle;
+ plaintext_d <= (others=>'0');
+
+ end case;
+ end if;
+ end process;
+
+end arch_decryptor ;
+
+
+
+
+
+
+
Index: trunk/decryption/carrylook_ahead2.vhd
===================================================================
--- trunk/decryption/carrylook_ahead2.vhd (nonexistent)
+++ trunk/decryption/carrylook_ahead2.vhd (revision 4)
@@ -0,0 +1,32 @@
+-----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity carrylook_ahead2 is
+port(a1,b1 : in std_logic_vector(15 downto 0);
+ s1 :out std_logic_vector(15 downto 0);
+ cin :in std_logic);
+
+end carrylook_ahead2;
+
+architecture Behavioral of carrylook_ahead2 is
+signal p ,g : std_logic_vector( 15 downto 0);
+signal c: std_logic_vector( 16 downto 0);
+
+begin
+c(0)<= cin;
+l1: for i in 0 to 15 generate
+p(i)<= a1(i) xor b1(i);
+
+g(i)<=a1(i) and b1(i);
+
+s1(i)<=p(i) xor c(i);
+c(i+1)<=g(i) or (p(i) and c(i));
+
+end generate;
+
+end Behavioral;
+
Index: trunk/decryption/transcript
===================================================================
--- trunk/decryption/transcript (nonexistent)
+++ trunk/decryption/transcript (revision 4)
@@ -0,0 +1,2 @@
+# Reading C:/FPGAdvPersonal63LS/Modeltech/tcl/vsim/pref.tcl
+# OpenFile "G:/crp project/decryption/vsim.wlf"
Index: trunk/decryption/decryptor.vhd
===================================================================
--- trunk/decryption/decryptor.vhd (nonexistent)
+++ trunk/decryption/decryptor.vhd (revision 4)
@@ -0,0 +1,424 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity decryptor is
+
+port (
+ plaintext_d :out std_logic_vector(15 downto 0);-- 16 bit Plaintext output of decryptor
+ ready_d :out std_logic; -- 1 bit ready output of decryptor
+ ciphertext :in std_logic_vector(15 downto 0);-- 16 bit ciphertext input to decrytpor which is output of encryptor
+ round_keys_d:in std_logic_vector(15 downto 0);-- 16 bit roundkeys given to decryptor
+ start_d :in std_logic;
+ reset :in std_logic;
+ clock :in std_logic
+ );
+
+end decryptor;
+
+
+Architecture arch_decryptor of decryptor is
+
+component multiplier
+port( B :in std_logic_vector(15 downto 0);
+ Product :out std_logic_vector(15 downto 0)
+ );
+end component;
+-- constants for the plain text fsm
+
+constant idle:std_logic_vector(3 downto 0):= "0000";
+constant out_A :std_logic_vector(3 downto 0):= "0001";
+constant out_B :std_logic_vector(3 downto 0):= "0010";
+constant out_C :std_logic_vector(3 downto 0):= "0011";
+constant out_D :std_logic_vector(3 downto 0):= "0100";
+
+
+
+
+--ct1, ttemp and utemp are temprary registers to hold the values of t, u and C.
+--signal round_keys_d_saved:std_logic_vector(15 downto 0);
+signal ready_d_pre: std_logic; -- ready_d_pre is used to trigger the plaintext fsm (earlier version of ready_d)
+
+signal state:std_logic_vector(5 downto 0); --state of primary fsm
+signal state_out:std_logic_vector(3 downto 0); -- state of plaintext fsm
+
+signal sig3,sig4:integer range 0 TO 15;
+
+signal last_round ,cleanup : std_logic;
+signal A_final,B_final,C_final,D_final:std_logic_vector(15 downto 0);
+signal utemp1,ttemp1 :std_logic_vector(15 downto 0);-------a_new
+signal A, B, C, D :std_logic_vector(15 downto 0);
+signal product1,product2 : std_logic_vector(15 downto 0);
+---key constant------
+
+ constant p:std_logic_vector(15 downto 0):= "1011011111100001";
+ constant q:std_logic_vector(15 downto 0):= "1001111000110111";
+
+ type s_tp is array(43 downto 0) of std_logic_vector(15 downto 0);
+ signal s :s_tp;
+ type l_tp is array(42 downto 0) of std_logic_vector(15 downto 0);
+ signal l :l_tp;
+
+
+
+begin
+
+a1: multiplier port map (B,product1);
+b1: multiplier port map (D,product2);
+
+
+ sig3<=conv_integer(unsigned(utemp1(3 downto 0)));
+ sig4<=conv_integer(unsigned(ttemp1(3 downto 0)));
+
+
+ ----key algo----
+
+
+ s(0) <= P ; -- initialize constant array
+ l(0)<=(round_keys_d + s(0));
+ s(1)<=(l(0)+ s(0)+ q);
+ l(1)<=( l(0)+s(1));
+ s(2)<=(l(1)+ s(1)+ q);
+ l(2)<=( l(1)+s(2));
+ s(3)<=(l(2)+ s(2)+ q);
+ l(3)<=( l(2)+s(3));
+ s(4)<=(l(3)+ s(3)+ q);
+ l(4)<=( l(3)+s(4));
+ s(5)<=(l(4)+ s(4)+ q);
+ l(5)<=( l(4)+s(5));
+ s(6)<=(l(5)+ s(5)+ q);
+ l(6)<=( l(5)+s(6));
+ s(7)<=(l(6)+ s(6)+ q);
+ l(7)<=( l(6)+s(7));
+ s(8)<=(l(7)+ s(7)+ q);
+ l(8)<=( l(7)+s(8));
+ s(9)<=(l(8)+ s(8)+ q);
+ l(9)<=( l(8)+s(9));
+ s(10)<=(l(9)+ s(9)+ q);
+ l(10)<=( l(9)+s(10 ));
+ s(11)<=(l(10)+ s(10)+ q);
+ l(11)<=( l(10)+s(11));
+ s(12)<=(l(11)+ s(11)+ q);
+ l(12)<=( l(11)+s(12));
+ s(13)<=(l(12)+ s(12)+ q);
+ l(13)<=( l(12)+s(13));
+ s(14)<=(l(13)+ s(13)+ q);
+ l(14)<=( l(13)+s(14));
+ s(15)<=(l(14)+ s(14)+ q);
+ l(15)<=( l(14)+s(15));
+ s(16)<=(l(15)+ s(15)+ q);
+ l(16)<=( l(15)+s(16));
+ s(17)<=(l(16)+ s(16)+ q);
+ l(17)<=( l(16)+s(17));
+ s(18)<=(l(17)+ s(17)+ q);
+ l(18)<=( l(17)+s(18));
+ s(19)<=(l(18)+ s(18)+ q);
+ l(19)<=( l(18)+s(19));
+ s(20)<=(l(19)+ s(19)+ q);
+ l(20)<=( l(19)+s(20));
+ s(21)<=(l(20)+ s(20)+ q);
+ l(21)<=( l(20)+s(21));
+ s(22)<=(l(21)+ s(21)+ q);
+ l(22)<=( l(21)+s(22));
+ s(23)<=(l(22)+ s(22)+ q);
+ l(23)<=( l(22)+s(23));
+ s(24)<=(l(23)+ s(23)+ q);
+ l(24)<=( l(23)+s(24));
+ s(25)<=(l(24)+ s(24)+ q);
+ l(25)<=( l(24)+s(25));
+ s(26)<=(l(25)+ s(25)+ q);
+ l(26)<=( l(25)+s(26));
+ s(27)<=(l(26)+ s(26)+ q);
+ l(27)<=( l(26)+s(27));
+ s(28)<=(l(27)+ s(27)+ q);
+ l(28)<=( l(27)+s(28));
+ s(29)<=(l(28)+ s(28)+ q);
+ l(29)<=( l(23)+s(24));
+ s(30)<=(l(29)+ s(29)+ q);
+ l(30)<=( l(29)+s(30));
+ s(31)<=(l(30)+ s(30)+ q);
+ l(31)<=( l(30)+s(31));
+ s(32)<=(l(31)+ s(31)+ q);
+ l(32)<=( l(31)+s(32));
+ s(33)<=(l(32)+ s(32)+ q);
+ l(33)<=( l(32)+s(33));
+ s(34)<=(l(33)+ s(33)+ q);
+ l(34)<=( l(33)+s(34));
+ s(35)<=(l(34)+ s(34)+ q);
+ l(35)<=( l(34)+s(35));
+ s(36)<=(l(35)+ s(35)+ q);
+ l(36)<=( l(35)+s(36));
+ s(37)<=(l(36)+ s(36)+ q);
+ l(37)<=( l(36)+s(37));
+ s(38)<=(l(37)+ s(37)+ q);
+ l(38)<=( l(37)+s(38));
+ s(39)<=(l(38)+ s(38)+ q);
+ l(39)<=( l(33)+s(34));
+ s(40)<=(l(39)+ s(39)+ q);
+ l(40)<=( l(39)+s(40));
+ s(40)<=(l(39)+ s(39)+ q);
+ l(41)<=( l(40)+s(40));
+ s(41)<=(l(40)+ s(40)+ q);
+ l(42)<=( l(41)+s(41));
+ s(42)<=(l(41)+ s(41)+ q);
+ s(43)<=(l(42)+ s(42)+ q);
+
+
+
+process(clock,reset,ciphertext,sig3,sig4)
+
+
+variable tempA,tempB,tempC,tempD :std_logic_vector(15 downto 0);
+variable temp_AD,temp_BA,temp_CB,temp_DC :std_logic_vector(15 downto 0);
+VARIABLE t,u,t_pre,u_pre:std_logic_vector( 15 downto 0);--temporary VARIABLE used for calculation of A, C, t and u
+VARIABLE A_pre_2,C_pre_2,A_pre ,C_pre :std_logic_vector(15 downto 0);
+
+variable cnt: std_logic_vector(6 downto 0):="0000000";
+
+
+begin
+ if (reset='1') then
+
+ state <= "000001"; -- reset state
+ ready_d <= '0';
+
+ cnt :=(others=>'0');
+
+ A <= (others=>'0');
+ B <= (others=>'0');
+ C <= (others=>'0');
+ D <= (others=>'0');
+ ready_d <= '0';
+ TEMPA:=(others=>'0');
+ TEMPB:=(others=>'0');
+ TEMPC:=(others=>'0');
+ TEMPD:=(others=>'0');
+ temp_AD:= (others=>'0');
+ temp_BA:= (others=>'0');
+ temp_CB:= (others=>'0');
+ temp_DC:= (others=>'0');
+
+
+ elsif(clock'event and clock='1') then
+
+ case state is --synopsys parallel_case
+ when"000001"=>
+
+ if (start_d = '0') then
+ state <= "000001";
+ else
+ state <= "000010";
+ ready_d <= '1';
+ end if;
+
+
+ when "000010"=>
+
+ state <= "000011";
+ A <= ciphertext;--read ciphertext into A
+ ready_d <= '0';
+
+ when "000011"=>
+
+ state <= "000100";
+ B <= ciphertext; -- read ciphertext into B
+ ready_d <= '0';
+
+
+ when "000100"=>
+
+ state <= "000101";
+ C <= ciphertext; -- read ciphertext into C
+ ready_d <= '0';
+
+
+ when "000101"=>
+
+ state <= "000110";
+ D <= ciphertext;--assign ciphertext to D
+ A <= A - s(42); -- Use round keys to calculate new value of A
+ C <= C - s(43); -- read ciphertext - roundkeys into C
+ ready_d <= '0';
+
+
+ when "000110"=> -- begin calculation of plaintext loop from r downto 1
+ state <= "001000";
+ TEMPA:=A;
+ TEMPB:=B;
+ TEMPC:=C;
+ TEMPD:=D;
+ --swap the value of A, B ,C and D so that new value of A,B ,C AND D can be used.
+ temp_AD:= tempA xor tempD;
+ A<= temp_AD xor tempA;
+
+ temp_BA:= tempB xor tempA;
+ B<= temp_BA xor tempB;
+
+ temp_CB:= tempC xor tempB;
+ C<= temp_CB xor tempC;
+
+ temp_DC:= tempD xor tempC;
+ D<= temp_DC xor tempD;
+
+ ready_d <= '0';
+
+
+ when "001000"=>
+
+ STATE <="001001";
+
+
+ t_pre := product1;
+
+
+ u_pre := product2;
+
+ t:= t_pre(11 downto 0) & t_pre(15 downto 12);
+ ttemp1<=t;
+
+
+ u:= u_pre(11 downto 0)& u_pre(15 downto 12);
+ utemp1<=u;
+
+ ready_d <= '0';
+
+
+
+ when "001001"=>
+
+ state <= "001010";
+
+ for i in 1 to 20 loop
+ A_pre_2 := (A - s(2*i)); -- A = A-S[2i]
+ C_pre_2 := (C - s(2*i+1)); -- C = C - S[2i+1]
+ end loop ;
+ ready_d <= '0';
+
+ --sig3<=conv_integer(unsigned(u(3 downto 0)));
+ A_pre :=A_pre_2(sig3-1 downto 0) & A_pre_2(15 downto sig3);
+
+ A <= (A_pre xor t); -- A = ((A-S[2i] >>>u) xor t
+ --sig4<=conv_integer(unsigned(t(3 downto 0)));
+ C_pre:=C_pre_2(sig4-1 downto 0)& C_pre_2(15 downto sig4);
+
+ C <= (C_pre xor u); -- C = ((C-S[2i+1]>>>t) xor u
+
+ when "001010"=>
+
+ state <= "000001";
+ if(cnt<19 )then
+ cnt:=cnt+1 ;
+ state <="000110";
+ else
+ last_round <='1';
+ state<="001011";
+ cnt:="0000000" ;
+ end if;
+
+
+
+
+
+ when "001011"=>
+
+ state <= "001100";
+ D <= D - s(1); -- Calculate final value of D
+ ready_d <= '0';
+
+
+
+ when "001100" =>
+
+ state <= "001101";
+ B <= B - s(0); -- Calculate final value of B
+ ready_d <= '1'; -- set ready_d signal high as decryption process is over
+
+ cleanup<='1';
+ ready_d_pre <= '1';-- Assign ready_d_pre high which essentially starts up second FSM.
+
+ when "001101" =>
+
+ if(cleanup='1') then
+ A_final <= A;
+ B_final <= B;
+ C_final <= C;
+ D_final <= D;
+ else
+ A_final <= A_final ;
+ B_final <= B_final ;
+ C_final <= C_final ;
+ D_final <= D_final ;
+ end if;
+
+
+ when others=>
+ state <= "000001";
+ ready_d <= '1';
+ A <= (others=>'0');
+ B <= (others=>'0');
+ C <= (others=>'0');
+ D <= (others=>'0');
+
+ end case;
+ end if;
+end process;
+
+
+process(clock,reset,ready_d_pre,A_final,B_final,C_final,D_final)
+ begin
+ if (reset='1') then
+
+ state_out <= idle;
+ plaintext_d <= (others=>'0');
+
+ elsif (clock'event and clock='1') then
+
+ case state_out is --synopsys parallel_case
+ when idle=>
+
+ if (ready_d_pre='1') then
+ state_out <= out_A;
+ else
+ state_out <= idle;
+ plaintext_d <= (others=>'0');
+ end if;
+ when out_A=>
+
+ state_out <= out_B;
+ plaintext_d <= A_final; -- Output plaintext as A
+
+
+ when out_B=>
+
+ state_out <= out_C;
+ plaintext_d <= B_final; -- Output plaintext as B
+
+ when out_C=>
+
+ state_out <= out_D;
+ plaintext_d <= C_final; -- Output plaintext as C
+
+ when out_D=>
+
+ state_out <= idle;
+ plaintext_d <= D_final; -- Output plaintext as D
+
+ when others=>
+
+ state_out <= idle;
+ plaintext_d <= (others=>'0');
+
+ end case;
+ end if;
+ end process;
+
+end arch_decryptor ;
+
+
+
+
+
+
+
Index: trunk/decryption/decryptor.mpf
===================================================================
--- trunk/decryption/decryptor.mpf (nonexistent)
+++ trunk/decryption/decryptor.mpf (revision 4)
@@ -0,0 +1,459 @@
+;
+; Copyright Model Technology, a Mentor Graphics Corporation company 2004,
+; All rights reserved.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explict enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messges. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+vlog95compat = 0
+
+[sccom]
+; Disable SystemC name binding during compilation. Default is off.
+; NoNameBind = 1
+
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than ModelSim default.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+resolution = 1ns
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = ns
+
+; Default run length
+RunLength = 100 ns
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+; from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not define for assertion level, use AssertionFormatBreak
+; if assertion triggers a breakpoint (controlled by BreakOnAssertion level),
+; otherwise use AssertionFormat.
+;
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+
+; Assertion File - alternate file for storing VHDL/PSL assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, or deposit
+; or in other terms, fixed, wired, or charged.
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of a generate statement label. Do not quote it.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.
+; This is necessary when C++ files have been compiled with aCC's -AA option.
+; The default behavior is to use /usr/lib/libCsup.sl.
+; UseCsupV2 = 1
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (log only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether or not integer arrays will appear as memories.
+; The default is 1 (display integer arrays as memories).
+; ShowIntMem = 0
+
+; Specify whether or not enumerated type arrays (other than std_logic-based)
+; will appear as memories.
+; The default is 1 (display enumerated type arrays as memories).
+; ShowEnumMem = 0
+
+; Specify whether or not arrays of 3 or more dimensions will appear as memories.
+; The default is 1 (display 3D+ type arrays as memories).
+; Show3DMem = 0
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off PSL assertion pass enable. Default is off.
+; AssertionPassEnable = 1
+
+; Turn on/off PSL assertion fail enable. Default is on.
+; AssertionFailEnable = 0
+
+; Set PSL assertion pass limit. Default is 1.
+; Any positive integer, -1 for infinity.
+; AssertionPassLimit = -1
+
+; Set PSL assertion fail limit. Default is 1.
+; Any positive integer, -1 for infinity.
+; AssertionFailLimit = -1
+
+; Turn on/off PSL assertion pass log. Default is on.
+; AssertionPassLog = 0
+
+; Turn on/off PSL assertion fail log. Default is on.
+; AssertionFailLog = 0
+
+; Set action type for PSL assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+[lmc]
+; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+
+; ModelSim's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = /lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = /lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = /lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = /lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = /lib/linux/libsfi.so
+[Project]
+Project_Version = 5
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 1
+Project_File_0 = G:/crp project/decryption/decryptor.vhd
+Project_File_P_0 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 0 dont_compile 0 cover_stmt 1 vhdl_use93 2002
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+VHDL_DoubleClick = Edit
+VERILOG_DoubleClick = Edit
+SYSTEMC_DoubleClick = Edit
+TCL_DoubleClick = Edit
+TEXT_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+VERILOG_CustomDoubleClick =
+SYSTEMC_CustomDoubleClick =
+TCL_CustomDoubleClick =
+TEXT_CustomDoubleClick =
+ForceSoftPaths = 0
Index: trunk/decryption/vsim.wlf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/decryption/vsim.wlf
===================================================================
--- trunk/decryption/vsim.wlf (nonexistent)
+++ trunk/decryption/vsim.wlf (revision 4)
trunk/decryption/vsim.wlf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/decryption/multiplier.vhd
===================================================================
--- trunk/decryption/multiplier.vhd (nonexistent)
+++ trunk/decryption/multiplier.vhd (revision 4)
@@ -0,0 +1,89 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+
+entity multiplier is
+port( B :in std_logic_vector(15 downto 0);
+ Product :out std_logic_vector(15 downto 0)
+ );
+end multiplier;
+
+architecture Behavioral of multiplier is
+
+signal P1:std_logic_vector(15 downto 0);
+signal P2:std_logic_vector(15 downto 0);
+signal P3:std_logic_vector(15 downto 0);
+signal P4:std_logic_vector(15 downto 0);
+signal P5:std_logic_vector(15 downto 0);
+signal P6:std_logic_vector(15 downto 0);
+signal P7:std_logic_vector(15 downto 0);
+signal P8:std_logic_vector(15 downto 0);
+signal P9:std_logic_vector(15 downto 0);
+
+component wallace_structure is
+port(P1,P2,P3,P4,P5,P6,P7,P8,P9 :in std_logic_vector( 15 downto 0);
+ product :out std_logic_vector( 15 downto 0));
+end component;
+
+begin
+-- partial products reduced to 9 from 16 due to the multiplication of B and 2B+1
+
+P1 <= B;
+
+gen1:for i in 13 downto 1 generate
+p2(i+2) <= B(0) and B(i); --P2 = {{B[3:15] & {13{B[15]}}},1'd0,B[15],1'd0};
+end generate;
+
+p2(2 downto 0)<=('0' & B(0) & '0');
+
+
+gen2:for i in 12 downto 2 generate
+p3(i+3) <= B(1) and B(i); --P3 <= {{B[5:15] & {11{B[14]}}},1'd0,B[14],3'd0};
+end generate;
+
+p3(4 downto 0)<=( '0' & B(1) & "000");
+
+gen3:for i in 11 downto 3 generate
+p4(i+4) <= B(2) and B(i); -- P4 <= {{B[4:12] & {9{B[13]}}},1'd0,B[13],5'd0};
+end generate;
+
+p4(6 downto 0)<=('0'& B(2) & "00000");
+
+
+gen5:for i in 10 downto 4 generate
+p5(i+5) <= B(3) and B(i); -- P5 <= {{B[5:11] & {7{B[12]}}},1'd0,B[12],7'd0};
+end generate;
+
+p5(8 downto 0)<=('0' & B(3) & "0000000");
+
+
+gen6:for i in 9 downto 5 generate
+p6(i+6) <= B(4) and B(i); --P6 <= {{B[6:10] & {5{B[11]}}},1'd0,B[11],9'd0};
+end generate;
+
+p6(10 downto 0)<=( '0' & B(4) & "000000000");
+
+
+gen7:for i in 8 downto 6 generate
+p7(i+7) <= B(5) and B(i); -- P7 <= {{B[7:9] & {3{B[10]}}},1'd0,B[10],11'd0};
+end generate;
+
+p7(12 downto 0)<=( '0' & B(5) & "00000000000");
+
+
+ P8 <= ((B(7) AND B(6)) & '0'& B(6) & "0000000000000");
+
+
+ P9 <= (B(7) & "000000000000000");
+
+w1: wallace_structure port map (P1,P2,P3,P4,P5,P6,P7,P8,P9,product); --Wallace tree
+
+
+
+
+end Behavioral;
+
Index: trunk/decryption/decryp.vhd
===================================================================
--- trunk/decryption/decryp.vhd (nonexistent)
+++ trunk/decryption/decryp.vhd (revision 4)
@@ -0,0 +1 @@
+
Index: trunk/decryption/decryptor.cr.mti
===================================================================
--- trunk/decryption/decryptor.cr.mti (nonexistent)
+++ trunk/decryption/decryptor.cr.mti (revision 4)
@@ -0,0 +1,10 @@
+{G:/crp project/decryption/decryptor.vhd} {1 {vcom -work work -2002 -explicit {G:/crp project/decryption/decryptor.vhd}
+Model Technology ModelSim PE vcom 5.8c Compiler 2004.03 Mar 25 2004
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Compiling entity decryptor
+-- Compiling architecture arch_decryptor of decryptor
+
+} {} {}}
Index: trunk/decryption/decryp.mpf
===================================================================
--- trunk/decryption/decryp.mpf (nonexistent)
+++ trunk/decryption/decryp.mpf (revision 4)
@@ -0,0 +1,459 @@
+;
+; Copyright Model Technology, a Mentor Graphics Corporation company 2004,
+; All rights reserved.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explict enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messges. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+vlog95compat = 0
+
+[sccom]
+; Disable SystemC name binding during compilation. Default is off.
+; NoNameBind = 1
+
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than ModelSim default.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+resolution = 1ns
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = ns
+
+; Default run length
+RunLength = 100 ns
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+; from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not define for assertion level, use AssertionFormatBreak
+; if assertion triggers a breakpoint (controlled by BreakOnAssertion level),
+; otherwise use AssertionFormat.
+;
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+
+; Assertion File - alternate file for storing VHDL/PSL assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, or deposit
+; or in other terms, fixed, wired, or charged.
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of a generate statement label. Do not quote it.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.
+; This is necessary when C++ files have been compiled with aCC's -AA option.
+; The default behavior is to use /usr/lib/libCsup.sl.
+; UseCsupV2 = 1
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (log only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether or not integer arrays will appear as memories.
+; The default is 1 (display integer arrays as memories).
+; ShowIntMem = 0
+
+; Specify whether or not enumerated type arrays (other than std_logic-based)
+; will appear as memories.
+; The default is 1 (display enumerated type arrays as memories).
+; ShowEnumMem = 0
+
+; Specify whether or not arrays of 3 or more dimensions will appear as memories.
+; The default is 1 (display 3D+ type arrays as memories).
+; Show3DMem = 0
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off PSL assertion pass enable. Default is off.
+; AssertionPassEnable = 1
+
+; Turn on/off PSL assertion fail enable. Default is on.
+; AssertionFailEnable = 0
+
+; Set PSL assertion pass limit. Default is 1.
+; Any positive integer, -1 for infinity.
+; AssertionPassLimit = -1
+
+; Set PSL assertion fail limit. Default is 1.
+; Any positive integer, -1 for infinity.
+; AssertionFailLimit = -1
+
+; Turn on/off PSL assertion pass log. Default is on.
+; AssertionPassLog = 0
+
+; Turn on/off PSL assertion fail log. Default is on.
+; AssertionFailLog = 0
+
+; Set action type for PSL assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+[lmc]
+; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+
+; ModelSim's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = /lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = /lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = /lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = /lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = /lib/linux/libsfi.so
+[Project]
+Project_Version = 5
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 1
+Project_File_0 = G:/final crp project/decryption/decryptor.vhd
+Project_File_P_0 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1232621188 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 0 dont_compile 0 vhdl_use93 2002 cover_stmt 1
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+VHDL_DoubleClick = Edit
+VERILOG_DoubleClick = Edit
+SYSTEMC_DoubleClick = Edit
+TCL_DoubleClick = Edit
+TEXT_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+VERILOG_CustomDoubleClick =
+SYSTEMC_CustomDoubleClick =
+TCL_CustomDoubleClick =
+TEXT_CustomDoubleClick =
+ForceSoftPaths = 0
Index: trunk/decryption/wallace_structure.vhd
===================================================================
--- trunk/decryption/wallace_structure.vhd (nonexistent)
+++ trunk/decryption/wallace_structure.vhd (revision 4)
@@ -0,0 +1,64 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:03:30 10/09/2007
+-- Design Name:
+-- Module Name: wallace_structure - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+
+entity wallace_structure is
+
+port(P1,P2,P3,P4,P5,P6,P7,P8,P9 :in std_logic_vector( 15 downto 0);
+ product :out std_logic_vector( 15 downto 0));
+
+
+
+end wallace_structure;
+
+architecture Behavioral of wallace_structure is
+signal s1,s2 :std_logic_vector ( 15 downto 0);
+signal c_out :std_logic;
+component carrysave_adder is
+port (p1,p2,p3,p4,p5,p6,p7,p8,p9 :in std_logic_vector ( 15 downto 0);
+ s1 : out std_logic_vector (15 downto 0);
+ c1 :out std_logic_vector (15 downto 0));
+end component;
+
+component carrylook_ahead2 is
+port(a1,b1 : in std_logic_vector(15 downto 0);
+ s1 :out std_logic_vector(15 downto 0);
+ cin :in std_logic);
+
+end component;
+
+
+
+
+begin
+
+ca1:carrysave_adder port map(P1,P2,P3,P4,P5,P6,P7,P8,P9,s1,s2 );
+ca2:carrylook_ahead2 port map(s1,s2,product,'0');
+
+
+
+
+end Behavioral;
+
Index: trunk/decryption/carrysave_adder.vhd
===================================================================
--- trunk/decryption/carrysave_adder.vhd (nonexistent)
+++ trunk/decryption/carrysave_adder.vhd (revision 4)
@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:10:53 10/09/2007
+-- Design Name:
+-- Module Name: carrysave_adder - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+
+entity carrysave_adder is
+port (p1,p2,p3,p4,p5,p6,p7,p8,p9 :in std_logic_vector ( 15 downto 0);
+ s1 : out std_logic_vector (15 downto 0);
+ c1 :out std_logic_vector (15 downto 0));
+
+
+end carrysave_adder;
+
+architecture Behavioral of carrysave_adder is
+
+
+ component full_adder
+ port (a,b,c :in std_logic_vector(15 downto 0) ;
+ sf,cf :out std_logic_vector(15 downto 0) );
+ end component;
+
+signal su1,ca1 :std_logic_vector (15 downto 0);
+signal su2,ca2 :std_logic_vector (15 downto 0);
+signal su3,ca3 :std_logic_vector (15 downto 0);
+signal su4,ca4 :std_logic_vector (15 downto 0);
+signal su5,ca5 :std_logic_vector (15 downto 0);
+signal su6,ca6 :std_logic_vector (15 downto 0);
+
+
+begin
+ fa0 : full_adder port map(p1,p2,p3,su1,ca1);
+ fa1 : full_adder port map(p4,p5,p6,su2,ca2);
+ fa2 : full_adder port map(p7,p8,p9,su3,ca3);
+ fa3 : full_adder port map(ca1,su1,su2,su4,ca4);
+ fa4 : full_adder port map(ca3,su3,ca2,su5,ca5);
+ fa5 : full_adder port map(ca4,su4,su5,su6,ca6);
+ fa6 : full_adder port map(ca6,su6,ca5,s1,c1);
+
+
+
+
+
+end Behavioral;
+
Index: trunk/encryption/encry.vhd
===================================================================
--- trunk/encryption/encry.vhd (nonexistent)
+++ trunk/encryption/encry.vhd (revision 4)
@@ -0,0 +1,459 @@
+ ----------------------------------------------------------------------------------
+-- Description:Implements the RC6 encryption algorithm.
+-- Everything based on a positive edge of clock and
+-- an asynchronous reset.
+--
+-- Module contains two finite state machines.
+--
+-- One fsm controls the calculation of the various
+-- rounds. Another fsm is responsible for outputting
+-- the ciphertext so the encryptor can accept plain
+-- text while cipher text is still in the process of
+-- going out.
+--
+-- We assume the number of rounds to be 20.
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- encryptor module declaration
+
+entity encryptor is
+
+port (
+ plaintext_e :in std_logic_vector(15 downto 0);-- 16 bit Plaintext output of decryptor
+ round_keyse :in std_logic_vector(15 downto 0);-- 16 bit roundkeys given to decryptor
+ start_e:in std_logic; --1 bit ready signal for encryptor
+ reset :in std_logic; --reset
+ clock :in std_logic ; --clock
+ ready_e :out std_logic; -- 1 bit ready output of decryptor
+ ciphertext: out std_logic_vector(15 downto 0)-- 16 bit ciphertext input to decrytpor which is output of encryptor
+
+ );
+
+end encryptor;
+
+
+Architecture arch_encryptor of encryptor is
+
+-------wallace tree
+
+component multiplier
+port( B :in std_logic_vector(15 downto 0);
+ Product :out std_logic_vector(15 downto 0)
+ );
+end component;
+
+-------- constant for key generation.
+
+constant p:std_logic_vector(15 downto 0):= "1011011111100001";------constant value p
+constant q:std_logic_vector(15 downto 0):= "1001111000110111";------constant value q
+
+type s_tp is array(43 downto 0) of std_logic_vector(15 downto 0);--array of 44 * 16
+signal s :s_tp;
+
+type l_tp is array(42 downto 0) of std_logic_vector(15 downto 0);--array of 43 *16
+signal l :l_tp;
+
+--constant round_keyse : std_logic_vector(15 downto 0):= "0000000000000000";
+
+
+--------- constants for the plain text fsm
+
+constant out_idle:std_logic_vector(3 downto 0):= "0000";
+constant out_A :std_logic_vector(3 downto 0):= "0001";
+constant out_B :std_logic_vector(3 downto 0):= "0010";
+constant out_C :std_logic_vector(3 downto 0):= "0011";
+constant out_D :std_logic_vector(3 downto 0):= "0100";
+
+
+
+--------- signals needed for internal connections
+
+signal cleanup_A,cleanup_C ,start_d1,last_round: std_logic;
+signal next_state_out: std_logic_vector( 3 downto 0);
+signal state:std_logic_vector(5 downto 0); --state of primary fsm
+signal state_out:std_logic_vector(3 downto 0); -- state of plaintext fsm
+signal utemp1,ttemp1:std_logic_vector(15 downto 0);
+
+signal sig3,sig4:INTEGER RANGE 0 TO 15;
+
+signal A_final,B_final,C_final,D_final:std_logic_vector(15 downto 0);
+signal A,B,C,D : std_logic_vector(15 downto 0);
+signal product1,product2 : std_logic_vector(15 downto 0);
+
+begin
+
+ --------fsm for input --------
+
+a1: multiplier port map (B,product1);
+b1: multiplier port map (D,product2);
+
+ sig3<=conv_integer(unsigned(utemp1(3 downto 0)));
+ sig4<=conv_integer(unsigned(ttemp1(3 downto 0)));
+ --------key generation operation------
+
+ s(0) <= P ; -- initialize constant array
+ l(0)<=(round_keyse +s(0));
+ s(1)<=(l(0)+ s(0)+ q);
+ l(1)<=( l(0)+s(1));
+ s(2)<=(l(1)+ s(1)+ q);
+ l(2)<=( l(1)+s(2));
+ s(3)<=(l(2)+ s(2)+ q);
+ l(3)<=( l(2)+s(3));
+ s(4)<=(l(3)+ s(3)+ q);
+ l(4)<=( l(3)+s(4));
+ s(5)<=(l(4)+ s(4)+ q);
+ l(5)<=( l(4)+s(5));
+ s(6)<=(l(5)+ s(5)+ q);
+ l(6)<=( l(5)+s(6));
+ s(7)<=(l(6)+ s(6)+ q);
+ l(7)<=( l(6)+s(7));
+ s(8)<=(l(7)+ s(7)+ q);
+ l(8)<=( l(7)+s(8));
+ s(9)<=(l(8)+s(8)+ q);
+ l(9)<=( l(8)+s(9));
+ s(10)<=(l(9)+s(9)+ q);
+ l(10)<=( l(9)+s(10 ));
+ s(11)<=(l(10)+s(10)+ q);
+ l(11)<=( l(10)+s(11));
+ s(12)<=(l(11)+ s(11)+ q);
+ l(12)<=( l(11)+s(12));
+ s(13)<=(l(12)+s(12)+ q);
+ l(13)<=( l(12)+s(13));
+ s(14)<=(l(13)+ s(13)+ q);
+ l(14)<=( l(13)+s(14));
+ s(15)<=(l(14)+ s(14)+ q);
+ l(15)<=( l(14)+s(15));
+ s(16)<=(l(15)+ s(15)+ q);
+ l(16)<=( l(15)+s(16));
+ s(17)<=(l(16)+ s(16)+ q);
+ l(17)<=( l(16)+s(17));
+ s(18)<=(l(17)+ s(17)+ q);
+ l(18)<=( l(17)+s(18));
+ s(19)<=(l(18)+ s(18)+ q);
+ l(19)<=( l(18)+s(19));
+ s(20)<=(l(19)+ s(19)+ q);
+ l(20)<=( l(19)+s(20));
+ s(21)<=(l(20)+ s(20)+ q);
+ l(21)<=( l(20)+s(21));
+ s(22)<=(l(21)+ s(21)+ q);
+ l(22)<=( l(21)+s(22));
+ s(23)<=(l(22)+ s(22)+ q);
+ l(23)<=( l(22)+s(23));
+ s(24)<=(l(23)+ s(23)+ q);
+ l(24)<=( l(23)+s(24));
+ s(25)<=(l(24)+ s(24)+ q);
+ l(25)<=( l(24)+s(25));
+ s(26)<=(l(25)+ s(25)+ q);
+ l(26)<=( l(25)+s(26));
+ s(27)<=(l(26)+ s(26)+ q);
+ l(27)<=( l(26)+s(27));
+ s(28)<=(l(27)+ s(27)+ q);
+ l(28)<=( l(27)+s(28));
+ s(29)<=(l(28)+ s(28)+ q);
+ l(29)<=( l(23)+s(24));
+ s(30)<=(l(29)+ s(29)+ q);
+ l(30)<=( l(29)+s(30));
+ s(31)<=(l(30)+ s(30)+ q);
+ l(31)<=( l(30)+s(31));
+ s(32)<=(l(31)+ s(31)+ q);
+ l(32)<=( l(31)+s(32));
+ s(33)<=(l(32)+ s(32)+ q);
+ l(33)<=( l(32)+s(33));
+ s(34)<=(l(33)+ s(33)+ q);
+ l(34)<=( l(33)+s(34));
+ s(35)<=(l(34)+ s(34)+ q);
+ l(35)<=( l(34)+s(35));
+ s(36)<=(l(35)+ s(35)+ q);
+ l(36)<=( l(35)+s(36));
+ s(37)<=(l(36)+ s(36)+ q);
+ l(37)<=( l(36)+s(37));
+ s(38)<=(l(37)+ s(37)+ q);
+ l(38)<=( l(37)+s(38));
+ s(39)<=(l(38)+ s(38)+ q);
+ l(39)<=( l(33)+s(34));
+ s(40)<=(l(39)+ s(39)+ q);
+ l(40)<=( l(39)+s(40));
+ s(40)<=(l(39)+ s(39)+ q);
+ l(41)<=( l(40)+s(40));
+ s(41)<=(l(40)+ s(40)+ q);
+ l(42)<=( l(41)+s(41));
+ s(42)<=(l(41)+ s(41)+ q);
+ s(43)<=(l(42)+ s(42)+ q);
+
+
+process(clock,reset,plaintext_e,sig3,sig4)
+
+-----internal variable declaration
+
+variable t_pre,u_pre:std_logic_vector(15 downto 0);
+--variable p1,p2 : std_logic_vector(47 downto 0);
+VARIABLE t,u,A_temp2,C_temp2,A_temp1,C_temp1:std_logic_vector( 15 downto 0);
+variable tempA,tempB,tempC,tempD :std_logic_vector(15 downto 0);
+variable temp_AB,temp_BC,temp_CD,temp_DA :std_logic_vector(15 downto 0);
+variable cnt: std_logic_vector(6 downto 0):="0000000";
+
+begin
+
+
+
+
+
+ if (reset='1') then
+
+ state <= "000001"; -- reset state
+ ready_e <= '0';
+ cnt:=(others=>'0');
+ A <= (others=>'0');
+ B <= (others=>'0');
+ C <= (others=>'0');
+ D <= (others=>'0');
+ ready_e <= '0';
+
+ elsif(clock'event and clock='1') then
+
+ case state is --synopsys parallel_case
+ when"000001"=>
+
+ if (start_e = '0') then
+ state <= "000001";
+ else
+ state <= "000010";
+ ready_e <= '1';
+ end if;
+
+
+ when "000010"=>
+
+ state <= "000011";
+ A <= plaintext_e;--read ciphertext into A
+ ready_e <= '0';
+
+ when "000011"=>
+
+ state <= "000100";
+ B <= plaintext_e; -- read ciphertext into B
+ ready_e <= '0';
+
+
+ when "000100"=>
+
+ state <= "000101";
+ C <= plaintext_e ; -- read ciphertext - into C
+ B <= B+ s(0) ;-- Use round keys to calculate new value of B
+ ready_e<= '0';
+
+
+ when "000101"=>
+
+ state <= "000110";
+ D <= plaintext_e;--assign ciphertext to D
+ ready_e <= '0';
+
+
+ when "000110"=> -- begin calculation of plaintext loop from r downto 1
+
+ state<= "000111" ;
+
+ D <= D + s(1); -- Use round keys to calculate new value of D
+
+
+ ready_e <='0';
+
+ when "000111" =>
+
+ STATE <="001000";
+
+ --t= (B * (2B+1))
+
+ t_pre := product1;
+
+
+ --t= (D * (2D+1))
+
+ u_pre := product2;
+
+ t:= t_pre(11 downto 0)& t_pre(15 downto 12);
+
+ ttemp1<=t;
+ --t= (B * (2B+1)) <<<4
+
+
+ u:= u_pre(11 downto 0)& u_pre(15 downto 12);
+
+ utemp1<=u;
+ --u= (D * (2D+1)) <<<4
+
+ A_temp1 := (A xor t);
+ C_temp1 := (C xor u);
+
+
+
+ when "001000" =>
+
+ state <="001001" ;
+
+
+
+
+
+ A_temp2:=A_temp1(15-sig3 downto 0)& A_temp1(15 downto 15-sig3+1);
+ ---rotate (A xor t) << u
+
+ C_temp2:=C_temp1(15-sig4 downto 0)& C_temp1(15 downto 15-sig4+1);
+ ---rotate (c xor u) << t
+
+
+ for i in 1 to 20 loop
+ A <= (A_temp2 + s(2*i));
+ C <= (C_temp2 + s(2*i+1));
+ end loop;
+
+
+ when "001001"=>
+ state <="001010";
+ -------swap operation---------
+ TEMPA:=A;
+ TEMPB:=B;
+ TEMPC:=C;
+ TEMPD:=D;
+
+ temp_AB:= tempA xor tempB;
+ A<= temp_AB xor tempA;
+
+ temp_BC:= tempB xor tempC;
+ B<= temp_BC xor tempB;
+
+ temp_CD:= tempC xor tempD;
+ C<= temp_CD xor tempC;
+
+ temp_DA:= tempD xor tempA;
+ D<= temp_DA xor tempD;
+
+ ready_e <= '0';
+
+ WHEN "001010" =>
+ ------start counter------
+ if(cnt<19)then
+ cnt:=cnt+1 ;
+ state <="000111";
+ else
+ state<="001011";
+ cnt:="0000000" ;
+ last_round <='1';
+ end if;
+
+
+
+ when "001011" =>
+
+ state <= "001100";
+ if (last_round ='1') then
+ -- calculate last A value
+ cleanup_A <= '1';
+ -- calculate last C value
+ cleanup_C <= '1';
+ else
+ cleanup_A <= '0';
+ cleanup_C <= '0';
+ end if;
+
+ when "001100" =>
+
+ state <= "000001";
+
+
+ --rounds are over
+ --now do the cleanup
+ if (cleanup_A='1') then
+ A_final <= A + s(42); --A_temp2 + round_keys_e_saved;
+ B_final <= B;--B_temp2;
+ D_final <= D;--D_temp2;
+ else
+ A_final <= A_final;
+ B_final <= B_final;
+ D_final <= D_final;
+ end if;
+
+ if (cleanup_C='1') then
+ C_final <= C + s(43);
+ start_d1 <= '1';
+ else
+ C_final <= C_final;
+ start_d1 <= '0';
+ end if;
+
+ when others =>
+ state <="000001" ;
+
+ end case;
+end if;
+end process;
+
+
+
+-- current state logic for output FSM
+process(clock,reset )
+begin
+ -- if reset stay idle
+ -- else output based on
+ --state
+ if (reset='1') then
+ state_out <= out_idle;
+ elsif(clock'event and clock='1') then
+ state_out <= next_state_out;
+ end if;
+end process;
+
+
+-- next state, output logic for output FSM
+process(state_out,start_d1,A_final,B_final,C_final,D_final)
+begin
+ case state_out is --synopsys parallel_case
+ when out_idle=>
+
+ -- wait for start_d
+ if (start_d1='1') then
+ next_state_out <= out_A;
+ else
+ next_state_out <= out_idle;
+ ciphertext <= (others=>'0');
+ end if;
+ when out_A=>
+
+ next_state_out <= out_B;
+ -- output A
+ ciphertext <= A_final;----------ouput cipher text 1
+
+ when out_B=>
+
+ next_state_out <= out_C;
+ -- output B
+ ciphertext <= B_final;----------ouput cipher text 2
+
+ when out_C=>
+
+ next_state_out <= out_D;
+ -- output C
+ ciphertext <= C_final;----------ouput cipher text 3
+
+ when out_D=>
+
+ next_state_out <= out_idle;
+ -- output D
+ ciphertext <= D_final;----------ouput cipher text 4
+
+ when others=>
+
+ next_state_out <= out_idle;
+ ciphertext <= (others=>'0');
+
+ end case;
+
+-----------------------complete output come after 93 clock---------------------
+
+end process;
+end arch_encryptor ;
Index: trunk/encryption/full_adder.vhd
===================================================================
--- trunk/encryption/full_adder.vhd (nonexistent)
+++ trunk/encryption/full_adder.vhd (revision 4)
@@ -0,0 +1,40 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:41:01 10/09/2007
+-- Design Name:
+-- Module Name: full_adder - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+
+entity full_adder is
+
+port ( a,b,c : in std_logic_vector (15 downto 0);
+ sf,cf : out std_logic_vector (15 downto 0));
+end full_adder;
+
+architecture Behavioral of full_adder is
+signal sig:std_logic_vector (15 downto 0);
+begin
+ sf <= a xor b xor c;
+ sig <= (a and b)or (a and c) or (b and c);
+ cf <= (sig(14 downto 0) & '0');
+end Behavioral;
+
Index: trunk/encryption/encry.mpf
===================================================================
--- trunk/encryption/encry.mpf (nonexistent)
+++ trunk/encryption/encry.mpf (revision 4)
@@ -0,0 +1,459 @@
+;
+; Copyright Model Technology, a Mentor Graphics Corporation company 2004,
+; All rights reserved.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explict enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messges. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+vlog95compat = 0
+
+[sccom]
+; Disable SystemC name binding during compilation. Default is off.
+; NoNameBind = 1
+
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than ModelSim default.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+resolution = 1ns
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = ns
+
+; Default run length
+RunLength = 100 ns
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+; from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not define for assertion level, use AssertionFormatBreak
+; if assertion triggers a breakpoint (controlled by BreakOnAssertion level),
+; otherwise use AssertionFormat.
+;
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+
+; Assertion File - alternate file for storing VHDL/PSL assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, or deposit
+; or in other terms, fixed, wired, or charged.
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of a generate statement label. Do not quote it.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.
+; This is necessary when C++ files have been compiled with aCC's -AA option.
+; The default behavior is to use /usr/lib/libCsup.sl.
+; UseCsupV2 = 1
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (log only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether or not integer arrays will appear as memories.
+; The default is 1 (display integer arrays as memories).
+; ShowIntMem = 0
+
+; Specify whether or not enumerated type arrays (other than std_logic-based)
+; will appear as memories.
+; The default is 1 (display enumerated type arrays as memories).
+; ShowEnumMem = 0
+
+; Specify whether or not arrays of 3 or more dimensions will appear as memories.
+; The default is 1 (display 3D+ type arrays as memories).
+; Show3DMem = 0
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off PSL assertion pass enable. Default is off.
+; AssertionPassEnable = 1
+
+; Turn on/off PSL assertion fail enable. Default is on.
+; AssertionFailEnable = 0
+
+; Set PSL assertion pass limit. Default is 1.
+; Any positive integer, -1 for infinity.
+; AssertionPassLimit = -1
+
+; Set PSL assertion fail limit. Default is 1.
+; Any positive integer, -1 for infinity.
+; AssertionFailLimit = -1
+
+; Turn on/off PSL assertion pass log. Default is on.
+; AssertionPassLog = 0
+
+; Turn on/off PSL assertion fail log. Default is on.
+; AssertionFailLog = 0
+
+; Set action type for PSL assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+[lmc]
+; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+
+; ModelSim's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = /lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = /lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = /lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = /lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = /lib/linux/libsfi.so
+[Project]
+Project_Version = 5
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 1
+Project_File_0 = G:/crp project/encryption/encry.vhd
+Project_File_P_0 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 0 dont_compile 0 cover_stmt 1 vhdl_use93 2002
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+VHDL_DoubleClick = Edit
+VERILOG_DoubleClick = Edit
+SYSTEMC_DoubleClick = Edit
+TCL_DoubleClick = Edit
+TEXT_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+VERILOG_CustomDoubleClick =
+SYSTEMC_CustomDoubleClick =
+TCL_CustomDoubleClick =
+TEXT_CustomDoubleClick =
+ForceSoftPaths = 0
Index: trunk/encryption/work/encryptor/arch_encryptor.psm
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/encryption/work/encryptor/arch_encryptor.psm
===================================================================
--- trunk/encryption/work/encryptor/arch_encryptor.psm (nonexistent)
+++ trunk/encryption/work/encryptor/arch_encryptor.psm (revision 4)
trunk/encryption/work/encryptor/arch_encryptor.psm
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/encryption/work/encryptor/_primary.dat
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/encryption/work/encryptor/_primary.dat
===================================================================
--- trunk/encryption/work/encryptor/_primary.dat (nonexistent)
+++ trunk/encryption/work/encryptor/_primary.dat (revision 4)
trunk/encryption/work/encryptor/_primary.dat
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/encryption/work/encryptor/arch_encryptor.dat
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/encryption/work/encryptor/arch_encryptor.dat
===================================================================
--- trunk/encryption/work/encryptor/arch_encryptor.dat (nonexistent)
+++ trunk/encryption/work/encryptor/arch_encryptor.dat (revision 4)
trunk/encryption/work/encryptor/arch_encryptor.dat
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/encryption/work/_info
===================================================================
--- trunk/encryption/work/_info (nonexistent)
+++ trunk/encryption/work/_info (revision 4)
@@ -0,0 +1,61 @@
+m255
+cModel Technology
+dE:\anand_doc\project_testin
+Edecryptor
+DP ieee std_logic_unsigned hEMVMlaNCR^_ffSOVF0
+OE;C;5.8c;15
+32
+M3 ieee std_logic_1164
+M2 ieee std_logic_arith
+M1 ieee std_logic_unsigned
+o-work work
+tExplicit T
+Eencryptor
+DP ieee std_logic_unsigned hEMVMlaNCR^5=PK22
+OE;C;5.8c;15
+32
+o-work work
+tExplicit T
+Aarch_encryptor
+DP ieee std_logic_unsigned hEMVMlaNCR^5=PK22
+l77
+L39
+VhIz>3Rz@ao>A_C2oKIS2>3
+OE;C;5.8c;15
+32
+M3 ieee std_logic_1164
+M2 ieee std_logic_arith
+M1 ieee std_logic_unsigned
+o-work work
+tExplicit T
Index: trunk/encryption/work/decryptor/arch_decryptor.dat
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/encryption/work/decryptor/arch_decryptor.dat
===================================================================
--- trunk/encryption/work/decryptor/arch_decryptor.dat (nonexistent)
+++ trunk/encryption/work/decryptor/arch_decryptor.dat (revision 4)
trunk/encryption/work/decryptor/arch_decryptor.dat
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/encryption/work/decryptor/arch_decryptor.psm
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/encryption/work/decryptor/arch_decryptor.psm
===================================================================
--- trunk/encryption/work/decryptor/arch_decryptor.psm (nonexistent)
+++ trunk/encryption/work/decryptor/arch_decryptor.psm (revision 4)
trunk/encryption/work/decryptor/arch_decryptor.psm
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/encryption/work/decryptor/_primary.dat
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/encryption/work/decryptor/_primary.dat
===================================================================
--- trunk/encryption/work/decryptor/_primary.dat (nonexistent)
+++ trunk/encryption/work/decryptor/_primary.dat (revision 4)
trunk/encryption/work/decryptor/_primary.dat
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/encryption/output wave/final.wlf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/encryption/output wave/final.wlf
===================================================================
--- trunk/encryption/output wave/final.wlf (nonexistent)
+++ trunk/encryption/output wave/final.wlf (revision 4)
trunk/encryption/output wave/final.wlf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/encryption/output wave/transcript
===================================================================
--- trunk/encryption/output wave/transcript (nonexistent)
+++ trunk/encryption/output wave/transcript (revision 4)
@@ -0,0 +1,5 @@
+# Reading C:/FPGAdvPersonal63LS/Modeltech/tcl/vsim/pref.tcl
+# OpenFile "G:/final crp project/encryption/output wave/final.wlf"
+quit -sim
+project open {G:/deepak crp/enc/enc}
+# Loading project enc
Index: trunk/encryption/output wave/new value.wlf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/encryption/output wave/new value.wlf
===================================================================
--- trunk/encryption/output wave/new value.wlf (nonexistent)
+++ trunk/encryption/output wave/new value.wlf (revision 4)
trunk/encryption/output wave/new value.wlf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/encryption/vsim.wlf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/encryption/vsim.wlf
===================================================================
--- trunk/encryption/vsim.wlf (nonexistent)
+++ trunk/encryption/vsim.wlf (revision 4)
trunk/encryption/vsim.wlf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/encryption/multiplier.vhd
===================================================================
--- trunk/encryption/multiplier.vhd (nonexistent)
+++ trunk/encryption/multiplier.vhd (revision 4)
@@ -0,0 +1,89 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+
+entity multiplier is
+port( B :in std_logic_vector(15 downto 0);
+ Product :out std_logic_vector(15 downto 0)
+ );
+end multiplier;
+
+architecture Behavioral of multiplier is
+
+signal P1:std_logic_vector(15 downto 0);
+signal P2:std_logic_vector(15 downto 0);
+signal P3:std_logic_vector(15 downto 0);
+signal P4:std_logic_vector(15 downto 0);
+signal P5:std_logic_vector(15 downto 0);
+signal P6:std_logic_vector(15 downto 0);
+signal P7:std_logic_vector(15 downto 0);
+signal P8:std_logic_vector(15 downto 0);
+signal P9:std_logic_vector(15 downto 0);
+
+component wallace_structure is
+port(P1,P2,P3,P4,P5,P6,P7,P8,P9 :in std_logic_vector( 15 downto 0);
+ product :out std_logic_vector( 15 downto 0));
+end component;
+
+begin
+-- partial products reduced to 9 from 16 due to the multiplication of B and 2B+1
+
+P1 <= B;
+
+gen1:for i in 13 downto 1 generate
+p2(i+2) <= B(0) and B(i); --P2 = {{B[3:15] & {13{B[15]}}},1'd0,B[15],1'd0};
+end generate;
+
+p2(2 downto 0)<=('0' & B(0) & '0');
+
+
+gen2:for i in 12 downto 2 generate
+p3(i+3) <= B(1) and B(i); --P3 <= {{B[5:15] & {11{B[14]}}},1'd0,B[14],3'd0};
+end generate;
+
+p3(4 downto 0)<=( '0' & B(1) & "000");
+
+gen3:for i in 11 downto 3 generate
+p4(i+4) <= B(2) and B(i); -- P4 <= {{B[4:12] & {9{B[13]}}},1'd0,B[13],5'd0};
+end generate;
+
+p4(6 downto 0)<=('0'& B(2) & "00000");
+
+
+gen5:for i in 10 downto 4 generate
+p5(i+5) <= B(3) and B(i); -- P5 <= {{B[5:11] & {7{B[12]}}},1'd0,B[12],7'd0};
+end generate;
+
+p5(8 downto 0)<=('0' & B(3) & "0000000");
+
+
+gen6:for i in 9 downto 5 generate
+p6(i+6) <= B(4) and B(i); --P6 <= {{B[6:10] & {5{B[11]}}},1'd0,B[11],9'd0};
+end generate;
+
+p6(10 downto 0)<=( '0' & B(4) & "000000000");
+
+
+gen7:for i in 8 downto 6 generate
+p7(i+7) <= B(5) and B(i); -- P7 <= {{B[7:9] & {3{B[10]}}},1'd0,B[10],11'd0};
+end generate;
+
+p7(12 downto 0)<=( '0' & B(5) & "00000000000");
+
+
+ P8 <= ((B(7) AND B(6)) & '0'& B(6) & "0000000000000");
+
+
+ P9 <= (B(7) & "000000000000000");
+
+w1: wallace_structure port map (P1,P2,P3,P4,P5,P6,P7,P8,P9,product); --Wallace tree
+
+
+
+
+end Behavioral;
+
Index: trunk/encryption/wallace_structure.vhd
===================================================================
--- trunk/encryption/wallace_structure.vhd (nonexistent)
+++ trunk/encryption/wallace_structure.vhd (revision 4)
@@ -0,0 +1,64 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:03:30 10/09/2007
+-- Design Name:
+-- Module Name: wallace_structure - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+
+entity wallace_structure is
+
+port(P1,P2,P3,P4,P5,P6,P7,P8,P9 :in std_logic_vector( 15 downto 0);
+ product :out std_logic_vector( 15 downto 0));
+
+
+
+end wallace_structure;
+
+architecture Behavioral of wallace_structure is
+signal s1,s2 :std_logic_vector ( 15 downto 0);
+signal c_out :std_logic;
+component carrysave_adder is
+port (p1,p2,p3,p4,p5,p6,p7,p8,p9 :in std_logic_vector ( 15 downto 0);
+ s1 : out std_logic_vector (15 downto 0);
+ c1 :out std_logic_vector (15 downto 0));
+end component;
+
+component carrylook_ahead2 is
+port(a1,b1 : in std_logic_vector(15 downto 0);
+ s1 :out std_logic_vector(15 downto 0);
+ cin :in std_logic);
+
+end component;
+
+
+
+
+begin
+
+ca1:carrysave_adder port map(P1,P2,P3,P4,P5,P6,P7,P8,P9,s1,s2 );
+ca2:carrylook_ahead2 port map(s1,s2,product,'0');
+
+
+
+
+end Behavioral;
+
Index: trunk/encryption/carrylook_ahead2.vhd
===================================================================
--- trunk/encryption/carrylook_ahead2.vhd (nonexistent)
+++ trunk/encryption/carrylook_ahead2.vhd (revision 4)
@@ -0,0 +1,32 @@
+-----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity carrylook_ahead2 is
+port(a1,b1 : in std_logic_vector(15 downto 0);
+ s1 :out std_logic_vector(15 downto 0);
+ cin :in std_logic);
+
+end carrylook_ahead2;
+
+architecture Behavioral of carrylook_ahead2 is
+signal p ,g : std_logic_vector( 15 downto 0);
+signal c: std_logic_vector( 16 downto 0);
+
+begin
+c(0)<= cin;
+l1: for i in 0 to 15 generate
+p(i)<= a1(i) xor b1(i);
+
+g(i)<=a1(i) and b1(i);
+
+s1(i)<=p(i) xor c(i);
+c(i+1)<=g(i) or (p(i) and c(i));
+
+end generate;
+
+end Behavioral;
+
Index: trunk/encryption/transcript
===================================================================
Index: trunk/encryption/TB.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/encryption/TB.doc
===================================================================
--- trunk/encryption/TB.doc (nonexistent)
+++ trunk/encryption/TB.doc (revision 4)
trunk/encryption/TB.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/encryption/encryptor_tb.vhd
===================================================================
--- trunk/encryption/encryptor_tb.vhd (nonexistent)
+++ trunk/encryption/encryptor_tb.vhd (revision 4)
@@ -0,0 +1,74 @@
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_arith.all ;
+USE ieee.std_logic_unsigned.all ;
+ENTITY encryptor_tb IS
+END ;
+
+ARCHITECTURE encryptor_tb_arch OF encryptor_tb IS
+ SIGNAL ciphertext : std_logic_vector (15 downto 0) ;
+ SIGNAL clock : std_logic :='0' ;
+ SIGNAL round_keyse : std_logic_vector (15 downto 0) ;
+ SIGNAL ready_e : std_logic ;
+ SIGNAL plaintext_e : std_logic_vector (15 downto 0) ;
+ SIGNAL start_e : std_logic ;
+ SIGNAL reset : std_logic ;
+ COMPONENT encryptor
+ PORT (
+ ciphertext : out std_logic_vector (15 downto 0) ;
+ clock : in std_logic ;
+ round_keyse : in std_logic_vector (15 downto 0) ;
+ ready_e : out std_logic ;
+ plaintext_e : in std_logic_vector (15 downto 0) ;
+ start_e : in std_logic ;
+ reset : in std_logic );
+ END COMPONENT ;
+BEGIN
+ DUT : encryptor
+ PORT MAP (
+ ciphertext => ciphertext ,
+ clock => clock ,
+ round_keyse => round_keyse ,
+ ready_e => ready_e ,
+ plaintext_e => plaintext_e ,
+ start_e => start_e ,
+ reset => reset ) ;
+
+process
+begin
+reset<='1';
+wait for 10 ns;
+start_e<='1';
+reset<='0';
+
+wait for 3000 ns;
+end process;
+
+
+process(clock)
+begin
+clock<= not clock after 10 ns;
+end process;
+
+process
+begin
+ wait for 30 ns;
+ plaintext_e<="0000000000000001";
+ wait for 20 ns;
+ plaintext_e<="0000000000000010";
+ wait for 20 ns;
+ plaintext_e<="0000000000000011";
+ wait for 20 ns;
+ plaintext_e<="0000000000000100";
+ wait for 3000 ns;
+end process;
+
+process
+begin
+ wait for 10 ns;
+ round_keyse<="0000000000000000";
+ wait for 3000 ns;
+end process;
+
+END ;
+
Index: trunk/encryption/encry.cr.mti
===================================================================
--- trunk/encryption/encry.cr.mti (nonexistent)
+++ trunk/encryption/encry.cr.mti (revision 4)
@@ -0,0 +1,10 @@
+{G:/crp project/encryption/encry.vhd} {1 {vcom -work work -2002 -explicit {G:/crp project/encryption/encry.vhd}
+Model Technology ModelSim PE vcom 5.8c Compiler 2004.03 Mar 25 2004
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package std_logic_unsigned
+-- Compiling entity encryptor
+-- Compiling architecture arch_encryptor of encryptor
+
+} {} {}}
Index: trunk/encryption/encry.vhd.bak
===================================================================
--- trunk/encryption/encry.vhd.bak (nonexistent)
+++ trunk/encryption/encry.vhd.bak (revision 4)
@@ -0,0 +1,451 @@
+----------------------------------------------------------------------------------
+-- Description:Implements the RC6 encryption algorithm.
+-- Everything based on a positive edge of clock and
+-- an asynchronous reset.
+--
+-- Module contains two finite state machines.
+--
+-- One fsm controls the calculation of the various
+-- rounds. Another fsm is responsible for outputting
+-- the ciphertext so the encryptor can accept plain
+-- text while cipher text is still in the process of
+-- going out.
+--
+-- We assume the number of rounds to be 20.
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- encryptor module declaration
+
+entity encryptor is
+
+port (
+ plaintext_e :in std_logic_vector(15 downto 0);-- 16 bit Plaintext output of decryptor
+ round_keyse :in std_logic_vector(15 downto 0);-- 16 bit roundkeys given to decryptor
+ start_e:in std_logic; --1 bit ready signal for encryptor
+ reset :in std_logic; --reset
+ clock :in std_logic ; --clock
+ ready_e :out std_logic; -- 1 bit ready output of decryptor
+ ciphertext: out std_logic_vector(15 downto 0)-- 16 bit ciphertext input to decrytpor which is output of encryptor
+
+ );
+
+end encryptor;
+
+
+Architecture arch_encryptor of encryptor is
+
+-------wallace tree
+
+component multiplier
+port( B :in std_logic_vector(15 downto 0);
+ Product :out std_logic_vector(15 downto 0)
+ );
+end component;
+
+-------- constant for key generation.
+
+constant p:std_logic_vector(15 downto 0):= "1011011111100001";------constant value p
+constant q:std_logic_vector(15 downto 0):= "1001111000110111";------constant value q
+
+type s_tp is array(43 downto 0) of std_logic_vector(15 downto 0);--array of 44 * 16
+signal s :s_tp;
+
+type l_tp is array(42 downto 0) of std_logic_vector(15 downto 0);--array of 43 *16
+signal l :l_tp;
+
+
+
+--------- constants for the plain text fsm
+
+constant out_idle:std_logic_vector(3 downto 0):= "0000";
+constant out_A :std_logic_vector(3 downto 0):= "0001";
+constant out_B :std_logic_vector(3 downto 0):= "0010";
+constant out_C :std_logic_vector(3 downto 0):= "0011";
+constant out_D :std_logic_vector(3 downto 0):= "0100";
+
+
+
+--------- signals needed for internal connections
+
+signal cleanup_A,cleanup_C ,start_d1,last_round: std_logic;
+signal next_state_out: std_logic_vector( 3 downto 0);
+signal state:std_logic_vector(5 downto 0); --state of primary fsm
+signal state_out:std_logic_vector(3 downto 0); -- state of plaintext fsm
+signal utemp1,ttemp1:std_logic_vector(15 downto 0);
+
+signal sig3,sig4:INTEGER RANGE 0 TO 15;
+
+signal A_final,B_final,C_final,D_final:std_logic_vector(15 downto 0);
+signal product1,product2 : std_logic_vector(15 downto 0);
+
+begin
+
+ sig3<=conv_integer(unsigned(utemp1(3 downto 0)));
+ sig4<=conv_integer(unsigned(ttemp1(3 downto 0)));
+ --------key generation operation------
+
+ s(0) <= P ; -- initialize constant array
+ l(0)<=(round_keyse +s(0));
+ s(1)<=(l(0)+ s(0)+ q);
+ l(1)<=( l(0)+s(1));
+ s(2)<=(l(1)+ s(1)+ q);
+ l(2)<=( l(1)+s(2));
+ s(3)<=(l(2)+ s(2)+ q);
+ l(3)<=( l(2)+s(3));
+ s(4)<=(l(3)+ s(3)+ q);
+ l(4)<=( l(3)+s(4));
+ s(5)<=(l(4)+ s(4)+ q);
+ l(5)<=( l(4)+s(5));
+ s(6)<=(l(5)+ s(5)+ q);
+ l(6)<=( l(5)+s(6));
+ s(7)<=(l(6)+ s(6)+ q);
+ l(7)<=( l(6)+s(7));
+ s(8)<=(l(7)+ s(7)+ q);
+ l(8)<=( l(7)+s(8));
+ s(9)<=(l(8)+s(8)+ q);
+ l(9)<=( l(8)+s(9));
+ s(10)<=(l(9)+s(9)+ q);
+ l(10)<=( l(9)+s(10 ));
+ s(11)<=(l(10)+s(10)+ q);
+ l(11)<=( l(10)+s(11));
+ s(12)<=(l(11)+ s(11)+ q);
+ l(12)<=( l(11)+s(12));
+ s(13)<=(l(12)+s(12)+ q);
+ l(13)<=( l(12)+s(13));
+ s(14)<=(l(13)+ s(13)+ q);
+ l(14)<=( l(13)+s(14));
+ s(15)<=(l(14)+ s(14)+ q);
+ l(15)<=( l(14)+s(15));
+ s(16)<=(l(15)+ s(15)+ q);
+ l(16)<=( l(15)+s(16));
+ s(17)<=(l(16)+ s(16)+ q);
+ l(17)<=( l(16)+s(17));
+ s(18)<=(l(17)+ s(17)+ q);
+ l(18)<=( l(17)+s(18));
+ s(19)<=(l(18)+ s(18)+ q);
+ l(19)<=( l(18)+s(19));
+ s(20)<=(l(19)+ s(19)+ q);
+ l(20)<=( l(19)+s(20));
+ s(21)<=(l(20)+ s(20)+ q);
+ l(21)<=( l(20)+s(21));
+ s(22)<=(l(21)+ s(21)+ q);
+ l(22)<=( l(21)+s(22));
+ s(23)<=(l(22)+ s(22)+ q);
+ l(23)<=( l(22)+s(23));
+ s(24)<=(l(23)+ s(23)+ q);
+ l(24)<=( l(23)+s(24));
+ s(25)<=(l(24)+ s(24)+ q);
+ l(25)<=( l(24)+s(25));
+ s(26)<=(l(25)+ s(25)+ q);
+ l(26)<=( l(25)+s(26));
+ s(27)<=(l(26)+ s(26)+ q);
+ l(27)<=( l(26)+s(27));
+ s(28)<=(l(27)+ s(27)+ q);
+ l(28)<=( l(27)+s(28));
+ s(29)<=(l(28)+ s(28)+ q);
+ l(29)<=( l(23)+s(24));
+ s(30)<=(l(29)+ s(29)+ q);
+ l(30)<=( l(29)+s(30));
+ s(31)<=(l(30)+ s(30)+ q);
+ l(31)<=( l(30)+s(31));
+ s(32)<=(l(31)+ s(31)+ q);
+ l(32)<=( l(31)+s(32));
+ s(33)<=(l(32)+ s(32)+ q);
+ l(33)<=( l(32)+s(33));
+ s(34)<=(l(33)+ s(33)+ q);
+ l(34)<=( l(33)+s(34));
+ s(35)<=(l(34)+ s(34)+ q);
+ l(35)<=( l(34)+s(35));
+ s(36)<=(l(35)+ s(35)+ q);
+ l(36)<=( l(35)+s(36));
+ s(37)<=(l(36)+ s(36)+ q);
+ l(37)<=( l(36)+s(37));
+ s(38)<=(l(37)+ s(37)+ q);
+ l(38)<=( l(37)+s(38));
+ s(39)<=(l(38)+ s(38)+ q);
+ l(39)<=( l(33)+s(34));
+ s(40)<=(l(39)+ s(39)+ q);
+ l(40)<=( l(39)+s(40));
+ s(40)<=(l(39)+ s(39)+ q);
+ l(41)<=( l(40)+s(40));
+ s(41)<=(l(40)+ s(40)+ q);
+ l(42)<=( l(41)+s(41));
+ s(42)<=(l(41)+ s(41)+ q);
+ s(43)<=(l(42)+ s(42)+ q);
+--------fsm for input --------
+
+process(clock,reset,plaintext_e,sig3,sig4)
+
+-----internal variable declaration
+
+variable A,B,C,D,t_pre,u_pre:std_logic_vector(15 downto 0);
+
+VARIABLE t,u,A_temp2,C_temp2,A_temp1,C_temp1:std_logic_vector( 15 downto 0);
+variable tempA,tempB,tempC,tempD :std_logic_vector(15 downto 0);
+variable temp_AB,temp_BC,temp_CD,temp_DA :std_logic_vector(15 downto 0);
+variable cnt: std_logic_vector(6 downto 0):="0000000";
+
+begin
+
+
+
+
+
+ if (reset='1') then
+
+ state <= "000001"; -- reset state
+ ready_e <= '0';
+ cnt:=(others=>'0');
+ A := (others=>'0');
+ B := (others=>'0');
+ C := (others=>'0');
+ D := (others=>'0');
+ ready_e <= '0';
+
+ elsif(clock'event and clock='1') then
+
+ case state is --synopsys parallel_case
+ when"000001"=>
+
+ if (start_e = '0') then
+ state <= "000001";
+ else
+ state <= "000010";
+ ready_e <= '1';
+ end if;
+
+
+ when "000010"=>
+
+ state <= "000011";
+ A := plaintext_e;--read ciphertext into A
+ ready_e <= '0';
+
+ when "000011"=>
+
+ state <= "000100";
+ B := plaintext_e; -- read ciphertext into B
+ ready_e <= '0';
+
+
+ when "000100"=>
+
+ state <= "000101";
+ C := plaintext_e ; -- read ciphertext - into C
+ B := B+ s(0) ;-- Use round keys to calculate new value of B
+ ready_e<= '0';
+
+
+ when "000101"=>
+
+ state <= "000110";
+ D := plaintext_e;--assign ciphertext to D
+ ready_e <= '0';
+
+
+ when "000110"=> -- begin calculation of plaintext loop from r downto 1
+
+ state<= "000111" ;
+
+ D := D + s(1); -- Use round keys to calculate new value of D
+
+
+ ready_e <='0';
+
+ when "000111" =>
+
+ STATE <="001000";
+
+ --t= (B * (2B+1))
+
+ t_pre := product1;
+
+
+ --t= (D * (2D+1))
+
+ u_pre := product2;
+
+ t:= t_pre(11 downto 0)& t_pre(15 downto 12);
+
+ ttemp1<=t;
+ --t= (B * (2B+1)) <<<4
+
+ u:= u_pre(11 downto 0)& u_pre(15 downto 12);
+
+ utemp1<=u;
+ --u= (D * (2D+1)) <<<4
+
+ A_temp1 := (A xor t);
+ C_temp1 := (C xor u);
+
+
+
+ when "001000" =>
+
+ state <="001001" ;
+
+
+
+
+
+ A_temp2:=A_temp1(15-sig3 downto 0)& A_temp1(15 downto 15-sig3+1);
+ ---rotate (A xor t) << u
+
+ C_temp2:=C_temp1(15-sig4 downto 0)& C_temp1(15 downto 15-sig4+1);
+ ---rotate (c xor u) << t
+
+
+ for i in 1 to 20 loop
+ A := (A_temp2 + s(2*i));
+ C := (C_temp2 + s(2*i+1));
+ end loop;
+
+
+ when "001001"=>
+ state <="001010";
+ -------swap operation---------
+ TEMPA:=A;
+ TEMPB:=B;
+ TEMPC:=C;
+ TEMPD:=D;
+
+ temp_AB:= tempA xor tempB;
+ A:= temp_AB xor tempA;
+
+ temp_BC:= tempB xor tempC;
+ B:= temp_BC xor tempB;
+
+ temp_CD:= tempC xor tempD;
+ C:= temp_CD xor tempC;
+
+ temp_DA:= tempD xor tempA;
+ D:= temp_DA xor tempD;
+
+ ready_e <= '0';
+
+ WHEN "001010" =>
+ ------start counter------
+ if(cnt<19)then
+ cnt:=cnt+1 ;
+ state <="000111";
+ else
+ state<="001011";
+ cnt:="0000000" ;
+ last_round <='1';
+ end if;
+
+
+
+ when "001011" =>
+
+ state <= "001100";
+ if (last_round ='1') then
+ -- calculate last A value
+ cleanup_A <= '1';
+ -- calculate last C value
+ cleanup_C <= '1';
+ else
+ cleanup_A <= '0';
+ cleanup_C <= '0';
+ end if;
+
+ when "001100" =>
+
+ state <= "000001";
+
+
+ --rounds are over
+ --now do the cleanup
+ if (cleanup_A='1') then
+ A_final <= A + s(42); --A_temp2 + round_keys_e_saved;
+ B_final <= B;--B_temp2;
+ D_final <= D;--D_temp2;
+ else
+ A_final <= A_final;
+ B_final <= B_final;
+ D_final <= D_final;
+ end if;
+
+ if (cleanup_C='1') then
+ C_final <= C + s(43);
+ start_d1 <= '1';
+ else
+ C_final <= C_final;
+ start_d1 <= '0';
+ end if;
+
+ when others =>
+ state <="000001" ;
+
+ end case;
+end if;
+end process;
+
+
+
+-- current state logic for output FSM
+process(clock,reset )
+begin
+ -- if reset stay idle
+ -- else output based on
+ --state
+ if (reset='1') then
+ state_out <= out_idle;
+ elsif(clock'event and clock='1') then
+ state_out <= next_state_out;
+ end if;
+end process;
+
+
+-- next state, output logic for output FSM
+process(state_out,start_d1,A_final,B_final,C_final,D_final)
+begin
+ case state_out is --synopsys parallel_case
+ when out_idle=>
+
+ -- wait for start_d
+ if (start_d1='1') then
+ next_state_out <= out_A;
+ else
+ next_state_out <= out_idle;
+ ciphertext <= (others=>'0');
+ end if;
+ when out_A=>
+
+ next_state_out <= out_B;
+ -- output A
+ ciphertext <= A_final;----------ouput cipher text 1
+
+ when out_B=>
+
+ next_state_out <= out_C;
+ -- output B
+ ciphertext <= B_final;----------ouput cipher text 2
+
+ when out_C=>
+
+ next_state_out <= out_D;
+ -- output C
+ ciphertext <= C_final;----------ouput cipher text 3
+
+ when out_D=>
+
+ next_state_out <= out_idle;
+ -- output D
+ ciphertext <= D_final;----------ouput cipher text 4
+
+ when others=>
+
+ next_state_out <= out_idle;
+ ciphertext <= (others=>'0');
+
+ end case;
+
+-----------------------complete output come after 93 clock---------------------
+
+end process;
+end arch_encryptor ;
Index: trunk/encryption/carrysave_adder.vhd
===================================================================
--- trunk/encryption/carrysave_adder.vhd (nonexistent)
+++ trunk/encryption/carrysave_adder.vhd (revision 4)
@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:10:53 10/09/2007
+-- Design Name:
+-- Module Name: carrysave_adder - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+
+entity carrysave_adder is
+port (p1,p2,p3,p4,p5,p6,p7,p8,p9 :in std_logic_vector ( 15 downto 0);
+ s1 : out std_logic_vector (15 downto 0);
+ c1 :out std_logic_vector (15 downto 0));
+
+
+end carrysave_adder;
+
+architecture Behavioral of carrysave_adder is
+
+
+ component full_adder
+ port (a,b,c :in std_logic_vector(15 downto 0) ;
+ sf,cf :out std_logic_vector(15 downto 0) );
+ end component;
+
+signal su1,ca1 :std_logic_vector (15 downto 0);
+signal su2,ca2 :std_logic_vector (15 downto 0);
+signal su3,ca3 :std_logic_vector (15 downto 0);
+signal su4,ca4 :std_logic_vector (15 downto 0);
+signal su5,ca5 :std_logic_vector (15 downto 0);
+signal su6,ca6 :std_logic_vector (15 downto 0);
+
+
+begin
+ fa0 : full_adder port map(p1,p2,p3,su1,ca1);
+ fa1 : full_adder port map(p4,p5,p6,su2,ca2);
+ fa2 : full_adder port map(p7,p8,p9,su3,ca3);
+ fa3 : full_adder port map(ca1,su1,su2,su4,ca4);
+ fa4 : full_adder port map(ca3,su3,ca2,su5,ca5);
+ fa5 : full_adder port map(ca4,su4,su5,su6,ca6);
+ fa6 : full_adder port map(ca6,su6,ca5,s1,c1);
+
+
+
+
+
+end Behavioral;
+