OpenCores
URL https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk

Subversion Repositories debouncer_vhdl

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /debouncer_vhdl/trunk/bench
    from Rev 7 to Rev 8
    ↔ Reverse comparison
  •

Rev 7 → Rev 8

/debounce_atlys_top_bit.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/par_usage_statistics.html
5,16 → 5,16
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>180</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>180</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>151</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>6.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>7.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>8.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>20.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.3</xtag-par-property-value></TD></TR>
/debounce_vhdl_bench.gise
104,7 → 104,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1313109035" xil_pn:in_ck="-726592440621834462" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-3901394755573216894" xil_pn:start_ts="1313109027">
<transform xil_pn:end_ts="1313461503" xil_pn:in_ck="-726592440621834462" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-3901394755573216894" xil_pn:start_ts="1313461494">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
126,7 → 126,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1313109087" xil_pn:in_ck="1959554578214568806" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7550009954124855948" xil_pn:start_ts="1313109084">
<transform xil_pn:end_ts="1313461517" xil_pn:in_ck="1959554578214568806" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7550009954124855948" xil_pn:start_ts="1313461512">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
135,11 → 135,9
<outfile xil_pn:name="debounce_atlys_top.ngd"/>
<outfile xil_pn:name="debounce_atlys_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1313109105" xil_pn:in_ck="1959554578214568807" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1658770934691434356" xil_pn:start_ts="1313109087">
<transform xil_pn:end_ts="1313461537" xil_pn:in_ck="1959554578214568807" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1658770934691434356" xil_pn:start_ts="1313461517">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="debounce_atlys_top.pcf"/>
<outfile xil_pn:name="debounce_atlys_top_map.map"/>
151,7 → 149,7
<outfile xil_pn:name="debounce_atlys_top_summary.xml"/>
<outfile xil_pn:name="debounce_atlys_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1313109122" xil_pn:in_ck="-6999964895445881344" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7846039340612803429" xil_pn:start_ts="1313109105">
<transform xil_pn:end_ts="1313461555" xil_pn:in_ck="-6999964895445881344" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7846039340612803429" xil_pn:start_ts="1313461537">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
166,7 → 164,7
<outfile xil_pn:name="debounce_atlys_top_pad.txt"/>
<outfile xil_pn:name="debounce_atlys_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1313109138" xil_pn:in_ck="-1280993813019831418" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="7135157351517842893" xil_pn:start_ts="1313109122">
<transform xil_pn:end_ts="1313461578" xil_pn:in_ck="-1280993813019831418" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="7135157351517842893" xil_pn:start_ts="1313461562">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
178,7 → 176,7
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1313109122" xil_pn:in_ck="1959554578214568675" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1313109115">
<transform xil_pn:end_ts="1313461555" xil_pn:in_ck="1959554578214568675" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1313461548">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
/debounce_atlys_top_map.map
11,7 → 11,7
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Aug 11 21:31:29 2011
Mapped Date : Mon Aug 15 23:25:20 2011
 
Running global optimization...
Mapping design into LUTs...
25,49 → 25,49
Total CPU time at the beginning of Placer: 7 secs
 
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:ed93dd56) REAL time: 10 secs
Phase 1.1 Initial Placement Analysis (Checksum:ed93dd56) REAL time: 11 secs
 
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:ed93dd56) REAL time: 10 secs
Phase 2.7 Design Feasibility Check (Checksum:ed93dd56) REAL time: 11 secs
 
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:ed93dd56) REAL time: 10 secs
Phase 3.31 Local Placement Optimization (Checksum:ed93dd56) REAL time: 11 secs
 
Phase 4.2 Initial Placement for Architecture Specific Features
 
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:feb5d5d6) REAL time: 12 secs
(Checksum:feb5d5d6) REAL time: 13 secs
 
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 12 secs
Phase 5.36 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 13 secs
 
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:feb5d5d6) REAL time: 12 secs
Phase 6.30 Global Clock Region Assignment (Checksum:feb5d5d6) REAL time: 13 secs
 
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 12 secs
Phase 7.3 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 13 secs
 
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 12 secs
Phase 8.5 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 13 secs
 
Phase 9.8 Global Placement
...
..
Phase 9.8 Global Placement (Checksum:6e34e131) REAL time: 12 secs
Phase 9.8 Global Placement (Checksum:6e34e131) REAL time: 13 secs
 
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:6e34e131) REAL time: 12 secs
Phase 10.5 Local Placement Optimization (Checksum:6e34e131) REAL time: 13 secs
 
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:ddc79b4e) REAL time: 12 secs
Phase 11.18 Placement Optimization (Checksum:ddc79b4e) REAL time: 13 secs
 
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:ddc79b4e) REAL time: 12 secs
Phase 12.5 Local Placement Optimization (Checksum:ddc79b4e) REAL time: 13 secs
 
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:d90e05db) REAL time: 12 secs
Phase 13.34 Placement Validation (Checksum:d90e05db) REAL time: 13 secs
 
Total REAL time to Placer completion: 12 secs
Total REAL time to Placer completion: 13 secs
Total CPU time to Placer completion: 10 secs
Running post-placement packing...
Writing output files...
143,8 → 143,8
 
Average Fanout of Non-Clock Nets: 2.37
 
Peak Memory Usage: 295 MB
Total REAL time to MAP completion: 14 secs
Peak Memory Usage: 298 MB
Total REAL time to MAP completion: 15 secs
Total CPU time to MAP completion (all processors): 11 secs
 
Mapping completed.
/debounce_atlys_top.twr
89,7 → 89,7
---------------+---------------+---------+
 
 
Analysis completed Thu Aug 11 21:32:01 2011
Analysis completed Mon Aug 15 23:25:54 2011
--------------------------------------------------------------------------------
 
Trace Settings:
96,7 → 96,7
-------------------------
Trace Settings
 
Peak Memory Usage: 175 MB
Peak Memory Usage: 179 MB
 
 
 
/debounce_atlys_top.syr
4,13 → 4,13
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
Total CPU time to Xst completion: 0.18 secs
--> Parameter xsthdpdir set to xst
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
Total CPU time to Xst completion: 0.18 secs
--> Reading design: debounce_atlys_top.prj
 
118,7 → 118,7
Elaborating entity <debounce_atlys_top> (architecture <rtl>) from library <work>.
 
Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" Line 71: Net <dbg[15]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" Line 62: Net <dbg[15]> does not have a driver.
 
=========================================================================
* HDL Synthesis *
411,11 → 411,11
 
 
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.57 secs
Total CPU time to Xst completion: 4.40 secs
-->
 
Total memory usage is 185320 kilobytes
Total memory usage is 188424 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
/debounce_atlys_top.vhd
8,6 → 8,7
-- Target Devices: Spartan-6 LX45
-- Tool versions: ISE 13.1
-- Description:
--
-- This is a verification project for the Digilent Atlys board, to test the GRP_DEBOUNCE core.
-- It uses the board's 100MHz clock input, and clocks all sequential logic at this clock.
--
15,20 → 16,10
-- The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
-- with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
-- digital pod port.
-- If you want details of the testing circuit, send me an e-mail: jdoin@opencores.org
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/07/02 v0.01.0010 [JD] implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
-- 2011/07/03 v0.01.0020 [JD] added clock input, and a simple LED blinker for each LED.
-- 2011/07/03 v0.01.0030 [JD] added clear input, and instantiated a SPI_MASTER from my OpenCores project.
-- 2011/07/04 v0.01.0040 [JD] changed all clocks to clock enables, and use the 100MHz board gclk_i to clock all registers.
-- this change made the design go up to 288MHz, after synthesis.
-- 2011/07/07 v0.03.0050 [JD] implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
-- external monitoring pins to the VHDCI ports.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
-- 6.25MHz, 1MHz and 500kHz
-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
-- 2011/08/10 v1.01.0025 [JD] changed to test the grp_debouncer.vhd module alone.
-- 2011/08/11 v1.01.0026 [JD] reduced switch inputs to 7, to save digital pins to the strobe signal.
--
40,13 → 31,13
 
entity debounce_atlys_top is
Port (
gclk_i : in std_logic := 'X'; -- board clock input 100MHz
gclk_i : in std_logic := 'X'; -- board clock input 100MHz
--- input slide switches ---
sw_i : in std_logic_vector (6 downto 0); -- 7 input slide switches
sw_i : in std_logic_vector (6 downto 0); -- 7 input slide switches
--- output LEDs ----
led_o : out std_logic_vector (6 downto 0); -- 7 output leds
led_o : out std_logic_vector (6 downto 0); -- 7 output leds
--- debug outputs ---
dbg_o : out std_logic_vector (15 downto 0) -- 16 generic debug pins
dbg_o : out std_logic_vector (15 downto 0) -- 16 generic debug pins
);
end debounce_atlys_top;
 
78,10 → 69,10
Inst_sw_debouncer: entity work.grp_debouncer(rtl)
generic map (N => N, CNT_VAL => CNT_VAL)
port map(
clk_i => gclk_i, -- system clock
data_i => sw_i, -- noisy input data
data_o => sw_data, -- registered stable output data
strb_o => sw_new -- transition detection
clk_i => gclk_i, -- system clock
data_i => sw_i, -- noisy input data
data_o => sw_data, -- registered stable output data
strb_o => sw_new -- transition detection
);
 
--=============================================================================================
92,8 → 83,8
begin
-- transfer switch data when new switch is detected
if gclk_i'event and gclk_i = '1' then
if sw_new = '1' then -- clock enable
sw_reg <= sw_data; -- only provide local reset for the state registers
if sw_new = '1' then -- clock enable
sw_reg <= sw_data; -- only provide local reset for the state registers
end if;
end if;
end process dat_reg_proc;
102,7 → 93,7
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- LED register update
leds_reg_proc: leds_reg <= sw_reg; -- leds register is a copy of the updated switch register
leds_reg_proc: leds_reg <= sw_reg; -- leds register is a copy of the updated switch register
 
-- update debug register
dbg_in_proc: dbg(6 downto 0) <= sw_i; -- lower debug port has direct switch connections
/debounce_atlys_top_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>debounce_atlys_top Project Status (08/11/2011 - 21:32:18)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>debounce_atlys_top Project Status (08/15/2011 - 23:26:18)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>debounce_vhdl_bench.xise</TD>
385,22 → 385,22
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:30:34 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/xst.xmsgs?&DataKey=Warning'>2 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:31:26 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:31:44 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (9 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:31:54 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:02 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/xst.xmsgs?&DataKey=Warning'>2 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:16 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:36 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (9 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:47 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:32:01 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:32:12 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:54 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:26:11 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Aug 11 21:31:43 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Aug 11 21:32:12 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Aug 11 21:32:18 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Aug 15 23:25:35 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon Aug 15 23:26:12 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon Aug 15 23:26:18 2011</TD></TR>
</TABLE>
 
 
<br><center><b>Date Generated:</b> 08/11/2011 - 21:32:18</center>
<br><center><b>Date Generated:</b> 08/15/2011 - 23:26:18</center>
</BODY></HTML>
/debounce_atlys_top.par
1,7 → 1,7
Release 13.1 par O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
 
DEVELOP-W7:: Thu Aug 11 21:31:46 2011
DEVELOP-W7:: Mon Aug 15 23:25:39 2011
 
par -w -intstyle ise -ol high -xe n -mt 4 debounce_atlys_top_map.ncd
debounce_atlys_top.ncd debounce_atlys_top.pcf
160,9 → 160,9
All signals are completely routed.
 
Total REAL time to PAR completion: 8 secs
Total CPU time to PAR completion: 8 secs
Total CPU time to PAR completion: 7 secs
 
Peak Memory Usage: 259 MB
Peak Memory Usage: 261 MB
 
Placer: Placement generated during map.
Routing: Completed - No errors found.
/debounce_atlys_top_map.mrp
11,7 → 11,7
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Aug 11 21:31:29 2011
Mapped Date : Mon Aug 15 23:25:20 2011
 
Design Summary
--------------
82,8 → 82,8
 
Average Fanout of Non-Clock Nets: 2.37
 
Peak Memory Usage: 295 MB
Total REAL time to MAP completion: 14 secs
Peak Memory Usage: 298 MB
Total REAL time to MAP completion: 15 secs
Total CPU time to MAP completion (all processors): 11 secs
 
Table of Contents

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.