URL
https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk
Subversion Repositories debouncer_vhdl
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- This comparison shows the changes necessary to convert path
/debouncer_vhdl/trunk/rtl
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/readme.txt
17,7 → 17,6
--------------------------------------- |
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grp_debouncer.vhd switch debouncer model |
grp_debouncer_test.vhd testbench for simulating the switch debouncer model |
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The original development is done in Xilinx ISE 13.1, targeted to a Spartan-6 device. |
/grp_debouncer.vhd
40,21 → 40,23
-- | | | | |
-- | | \----------\ | |
-- | | N | | |
-- | \--------/-----------\ +----------------------+-----------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-------------)----------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ |
-- ------ ------ | ------ | N ____ \-----| \ |
-- | \----/----)) \ |AND |-----------[strb_o] |
-- | ))XOR |-------|___/ |
-- \--------------------------/----))___/ |
-- N |
-- | \--------/-----------\ +----------------------+---------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-----------)------------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ ______ |
-- ------ ------ | ------ | N ____ \---| \ | fd | |
-- | \---/---)) \ |AND |-----| |----[strb_o] |
-- | ))XOR |-----|___/ | | |
-- \-------------------------/---))___/ | | |
-- N | | |
-- |> | |
-- ------ |
-- |
-- |
-- PIPELINE LOGIC |
75,12 → 77,12
-- RESOURCES USED |
-- ============== |
-- |
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) registers. |
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) + 1 registers. |
-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2. |
-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r. |
-- |
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints. |
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clk_i. |
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clock. |
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools. |
-- |
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
110,6 → 112,7
-- |
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference. |
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45). |
-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
138,6 → 141,8
signal reg_A, reg_B : std_logic_vector (N-1 downto 0) := (others => '0'); -- debounce edge detectors |
signal reg_out : std_logic_vector (N-1 downto 0) := (others => '0'); -- registered output |
signal dat_strb : std_logic := '0'; -- data transfer strobe |
signal strb_reg : std_logic := '0'; -- registered strobe |
signal strb_next : std_logic := '0'; -- lookahead strobe |
signal dat_diff : std_logic := '0'; -- edge detector |
-- debounce counter |
signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter |
169,11 → 174,14
-- input pipeline logic |
pipeline_proc: process (clk_i) is |
begin |
-- edge detection pipeline |
if clk_i'event and clk_i = '1' then |
-- edge detection pipeline |
reg_A <= data_i; |
reg_B <= reg_A; |
-- new data strobe pipeline delay |
strb_reg <= strb_next; |
end if; |
-- output data pipeline |
if clk_i'event and clk_i = '1' then |
if dat_strb = '1' then |
reg_out <= reg_B; |
182,14 → 190,14
end process pipeline_proc; |
-- edge detector |
edge_detector_proc: dat_diff <= '1' when reg_A /= reg_B else '0'; |
-- lookahead new data strobe |
next_strobe_proc: strb_next <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0'; |
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--============================================================================================= |
-- OUTPUT LOGIC |
--============================================================================================= |
-- new data strobe detection |
strb_o_proc: strb_o <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0'; |
-- connect output ports |
data_o_proc: data_o <= reg_out; |
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strb_o_proc: strb_o <= strb_reg; |
end rtl; |
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