URL
https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk
Subversion Repositories debouncer_vhdl
Compare Revisions
- This comparison shows the changes necessary to convert path
/debouncer_vhdl
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/bench/debounce_atlys_test.vhd
21,9 → 21,8
COMPONENT debounce_atlys_top |
PORT( |
gclk_i : IN std_logic; |
sw_i : IN std_logic_vector(7 downto 0); |
led_o : OUT std_logic_vector(7 downto 0); |
strb_o : OUT std_logic; |
sw_i : IN std_logic_vector(6 downto 0); |
led_o : OUT std_logic_vector(6 downto 0); |
dbg_o : OUT std_logic_vector(15 downto 0) |
); |
END COMPONENT; |
34,13 → 33,13
--- clock signals --- |
signal sysclk : std_logic := '0'; -- 100MHz clock |
--- switch debouncer signals --- |
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- switch data |
signal sw_data : std_logic_vector (6 downto 0) := (others => '0'); -- switch data |
-- debug output signals |
signal leds : std_logic_vector (7 downto 0); -- board leds |
signal leds : std_logic_vector (6 downto 0); -- board leds |
signal dbg : std_logic_vector (15 downto 0); -- LA debug vector |
signal strobe : std_logic; |
signal sw_input : std_logic_vector (7 downto 0); -- raw switches |
signal sw_output : std_logic_vector (7 downto 0); -- debounced switches |
signal sw_input : std_logic_vector (6 downto 0); -- raw switches |
signal sw_output : std_logic_vector (6 downto 0); -- debounced switches |
begin |
|
--============================================================================================= |
48,8 → 47,8
--============================================================================================= |
-- debounce_atlys_top: |
-- receives the 100 MHz clock from the board clock oscillator |
-- receives the 8 slide switches and 5 pushbuttons as test stimuli |
-- connects to 8 board LEDs |
-- receives 7 slide switches as test stimuli |
-- connects to 7 board LEDs |
-- connects to 16 debug pins |
Inst_debounce_atlys_top: debounce_atlys_top |
PORT MAP( |
56,13 → 55,13
gclk_i => sysclk, -- connect board clock |
sw_i => sw_data, -- connect board switches |
led_o => leds, -- connect board leds |
strb_o => strobe, -- connect strobe debug |
dbg_o => dbg -- connect logic analyzer |
); |
|
-- debug signals mapped on dbg vector |
sw_input <= dbg(7 downto 0); |
sw_output <= dbg(15 downto 8); |
sw_input <= dbg(6 downto 0); |
sw_output <= dbg(13 downto 7); |
strobe <= dbg(14); |
|
--============================================================================================= |
-- CLOCK GENERATION |
81,34 → 80,45
tb : process |
begin |
wait for 100 ns; -- wait until global set/reset completes |
sw_data <= X"00"; |
sw_data <= B"000_0000"; |
wait for 1 us; |
|
-- change switches to 0x93, with bouncing |
sw_data <= X"81"; |
wait for 50 ns; |
sw_data <= X"80"; |
wait for 250 ns; |
sw_data <= X"91"; |
wait for 40 ns; |
sw_data <= X"81"; |
wait for 90 ns; |
sw_data <= X"93"; |
wait for 40 us; |
-- change switches to 0x71, with bouncing |
sw_data <= B"100_0001"; |
wait until strobe = '1'; |
wait until strobe = '0'; |
sw_data <= B"100_0000"; |
wait until strobe = '1'; |
wait until strobe = '0'; |
sw_data <= B"101_0001"; |
wait until strobe = '1'; |
wait until strobe = '0'; |
sw_data <= B"100_0001"; |
wait until strobe = '1'; |
wait until strobe = '0'; |
sw_data <= B"111_0001"; |
wait until strobe = '1'; |
wait until strobe = '0'; |
|
-- change switches to 0x3E, with bouncing |
sw_data <= X"97"; |
wait for 50 ns; |
sw_data <= X"16"; |
wait for 150 ns; |
sw_data <= X"3E"; |
wait for 300 ns; |
sw_data <= X"2C"; |
wait for 50 ns; |
sw_data <= X"3D"; |
wait for 400 ns; |
sw_data <= X"3E"; |
wait for 50 us; |
sw_data <= B"111_1001"; |
wait until strobe = '1'; |
wait until strobe = '0'; |
sw_data <= B"011_0001"; |
wait until strobe = '1'; |
wait until strobe = '0'; |
sw_data <= B"111_1101"; |
wait until strobe = '1'; |
wait until strobe = '0'; |
sw_data <= B"011_1011"; |
wait until strobe = '1'; |
wait until strobe = '0'; |
sw_data <= B"111_1100"; |
wait until strobe = '1'; |
wait until strobe = '0'; |
sw_data <= B"011_1110"; |
wait until strobe = '1'; |
wait until strobe = '0'; |
|
-- end simulation |
assert false report "End Simulation" severity failure; -- stop simulation |
/trunk/bench/fuseRelaunch.cmd
1,34 → 80,45
-intstyle "ise" -incremental -lib "secureip" -o "D:/Dropbox/VHDL_training/ISE_projects/debounce_vhdl_bench/testbench_isim_translate.exe" -prj "D:/Dropbox/VHDL_training/ISE_projects/debounce_vhdl_bench/testbench_translate.prj" "work.testbench" |
-intstyle "ise" -incremental -lib "secureip" -o "D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench/testbench_isim_beh.exe" -prj "D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench/testbench_beh.prj" "work.testbench" |
/trunk/bench/debounce_vhdl_bench.gise
68,14 → 68,84
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="debounce_atlys_top_summary.xml"/> |
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="debounce_atlys_top_usage.xml"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="debounce_atlys_top_xst.xrpt"/> |
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="grp_debouncer_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testbench_isim_beh.wdb"/> |
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/> |
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/> |
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/> |
</files> |
|
<transforms xmlns="http://www.xilinx.com/XMLSchema"> |
<transform xil_pn:end_ts="1316453641" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1316453641"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1316454957" xil_pn:in_ck="-8933073213822230910" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1316454957"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="debounce_atlys_test.vhd"/> |
<outfile xil_pn:name="debounce_atlys_top.vhd"/> |
<outfile xil_pn:name="grp_debouncer.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1316453701" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="4434870115928851094" xil_pn:start_ts="1316453701"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1316453701" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1902104842233773292" xil_pn:start_ts="1316453701"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1316453641" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="1757374532715662761" xil_pn:start_ts="1316453641"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1316454957" xil_pn:in_ck="-8933073213822230910" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1316454957"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="debounce_atlys_test.vhd"/> |
<outfile xil_pn:name="debounce_atlys_top.vhd"/> |
<outfile xil_pn:name="grp_debouncer.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1316454958" xil_pn:in_ck="-8933073213822230910" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="1459423336703152140" xil_pn:start_ts="1316454957"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForProperties"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="InputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="testbench_beh.prj"/> |
<outfile xil_pn:name="testbench_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1316454959" xil_pn:in_ck="-5244192273868876163" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5414671575160791934" xil_pn:start_ts="1316454958"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForProperties"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="testbench_isim_beh.wdb"/> |
</transform> |
<transform xil_pn:end_ts="1313030830" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1313030830"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
/trunk/bench/grp_debouncer.vhd
113,6 → 113,7
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference. |
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45). |
-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output. |
-- 2011/09/19 v1.01.0030 [JD] changed range for internal counter (cnt_reg, cnt_next) to avoid adder flipover (Altera/ModelSim). |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
145,8 → 146,8
signal strb_next : std_logic := '0'; -- lookahead strobe |
signal dat_diff : std_logic := '0'; -- edge detector |
-- debounce counter |
signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter |
signal cnt_next : integer range CNT_VAL downto 0 := 0; -- combinatorial signal |
signal cnt_reg : integer range CNT_VAL + 1 downto 0 := 0; -- debounce period counter |
signal cnt_next : integer range CNT_VAL + 1 downto 0 := 0; -- combinatorial signal |
begin |
|
--============================================================================================= |
/trunk/bench/debounce_atlys_top_summary.html
38,7 → 38,7
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> |
<A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
193,7 → 193,7
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> |
<TD ALIGN=RIGHT>31</TD> |
<TD ALIGN=RIGHT>218</TD> |
<TD ALIGN=RIGHT>14%</TD> |
359,18 → 359,18
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD> |
<TD>0 (Setup: 0, Hold: 0)</TD> |
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD> |
<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD> |
<TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD> |
All Signals Completely Routed</TD> |
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD> |
<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD> |
<TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD> |
<TD> |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> |
<A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> |
<TD BGCOLOR='#FFFF99'><B> </B></TD> |
<TD COLSPAN='2'> </TD> |
</TABLE> |
381,20 → 381,21
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:02 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:02 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:36 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:47 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:36 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:47 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:54 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:54 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Aug 15 23:25:35 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>seg 19. set 14:56:36 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>qui 11. ago 21:31:43 2011</TD></TR> |
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 08/30/2011 - 11:26:47</center> |
<br><center><b>Date Generated:</b> 09/19/2011 - 15:37:38</center> |
</BODY></HTML> |
/trunk/rtl/grp_debouncer.vhd
113,6 → 113,7
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference. |
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45). |
-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output. |
-- 2011/09/19 v1.01.0030 [JD] changed range for internal counter (cnt_reg, cnt_next) to avoid adder flipover (Altera/ModelSim). |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
145,8 → 146,8
signal strb_next : std_logic := '0'; -- lookahead strobe |
signal dat_diff : std_logic := '0'; -- edge detector |
-- debounce counter |
signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter |
signal cnt_next : integer range CNT_VAL downto 0 := 0; -- combinatorial signal |
signal cnt_reg : integer range CNT_VAL + 1 downto 0 := 0; -- debounce period counter |
signal cnt_next : integer range CNT_VAL + 1 downto 0 := 0; -- combinatorial signal |
begin |
|
--============================================================================================= |