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/tb_des_loop.vhd
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-- Company: |
-- Engineer: |
-- |
-- Create Date: 11:47:33 02/21/2013 |
-- Design Name: |
-- Module Name: C:/Users/vmr/Desktop/crypto_ng/des/dram/desl/tb_des_loop.vhd |
-- Project Name: desl |
-- Target Device: |
-- Tool versions: |
-- Description: |
-- |
-- VHDL Test Bench Created by ISE for module: des_loop |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
-- Notes: |
-- This testbench has been automatically generated using types std_logic and |
-- std_logic_vector for the ports of the unit under test. Xilinx recommends |
-- that these types always be used for the top-level I/O of a design in order |
-- to guarantee that the testbench will bind correctly to the post-implementation |
-- simulation model. |
-------------------------------------------------------------------------------- |
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-- Copyright (c) 2013 Antonio de la Piedra |
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-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
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LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
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-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--USE ieee.numeric_std.ALL; |
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ENTITY tb_des_loop IS |
ENTITY tb_des_loop IS |
END tb_des_loop; |
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ARCHITECTURE behavior OF tb_des_loop IS |