OpenCores
URL https://opencores.org/ocsvn/descore/descore/trunk

Subversion Repositories descore

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  • This comparison shows the changes necessary to convert path 
    /descore
    from Rev 1 to Rev 2
    ↔ Reverse comparison
  •

Rev 1 → Rev 2

/trunk/rtl/s_box_v_1.coe
0,0 → 1,66
memory_initialization_radix=10;
memory_initialization_vector=
14,
0,
4,
15,
13,
7,
1,
4,
2,
14,
15,
2,
11,
13,
8,
1,
3,
10,
10,
6,
6,
12,
12,
11,
5,
9,
9,
5,
0,
3,
7,
8,
4,
15,
1,
12,
14,
8,
8,
2,
13,
4,
6,
9,
2,
1,
11,
7,
15,
5,
12,
11,
9,
3,
7,
14,
3,
10,
10,
0,
5,
6,
0,
13;
/trunk/rtl/key_schedule.vhd
0,0 → 1,126
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:16 02/20/2013
-- Design Name:
-- Module Name: key_schedule - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity key_schedule is
port(clk : in std_logic;
rst : in std_logic;
mode : in std_logic; -- 0 encrypt, 1 decrypt
key : in std_logic_vector(63 downto 0);
key_out : out std_logic_vector(47 downto 0));
end key_schedule;
 
architecture Behavioral of key_schedule is
signal init_key_s : std_logic_vector(55 downto 0);
signal c_0_s : std_logic_vector(27 downto 0);
signal d_0_s : std_logic_vector(27 downto 0);
signal shift_s : std_logic_vector(15 downto 0);
signal key_pre_s : std_logic_vector(55 downto 0);
signal key_pre_delay_s : std_logic_vector(55 downto 0);
begin
 
pr_seq: process(clk, rst, key, shift_s(15), mode)
begin
if rst = '1' then
c_0_s <= key(7) & key (15) & key (23) & key (31) & key (39) & key (47) & key (55) &
key (63) & key(6) & key (14) & key (22) & key (30) & key (38) & key (46) &
key (54) & key (62) & key(5) & key (13) & key (21) & key (29) & key (37) &
key (45) & key (53) & key (61) & key(4) & key (12) & key (20) & key (28);
 
d_0_s <= key (1) & key (9) & key (17) & key (25) & key(33) & key (41) & key (49) &
key (57) & key (2) & key (10) & key (18) & key (26) & key(34) & key (42) &
key (50) & key (58) & key (3) & key (11) & key (19) & key (27) & key(35) &
key (43) & key (51) & key (59) & key (36) & key (44) & key (52) & key (60);
elsif rising_edge(clk) then
if shift_s(15) = '0' then
if mode = '0' then
c_0_s <= c_0_s(26 downto 0) & c_0_s(27);
d_0_s <= d_0_s(26 downto 0) & d_0_s(27);
else
c_0_s <= c_0_s(0) & c_0_s(27 downto 1);
d_0_s <= d_0_s(0) & d_0_s(27 downto 1);
end if;
else
if mode = '0' then
c_0_s <= c_0_s(25 downto 0) & c_0_s(27 downto 26);
d_0_s <= d_0_s(25 downto 0) & d_0_s(27 downto 26);
else
c_0_s <= c_0_s(1 downto 0) & c_0_s(27 downto 2);
d_0_s <= d_0_s(1 downto 0) & d_0_s(27 downto 2);
end if;
end if;
end if;
end process;
 
pr_shr: process(clk, rst, mode)
begin
if rst = '1' then
if mode = '0' then
shift_s <= "0011111101111110";
else
shift_s <= "0111111011111100";
end if;
elsif rising_edge(clk) then
shift_s <= shift_s(14 downto 0) & shift_s(15);
end if;
end process;
 
-- XXX Podemos meter aqui un FF para retrasar la salida n ciclos.
 
key_pre_s <= c_0_s & d_0_s;
pr_delay: process(clk, mode, key_pre_s)
begin
if rising_edge(clk) then
if mode = '1' then
key_pre_delay_s <= key_pre_s;
end if;
end if;
end process;
 
key_out <= (key_pre_s (42) & key_pre_s (39) & key_pre_s (45) & key_pre_s (32) & key_pre_s (55) & key_pre_s (51) & key_pre_s (53) & key_pre_s (28) &
key_pre_s (41) & key_pre_s (50) & key_pre_s (35) & key_pre_s (46) & key_pre_s (33) & key_pre_s (37) & key_pre_s (44) & key_pre_s (52) &
key_pre_s (30) & key_pre_s (48) & key_pre_s (40) & key_pre_s (49) & key_pre_s (29) & key_pre_s (36) & key_pre_s (43) & key_pre_s (54) &
key_pre_s (15) & key_pre_s (4) & key_pre_s (25) & key_pre_s (19) & key_pre_s (9) & key_pre_s (1) & key_pre_s (26) & key_pre_s (16) &
key_pre_s (5) & key_pre_s (11) & key_pre_s (23) & key_pre_s (8) & key_pre_s (12) & key_pre_s (7) & key_pre_s (17) & key_pre_s (0) &
key_pre_s (22) & key_pre_s (3) & key_pre_s (10) & key_pre_s (14) & key_pre_s (6) & key_pre_s (20) & key_pre_s (27) & key_pre_s (24))
when mode = '0' else
(key_pre_delay_s (42) & key_pre_delay_s (39) & key_pre_delay_s (45) & key_pre_delay_s (32) & key_pre_delay_s (55) & key_pre_delay_s (51) & key_pre_delay_s (53) & key_pre_delay_s (28) &
key_pre_delay_s (41) & key_pre_delay_s (50) & key_pre_delay_s (35) & key_pre_delay_s (46) & key_pre_delay_s (33) & key_pre_delay_s (37) & key_pre_delay_s (44) & key_pre_delay_s (52) &
key_pre_delay_s (30) & key_pre_delay_s (48) & key_pre_delay_s (40) & key_pre_delay_s (49) & key_pre_delay_s (29) & key_pre_delay_s (36) & key_pre_delay_s (43) & key_pre_delay_s (54) &
key_pre_delay_s (15) & key_pre_delay_s (4) & key_pre_delay_s (25) & key_pre_delay_s (19) & key_pre_delay_s (9) & key_pre_delay_s (1) & key_pre_delay_s (26) & key_pre_delay_s (16) &
key_pre_delay_s (5) & key_pre_delay_s (11) & key_pre_delay_s (23) & key_pre_delay_s (8) & key_pre_delay_s (12) & key_pre_delay_s (7) & key_pre_delay_s (17) & key_pre_delay_s (0) &
key_pre_delay_s (22) & key_pre_delay_s (3) & key_pre_delay_s (10) & key_pre_delay_s (14) & key_pre_delay_s (6) & key_pre_delay_s (20) & key_pre_delay_s (27) & key_pre_delay_s (24));
 
end Behavioral;
 
/trunk/rtl/des_loop.vhd
0,0 → 1,184
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:30:59 02/20/2013
-- Design Name:
-- Module Name: des - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity des_loop is
port(clk : in std_logic;
rst : in std_logic;
mode : in std_logic; -- 0 encrypt, 1 decrypt
key_in : in std_logic_vector(63 downto 0);
blk_in : in std_logic_vector(63 downto 0);
blk_out : out std_logic_vector(63 downto 0));
end des_loop;
 
architecture Behavioral of des_loop is
 
signal after_ip_s : std_logic_vector(63 downto 0);
signal after_ip_minus_one_s : std_logic_vector(63 downto 0);
signal after_f_s : std_logic_vector(31 downto 0);
signal final_s : std_logic_vector(63 downto 0);
 
component des_round is
port(clk : in std_logic;
l_0 : in std_logic_vector(31 downto 0);
r_0 : in std_logic_vector(31 downto 0);
k_i : in std_logic_vector(47 downto 0);
l_1 : out std_logic_vector(31 downto 0);
r_1 : out std_logic_vector(31 downto 0));
end component;
 
component key_schedule is
port(clk : in std_logic;
rst : in std_logic;
mode : in std_logic; -- 0 encrypt, 1 decrypt
key : in std_logic_vector(63 downto 0);
key_out : out std_logic_vector(47 downto 0));
end component;
 
signal key_s : std_logic_vector(47 downto 0);
 
signal l_0_s : std_logic_vector(31 downto 0);
signal l_1_s : std_logic_vector(31 downto 0);
signal l_2_s : std_logic_vector(31 downto 0);
signal l_3_s : std_logic_vector(31 downto 0);
signal l_4_s : std_logic_vector(31 downto 0);
signal l_5_s : std_logic_vector(31 downto 0);
signal l_6_s : std_logic_vector(31 downto 0);
signal l_7_s : std_logic_vector(31 downto 0);
signal l_8_s : std_logic_vector(31 downto 0);
signal l_9_s : std_logic_vector(31 downto 0);
signal l_10_s : std_logic_vector(31 downto 0);
signal l_11_s : std_logic_vector(31 downto 0);
signal l_12_s : std_logic_vector(31 downto 0);
signal l_13_s : std_logic_vector(31 downto 0);
signal l_14_s : std_logic_vector(31 downto 0);
signal l_15_s : std_logic_vector(31 downto 0);
signal l_16_s : std_logic_vector(31 downto 0);
 
signal r_0_s : std_logic_vector(31 downto 0);
signal r_1_s : std_logic_vector(31 downto 0);
signal r_2_s : std_logic_vector(31 downto 0);
signal r_3_s : std_logic_vector(31 downto 0);
signal r_4_s : std_logic_vector(31 downto 0);
signal r_5_s : std_logic_vector(31 downto 0);
signal r_6_s : std_logic_vector(31 downto 0);
signal r_7_s : std_logic_vector(31 downto 0);
signal r_8_s : std_logic_vector(31 downto 0);
signal r_9_s : std_logic_vector(31 downto 0);
signal r_10_s : std_logic_vector(31 downto 0);
signal r_11_s : std_logic_vector(31 downto 0);
signal r_12_s : std_logic_vector(31 downto 0);
signal r_13_s : std_logic_vector(31 downto 0);
signal r_14_s : std_logic_vector(31 downto 0);
signal r_15_s : std_logic_vector(31 downto 0);
signal r_16_s : std_logic_vector(31 downto 0);
signal k_0_s : std_logic_vector(47 downto 0);
signal k_1_s : std_logic_vector(47 downto 0);
signal k_2_s : std_logic_vector(47 downto 0);
signal k_3_s : std_logic_vector(47 downto 0);
signal k_4_s : std_logic_vector(47 downto 0);
signal k_5_s : std_logic_vector(47 downto 0);
signal k_6_s : std_logic_vector(47 downto 0);
signal k_7_s : std_logic_vector(47 downto 0);
signal k_8_s : std_logic_vector(47 downto 0);
signal k_9_s : std_logic_vector(47 downto 0);
signal k_10_s : std_logic_vector(47 downto 0);
signal k_11_s : std_logic_vector(47 downto 0);
signal k_12_s : std_logic_vector(47 downto 0);
signal k_13_s : std_logic_vector(47 downto 0);
signal k_14_s : std_logic_vector(47 downto 0);
signal k_15_s : std_logic_vector(47 downto 0);
signal rst_s : std_logic;
begin
 
pr_rst_delay : process(clk, rst)
begin
if rising_edge(clk) then
rst_s <= rst;
end if;
end process;
 
-- k_0_s <= "101000001001001011000010000010101011000101000000";
-- k_1_s <= "101000000001001001010010010011000000000010101011";
-- k_2_s <= "001001000101101001010000000001100101100001001001";
-- k_3_s <= "000001100111000101010000000000101001000101110000";
-- k_4_s <= "000011100100010101010001100000011000110100100000";
-- k_5_s <= "010011110100000100001001010010000000111000010000";
-- k_6_s <= "000010111000000110001001010110010100000000011100";
-- k_7_s <= "000110010000100010001011000000010101000010001000";
-- k_8_s <= "000110010000101010001000000110000010111010010000";
-- k_9_s <= "000100000011100010001100001110010100000000010001";
-- k_10_s <= "000100000010110001000100000000110110000000000010";
-- k_11_s <= "010000000110110000100100101001000010000100000100";
-- k_12_s <= "110000001010010100100100101000000000001011000110";
-- k_13_s <= "110000001000011000100011010101001000001010000011";
-- k_14_s <= "111000011001001000100010000101100000010001001001";
-- k_15_s <= "101000001001001000101010011000000001010010000110";
-- IP
 
pr_seq: process(clk, rst_s, blk_in)
begin
if rst_s = '1' then
l_0_s <= blk_in(6) & blk_in(14) & blk_in(22) & blk_in(30) & blk_in(38) & blk_in(46) & blk_in(54) & blk_in(62) &
blk_in(4) & blk_in(12) & blk_in(20) & blk_in(28) & blk_in(36) & blk_in(44) & blk_in(52) & blk_in(60) &
blk_in(2) & blk_in(10) & blk_in(18) & blk_in(26) & blk_in(34) & blk_in(42) & blk_in(50) & blk_in(58) &
blk_in(0) & blk_in(8) & blk_in(16) & blk_in(24) & blk_in(32) & blk_in(40) & blk_in(48) & blk_in(56);
r_0_s <= blk_in(7) & blk_in(15) & blk_in(23) & blk_in(31) & blk_in(39) & blk_in(47) & blk_in(55) & blk_in(63) &
blk_in(5) & blk_in(13) & blk_in(21) & blk_in(29) & blk_in(37) & blk_in(45) & blk_in(53) & blk_in(61) &
blk_in(3) & blk_in(11) & blk_in(19) & blk_in(27) & blk_in(35) & blk_in(43) & blk_in(51) & blk_in(59) &
blk_in(1) & blk_in(9) & blk_in(17) & blk_in(25) & blk_in(33) & blk_in(41) & blk_in(49) & blk_in(57);
elsif rising_edge(clk) then
l_0_s <= l_1_s;
r_0_s <= r_1_s;
end if;
end process;
 
DES_ROUND_0 : des_round port map (clk, l_0_s, r_0_s, k_0_s, l_1_s, r_1_s);
 
final_s <= r_1_s & l_1_s;
 
blk_out <= final_s(24) & final_s(56) & final_s(16) & final_s(48) & final_s(8) & final_s(40) & final_s(0) & final_s(32) &
final_s(25) & final_s(57) & final_s(17) & final_s(49) & final_s(9) & final_s(41) & final_s(1) & final_s(33) &
final_s(26) & final_s(58) & final_s(18) & final_s(50) & final_s(10) & final_s(42) & final_s(2) & final_s(34) &
final_s(27) & final_s(59) & final_s(19) & final_s(51) & final_s(11) & final_s(43) & final_s(3) & final_s(35) &
final_s(28) & final_s(60) & final_s(20) & final_s(52) & final_s(12) & final_s(44) & final_s(4) & final_s(36) &
final_s(29) & final_s(61) & final_s(21) & final_s(53) & final_s(13) & final_s(45) & final_s(5) & final_s(37) &
final_s(30) & final_s(62) & final_s(22) & final_s(54) & final_s(14) & final_s(46) & final_s(6) & final_s(38) &
final_s(31) & final_s(63) & final_s(23) & final_s(55) & final_s(15) & final_s(47) & final_s(7) & final_s(39);
 
KEY_SCHEDULE_0 : key_schedule port map (clk, rst, mode, key_in, k_0_s);
 
end Behavioral;
 
/trunk/rtl/s_box_v_2.coe
0,0 → 1,66
memory_initialization_radix=10;
memory_initialization_vector=
15,
3,
1,
13,
8,
4,
14,
7,
6,
15,
11,
2,
3,
8,
4,
14,
9,
12,
7,
0,
2,
1,
13,
10,
12,
6,
0,
9,
5,
11,
10,
5,
0,
13,
14,
8,
7,
10,
11,
1,
10,
3,
4,
15,
13,
4,
1,
2,
5,
11,
8,
6,
12,
7,
6,
12,
9,
0,
3,
5,
2,
14,
15,
9;
/trunk/rtl/s_box_dram_1.xco
0,0 → 1,73
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Feb 20 09:56:57 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:dist_mem_gen:7.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=s_box_v_1.coe
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=s_box_dram_1
CSET data_width=4
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=rom
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qsdpo=false
CSET reset_qspo=false
CSET simple_dual_port_address=non_registered
CSET simple_dual_port_output_clock_enable=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qsdpo=false
CSET sync_reset_qspo=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-21T20:07:40Z
# END Extra information
GENERATE
# CRC: 6f134488
/trunk/rtl/s_box_v_3.coe
0,0 → 1,66
memory_initialization_radix=10;
memory_initialization_vector=
10,
13,
0,
7,
9,
0,
14,
9,
6,
3,
3,
4,
15,
6,
5,
10,
1,
2,
13,
8,
12,
5,
7,
14,
11,
12,
4,
11,
2,
15,
8,
1,
13,
1,
6,
10,
4,
13,
9,
0,
8,
6,
15,
9,
3,
8,
0,
7,
11,
4,
1,
15,
2,
14,
12,
3,
5,
11,
10,
5,
14,
2,
7,
12;
/trunk/rtl/s_box_dram_2.xco
0,0 → 1,73
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Feb 20 10:20:05 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:dist_mem_gen:7.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=s_box_v_2.coe
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=s_box_dram_2
CSET data_width=4
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=rom
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qsdpo=false
CSET reset_qspo=false
CSET simple_dual_port_address=non_registered
CSET simple_dual_port_output_clock_enable=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qsdpo=false
CSET sync_reset_qspo=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-21T20:07:40Z
# END Extra information
GENERATE
# CRC: cb0f7640
/trunk/rtl/s_box_v_4.coe
0,0 → 1,66
memory_initialization_radix=10;
memory_initialization_vector=
7,
13,
13,
8,
14,
11,
3,
5,
0,
6,
6,
15,
9,
0,
10,
3,
1,
4,
2,
7,
8,
2,
5,
12,
11,
1,
12,
10,
4,
14,
15,
9,
10,
3,
6,
15,
9,
0,
0,
6,
12,
10,
11,
1,
7,
13,
13,
8,
15,
9,
1,
4,
3,
5,
14,
11,
5,
12,
2,
7,
8,
2,
4,
14;
/trunk/rtl/s_box_dram_3.xco
0,0 → 1,73
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Feb 20 10:21:01 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:dist_mem_gen:7.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=s_box_v_3.coe
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=s_box_dram_3
CSET data_width=4
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=rom
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qsdpo=false
CSET reset_qspo=false
CSET simple_dual_port_address=non_registered
CSET simple_dual_port_output_clock_enable=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qsdpo=false
CSET sync_reset_qspo=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-21T20:07:40Z
# END Extra information
GENERATE
# CRC: a8fb67f8
/trunk/rtl/s_box_dram_4.xco
0,0 → 1,73
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Feb 20 10:21:53 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:dist_mem_gen:7.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=s_box_v_4.coe
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=s_box_dram_4
CSET data_width=4
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=rom
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qsdpo=false
CSET reset_qspo=false
CSET simple_dual_port_address=non_registered
CSET simple_dual_port_output_clock_enable=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qsdpo=false
CSET sync_reset_qspo=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-21T20:07:40Z
# END Extra information
GENERATE
# CRC: 58461591
/trunk/rtl/s_box_v_5.coe
0,0 → 1,66
memory_initialization_radix=10;
memory_initialization_vector=
2,
14,
12,
11,
4,
2,
1,
12,
7,
4,
10,
7,
11,
13,
6,
1,
8,
5,
5,
0,
3,
15,
15,
10,
13,
3,
0,
9,
14,
8,
9,
6,
4,
11,
2,
8,
1,
12,
11,
7,
10,
1,
13,
14,
7,
2,
8,
13,
15,
6,
9,
15,
12,
0,
5,
9,
6,
10,
3,
4,
0,
5,
14,
3;
/trunk/rtl/s_box_dram_5.xco
0,0 → 1,73
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Feb 20 10:22:51 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:dist_mem_gen:7.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=s_box_v_5.coe
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=s_box_dram_5
CSET data_width=4
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=rom
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qsdpo=false
CSET reset_qspo=false
CSET simple_dual_port_address=non_registered
CSET simple_dual_port_output_clock_enable=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qsdpo=false
CSET sync_reset_qspo=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-21T20:07:40Z
# END Extra information
GENERATE
# CRC: 3bb20429
/trunk/rtl/s_box_v_6.coe
0,0 → 1,66
memory_initialization_radix=10;
memory_initialization_vector=
12,
10,
1,
15,
10,
4,
15,
2,
9,
7,
2,
12,
6,
9,
8,
5,
0,
6,
13,
1,
3,
13,
4,
14,
14,
0,
7,
11,
5,
3,
11,
8,
9,
4,
14,
3,
15,
2,
5,
12,
2,
9,
8,
5,
12,
15,
3,
10,
7,
11,
0,
14,
4,
1,
10,
7,
1,
6,
13,
0,
11,
8,
6,
13;
/trunk/rtl/s_box_dram_6.xco
0,0 → 1,73
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Feb 20 10:23:44 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:dist_mem_gen:7.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=s_box_v_6.coe
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=s_box_dram_6
CSET data_width=4
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=rom
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qsdpo=false
CSET reset_qspo=false
CSET simple_dual_port_address=non_registered
CSET simple_dual_port_output_clock_enable=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qsdpo=false
CSET sync_reset_qspo=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-21T20:07:40Z
# END Extra information
GENERATE
# CRC: 9fae36e1
/trunk/rtl/s_box_v_7.coe
0,0 → 1,66
memory_initialization_radix=10;
memory_initialization_vector=
4,
13,
11,
0,
2,
11,
14,
7,
15,
4,
0,
9,
8,
1,
13,
10,
3,
14,
12,
3,
9,
5,
7,
12,
5,
2,
10,
15,
6,
8,
1,
6,
1,
6,
4,
11,
11,
13,
13,
8,
12,
1,
3,
4,
7,
10,
14,
7,
10,
9,
15,
5,
6,
0,
8,
15,
0,
14,
5,
2,
9,
3,
2,
12;
/trunk/rtl/s_box_dram_7.xco
0,0 → 1,73
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Feb 20 10:24:39 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:dist_mem_gen:7.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=s_box_v_7.coe
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=s_box_dram_7
CSET data_width=4
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=rom
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qsdpo=false
CSET reset_qspo=false
CSET simple_dual_port_address=non_registered
CSET simple_dual_port_output_clock_enable=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qsdpo=false
CSET sync_reset_qspo=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-21T20:07:40Z
# END Extra information
GENERATE
# CRC: fc5a2759
/trunk/rtl/s_box_v_8.coe
0,0 → 1,66
memory_initialization_radix=10;
memory_initialization_vector=
13,
1,
2,
15,
8,
13,
4,
8,
6,
10,
15,
3,
11,
7,
1,
4,
10,
12,
9,
5,
3,
6,
14,
11,
5,
0,
0,
14,
12,
9,
7,
2,
7,
2,
11,
1,
4,
14,
1,
7,
9,
4,
12,
10,
14,
8,
2,
13,
0,
15,
6,
12,
10,
9,
13,
0,
15,
3,
3,
5,
5,
6,
8,
11;
/trunk/rtl/s_box_dram_8.xco
0,0 → 1,73
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Feb 20 10:25:29 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:dist_mem_gen:7.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=s_box_v_8.coe
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=s_box_dram_8
CSET data_width=4
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=rom
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qsdpo=false
CSET reset_qspo=false
CSET simple_dual_port_address=non_registered
CSET simple_dual_port_output_clock_enable=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qsdpo=false
CSET sync_reset_qspo=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-21T20:07:40Z
# END Extra information
GENERATE
# CRC: a5a5d472
/trunk/rtl/des_round.vhd
0,0 → 1,69
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:52:29 02/20/2013
-- Design Name:
-- Module Name: des_round - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity des_round is
port(clk : in std_logic;
l_0 : in std_logic_vector(31 downto 0);
r_0 : in std_logic_vector(31 downto 0);
k_i : in std_logic_vector(47 downto 0);
l_1 : out std_logic_vector(31 downto 0);
r_1 : out std_logic_vector(31 downto 0));
end des_round;
 
architecture Behavioral of des_round is
 
component f_fun is
port(clk : in std_logic;
r_in : in std_logic_vector(31 downto 0);
k_in : in std_logic_vector(47 downto 0);
r_out : out std_logic_vector(31 downto 0));
end component;
 
component dsp_xor is
port (clk : in std_logic;
op_1 : in std_logic_vector(31 downto 0);
op_2 : in std_logic_vector(31 downto 0);
op_3 : out std_logic_vector(31 downto 0));
end component;
 
signal f_out_s : std_logic_vector(31 downto 0);
 
begin
 
F_FUN_0 : f_fun port map (clk, r_0, k_i, f_out_s);
 
l_1 <= r_0;
r_1 <= l_0 xor f_out_s;
 
-- DSP_XOR_0 : dsp_xor port map (clk, l_0, f_out_s, r_1);
 
end Behavioral;
 
/trunk/rtl/f_fun.vhd
0,0 → 1,143
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:16:46 02/19/2013
-- Design Name:
-- Module Name: f_fun - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity f_fun is
port(clk : in std_logic;
r_in : in std_logic_vector(31 downto 0);
k_in : in std_logic_vector(47 downto 0);
r_out : out std_logic_vector(31 downto 0));
end f_fun;
 
architecture Behavioral of f_fun is
 
component dsp_xor is
port (clk : in std_logic;
op_1 : in std_logic_vector(31 downto 0);
op_2 : in std_logic_vector(31 downto 0);
op_3 : out std_logic_vector(31 downto 0));
end component;
 
component dsp_xor_48 is
port (clk : in std_logic;
op_1 : in std_logic_vector(47 downto 0);
op_2 : in std_logic_vector(47 downto 0);
op_3 : out std_logic_vector(47 downto 0));
end component;
 
COMPONENT s_box_dram_1
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
 
COMPONENT s_box_dram_2
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_3
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
 
COMPONENT s_box_dram_4
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
 
COMPONENT s_box_dram_5
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_6
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
 
COMPONENT s_box_dram_7
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
 
COMPONENT s_box_dram_8
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
signal blk_exp_s : std_logic_vector(47 downto 0);
signal post_exp_key_add_s : std_logic_vector(47 downto 0);
signal post_s_box_s : std_logic_vector(31 downto 0);
 
begin
 
-- E
 
blk_exp_s <= r_in(0) & r_in(31) & r_in(30) & r_in(29) & r_in(28) & r_in(27) &
r_in(28) & r_in(27) & r_in(26) & r_in(25) & r_in(24) & r_in(23) &
r_in(24) & r_in(23) & r_in(22) & r_in(21) & r_in(20) & r_in(19) &
r_in(20) & r_in(19) & r_in(18) & r_in(17) & r_in(16) & r_in(15) &
r_in(16) & r_in(15) & r_in(14) & r_in(13) & r_in(12) & r_in(11) &
r_in(12) & r_in(11) & r_in(10) & r_in(9) & r_in(8) & r_in(7) &
r_in(8) & r_in(7) & r_in(6) & r_in(5) & r_in(4) & r_in(3) &
r_in(4) & r_in(3) & r_in(2) & r_in(1) & r_in(0) & r_in(31);
-- DSP_XOR_0 : dsp_xor_48 port map (clk, blk_exp_s, k_in, post_exp_key_add_s);
 
post_exp_key_add_s <= blk_exp_s xor k_in;
 
-- S_BOX_0 : s_box_dram_1 port map (post_exp_key_add_s(47 downto 42), post_s_box_s(31 downto 28));
-- S_BOX_1 : s_box_dram_2 port map (post_exp_key_add_s(41 downto 36), post_s_box_s(27 downto 24));
-- S_BOX_2 : s_box_dram_3 port map (post_exp_key_add_s(35 downto 30), post_s_box_s(23 downto 20));
-- S_BOX_3 : s_box_dram_4 port map (post_exp_key_add_s(29 downto 24), post_s_box_s(19 downto 16));
-- S_BOX_4 : s_box_dram_5 port map (post_exp_key_add_s(23 downto 18), post_s_box_s(15 downto 12));
-- S_BOX_5 : s_box_dram_6 port map (post_exp_key_add_s(17 downto 12), post_s_box_s(11 downto 8));
-- S_BOX_6 : s_box_dram_7 port map (post_exp_key_add_s(11 downto 6), post_s_box_s(7 downto 4));
-- S_BOX_7 : s_box_dram_8 port map (post_exp_key_add_s(5 downto 0), post_s_box_s(3 downto 0));
 
S_BOX_0 : s_box_dram_1 port map (post_exp_key_add_s(47 downto 42), post_s_box_s(31 downto 28));
S_BOX_1 : s_box_dram_2 port map (post_exp_key_add_s(41 downto 36), post_s_box_s(27 downto 24));
S_BOX_2 : s_box_dram_3 port map (post_exp_key_add_s(35 downto 30), post_s_box_s(23 downto 20));
S_BOX_3 : s_box_dram_4 port map (post_exp_key_add_s(29 downto 24), post_s_box_s(19 downto 16));
S_BOX_4 : s_box_dram_5 port map (post_exp_key_add_s(23 downto 18), post_s_box_s(15 downto 12));
S_BOX_5 : s_box_dram_6 port map (post_exp_key_add_s(17 downto 12), post_s_box_s(11 downto 8));
S_BOX_6 : s_box_dram_7 port map (post_exp_key_add_s(11 downto 6), post_s_box_s(7 downto 4));
S_BOX_7 : s_box_dram_8 port map (post_exp_key_add_s(5 downto 0), post_s_box_s(3 downto 0));
 
 
r_out <= post_s_box_s(16) & post_s_box_s(25) & post_s_box_s(12) & post_s_box_s(11) & post_s_box_s(3) & post_s_box_s(20) & post_s_box_s(4) & post_s_box_s(15) &
post_s_box_s(31) & post_s_box_s(17) & post_s_box_s(9) & post_s_box_s(6) & post_s_box_s(27) & post_s_box_s(14) & post_s_box_s(1) & post_s_box_s(22) &
post_s_box_s(30) & post_s_box_s(24) & post_s_box_s(8) & post_s_box_s(18) & post_s_box_s(0) & post_s_box_s(5) & post_s_box_s(29) & post_s_box_s(23) &
post_s_box_s(13) & post_s_box_s(19) & post_s_box_s(2) & post_s_box_s(26) & post_s_box_s(10) & post_s_box_s(21) & post_s_box_s(28) & post_s_box_s(7);
 
 
end Behavioral;
 
/trunk/tb/tb_des_loop.vhd
0,0 → 1,120
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:47:33 02/21/2013
-- Design Name:
-- Module Name: C:/Users/vmr/Desktop/crypto_ng/des/dram/desl/tb_des_loop.vhd
-- Project Name: desl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: des_loop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_des_loop IS
END tb_des_loop;
ARCHITECTURE behavior OF tb_des_loop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT des_loop
PORT(
clk : IN std_logic;
rst : IN std_logic;
mode : IN std_logic;
key_in : IN std_logic_vector(63 downto 0);
blk_in : IN std_logic_vector(63 downto 0);
blk_out : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal mode : std_logic := '0';
signal key_in : std_logic_vector(63 downto 0) := (others => '0');
signal blk_in : std_logic_vector(63 downto 0) := (others => '0');
 
--Outputs
signal blk_out : std_logic_vector(63 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: des_loop PORT MAP (
clk => clk,
rst => rst,
mode => mode,
key_in => key_in,
blk_in => blk_in,
blk_out => blk_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
mode <= '0';
blk_in <= X"4E45565251554954";
key_in <= X"4B41534849534142";
rst <= '1';
wait for clk_period;
rst <= '0';
wait for clk_period*16;
assert blk_out = X"763549D38B570C0E"
report "ENCRYPT ERROR" severity FAILURE;
wait for clk_period;
 
mode <= '1';
blk_in <= X"763549D38B570C0E";
key_in <= X"4B41534849534142";
rst <= '1';
wait for clk_period;
rst <= '0';
wait for clk_period*16;
 
assert blk_out = X"4E45565251554954"
report "DECRYPT ERROR" severity FAILURE;
 
wait;
end process;
 
END;

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