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    /descore
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Rev 2 → Rev 3

/trunk/rtl/des_loop.vhd
1,34 → 1,22
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:30:59 02/20/2013
-- Design Name:
-- Module Name: des - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity des_loop is
port(clk : in std_logic;
rst : in std_logic;
127,23 → 115,6
rst_s <= rst;
end if;
end process;
 
-- k_0_s <= "101000001001001011000010000010101011000101000000";
-- k_1_s <= "101000000001001001010010010011000000000010101011";
-- k_2_s <= "001001000101101001010000000001100101100001001001";
-- k_3_s <= "000001100111000101010000000000101001000101110000";
-- k_4_s <= "000011100100010101010001100000011000110100100000";
-- k_5_s <= "010011110100000100001001010010000000111000010000";
-- k_6_s <= "000010111000000110001001010110010100000000011100";
-- k_7_s <= "000110010000100010001011000000010101000010001000";
-- k_8_s <= "000110010000101010001000000110000010111010010000";
-- k_9_s <= "000100000011100010001100001110010100000000010001";
-- k_10_s <= "000100000010110001000100000000110110000000000010";
-- k_11_s <= "010000000110110000100100101001000010000100000100";
-- k_12_s <= "110000001010010100100100101000000000001011000110";
-- k_13_s <= "110000001000011000100011010101001000001010000011";
-- k_14_s <= "111000011001001000100010000101100000010001001001";
-- k_15_s <= "101000001001001000101010011000000001010010000110";
-- IP
 
/trunk/rtl/key_schedule.vhd
1,34 → 1,22
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:16 02/20/2013
-- Design Name:
-- Module Name: key_schedule - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity key_schedule is
port(clk : in std_logic;
rst : in std_logic;
94,8 → 82,6
end if;
end process;
 
-- XXX Podemos meter aqui un FF para retrasar la salida n ciclos.
 
key_pre_s <= c_0_s & d_0_s;
pr_delay: process(clk, mode, key_pre_s)
/trunk/rtl/des_round.vhd
1,34 → 1,22
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:52:29 02/20/2013
-- Design Name:
-- Module Name: des_round - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity des_round is
port(clk : in std_logic;
l_0 : in std_logic_vector(31 downto 0);
63,7 → 51,5
l_1 <= r_0;
r_1 <= l_0 xor f_out_s;
 
-- DSP_XOR_0 : dsp_xor port map (clk, l_0, f_out_s, r_1);
 
end Behavioral;
 
/trunk/rtl/f_fun.vhd
1,22 → 1,19
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:16:46 02/19/2013
-- Design Name:
-- Module Name: f_fun - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
110,19 → 107,8
r_in(8) & r_in(7) & r_in(6) & r_in(5) & r_in(4) & r_in(3) &
r_in(4) & r_in(3) & r_in(2) & r_in(1) & r_in(0) & r_in(31);
-- DSP_XOR_0 : dsp_xor_48 port map (clk, blk_exp_s, k_in, post_exp_key_add_s);
 
post_exp_key_add_s <= blk_exp_s xor k_in;
 
-- S_BOX_0 : s_box_dram_1 port map (post_exp_key_add_s(47 downto 42), post_s_box_s(31 downto 28));
-- S_BOX_1 : s_box_dram_2 port map (post_exp_key_add_s(41 downto 36), post_s_box_s(27 downto 24));
-- S_BOX_2 : s_box_dram_3 port map (post_exp_key_add_s(35 downto 30), post_s_box_s(23 downto 20));
-- S_BOX_3 : s_box_dram_4 port map (post_exp_key_add_s(29 downto 24), post_s_box_s(19 downto 16));
-- S_BOX_4 : s_box_dram_5 port map (post_exp_key_add_s(23 downto 18), post_s_box_s(15 downto 12));
-- S_BOX_5 : s_box_dram_6 port map (post_exp_key_add_s(17 downto 12), post_s_box_s(11 downto 8));
-- S_BOX_6 : s_box_dram_7 port map (post_exp_key_add_s(11 downto 6), post_s_box_s(7 downto 4));
-- S_BOX_7 : s_box_dram_8 port map (post_exp_key_add_s(5 downto 0), post_s_box_s(3 downto 0));
 
S_BOX_0 : s_box_dram_1 port map (post_exp_key_add_s(47 downto 42), post_s_box_s(31 downto 28));
S_BOX_1 : s_box_dram_2 port map (post_exp_key_add_s(41 downto 36), post_s_box_s(27 downto 24));
S_BOX_2 : s_box_dram_3 port map (post_exp_key_add_s(35 downto 30), post_s_box_s(23 downto 20));
131,8 → 117,6
S_BOX_5 : s_box_dram_6 port map (post_exp_key_add_s(17 downto 12), post_s_box_s(11 downto 8));
S_BOX_6 : s_box_dram_7 port map (post_exp_key_add_s(11 downto 6), post_s_box_s(7 downto 4));
S_BOX_7 : s_box_dram_8 port map (post_exp_key_add_s(5 downto 0), post_s_box_s(3 downto 0));
 
 
r_out <= post_s_box_s(16) & post_s_box_s(25) & post_s_box_s(12) & post_s_box_s(11) & post_s_box_s(3) & post_s_box_s(20) & post_s_box_s(4) & post_s_box_s(15) &
post_s_box_s(31) & post_s_box_s(17) & post_s_box_s(9) & post_s_box_s(6) & post_s_box_s(27) & post_s_box_s(14) & post_s_box_s(1) & post_s_box_s(22) &
post_s_box_s(30) & post_s_box_s(24) & post_s_box_s(8) & post_s_box_s(18) & post_s_box_s(0) & post_s_box_s(5) & post_s_box_s(29) & post_s_box_s(23) &
/trunk/tb/tb_des_loop.vhd
1,38 → 1,23
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:47:33 02/21/2013
-- Design Name:
-- Module Name: C:/Users/vmr/Desktop/crypto_ng/des/dram/desl/tb_des_loop.vhd
-- Project Name: desl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: des_loop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_des_loop IS
ENTITY tb_des_loop IS
END tb_des_loop;
ARCHITECTURE behavior OF tb_des_loop IS

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