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fpga/experiments/memctrl/fpga/memctrl-1/build/memtest.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: fpga/experiments/memctrl/fpga/memctrl-1/src/ramtest/ramtest.v =================================================================== --- fpga/experiments/memctrl/fpga/memctrl-1/src/ramtest/ramtest.v (nonexistent) +++ fpga/experiments/memctrl/fpga/memctrl-1/src/ramtest/ramtest.v (revision 318) @@ -0,0 +1,262 @@ +// +// ramtest.v -- RAM test generator +// + + +`timescale 1ns/10ps +`default_nettype none + + +//`define SIMULATE +//`define VERBOSE + +`define INST_PERIOD 31 +`define INST_PHASE 19 +`define DATA_PERIOD 17 +`define DATA_PHASE 7 + + +// +// memory test generator +// +// Algorithm: Three independent address/data generators +// produce exactly the same sequence of address/data pairs, +// although at different times: data write, data read, and +// instruction read. Three out of four data cycles are writes, +// one is a read. Instruction reads are also less frequent +// than data writes: 1/31 < 1/17 * 3/4. The writing process +// is therefore always ahead of the reading processes, with +// an increasing gap in between. +// + +module ramtest(clk, rst, + inst_stb, inst_addr, + inst_din, inst_ack, + data_stb, data_we, data_addr, + data_dout, data_din, data_ack, + test_ended, test_error); + input clk; + input rst; + output reg inst_stb; + output [25:0] inst_addr; + input [63:0] inst_din; + input inst_ack; + output reg data_stb; + output reg data_we; + output [25:0] data_addr; + output [63:0] data_dout; + input [63:0] data_din; + input data_ack; + output test_ended; + output test_error; + + reg [4:0] inst_timer; + reg [4:0] data_timer; + reg [9:0] data_counter; + + wire ir_next; + wire [21:0] ir_a; + wire [63:0] ir_d; + + wire dw_next; + wire [21:0] dw_a; + wire [63:0] dw_d; + + wire dr_next; + wire [21:0] dr_a; + wire [63:0] dr_d; + +`ifdef SIMULATE + reg error_1; + reg error_3; +`endif + reg error_2; + reg error_4; + + always @(posedge clk) begin + if (rst) begin + inst_timer <= 0; + inst_stb <= 0; +`ifdef SIMULATE + error_1 <= 0; +`endif + error_2 <= 0; + end else begin + if (~test_ended) begin + if (~inst_stb) begin + if (inst_timer == `INST_PERIOD - 1) begin + inst_timer <= 0; + end else begin + inst_timer <= inst_timer + 1; + end + if (inst_timer == `INST_PHASE) begin + inst_stb <= 1; + end + end else begin + if (inst_ack) begin + inst_stb <= 0; +`ifdef SIMULATE +`ifdef VERBOSE + $display("%t: inst read @ 0x%h", $realtime, ir_a); + $display(" value = 0x%h", inst_din); +`endif + if (^inst_din[63:0] === 1'bx) begin + $display("Warning: Input data has don't cares at %t", + $realtime); + error_1 <= 1; + end +`endif + if (inst_din[63:0] != ir_d[63:0]) begin + error_2 <= 1; + end + end + end + end + end + end + + adgen adgen_ir( + .clk(clk), + .rst(rst), + .next(ir_next), + .addr(ir_a), + .data(ir_d) + ); + + assign ir_next = inst_ack; + assign inst_addr[25:0] = { 4'h0, ir_a[21:0] }; + + always @(posedge clk) begin + if (rst) begin + data_timer <= 0; + data_stb <= 0; + data_we <= 0; + data_counter <= 0; +`ifdef SIMULATE + error_3 <= 0; +`endif + error_4 <= 0; + end else begin + if (~test_ended) begin + if (~data_stb) begin + if (data_timer == `DATA_PERIOD - 1) begin + data_timer <= 0; + end else begin + data_timer <= data_timer + 1; + end + if (data_timer == `DATA_PHASE) begin + data_stb <= 1; + data_we <= ~&data_counter[1:0]; + end + end else begin + if (data_ack) begin + data_stb <= 0; + data_we <= 0; + data_counter <= data_counter + 1; +`ifdef SIMULATE +`ifdef VERBOSE + if (data_we == 1) begin + $display("%t: data write @ 0x%h", $realtime, dw_a); + $display(" value = 0x%h", dw_d); + end else begin + $display("%t: data read @ 0x%h", $realtime, dr_a); + $display(" value = 0x%h", data_din); + end +`endif + if (data_we == 0 && + ^data_din[63:0] === 1'bx) begin + $display("Warning: Input data has don't cares at %t", + $realtime); + error_3 <= 1; + end +`endif + if (data_we == 0 && + data_din[63:0] != dr_d[63:0]) begin + error_4 <= 1; + end + end + end + end + end + end + + adgen adgen_dw( + .clk(clk), + .rst(rst), + .next(dw_next), + .addr(dw_a), + .data(dw_d) + ); + + adgen adgen_dr( + .clk(clk), + .rst(rst), + .next(dr_next), + .addr(dr_a), + .data(dr_d) + ); + + assign dw_next = data_ack & data_we; + assign dr_next = data_ack & ~data_we; + assign data_addr[25:0] = { 4'h0, data_we ? dw_a[21:0] : dr_a[21:0] }; + assign data_dout[63:0] = dw_d[63:0]; + + assign test_ended = &data_counter[9:0]; + +`ifdef SIMULATE + assign test_error = error_1 | error_2 | error_3 | error_4; +`else + assign test_error = error_2 | error_4; +`endif + +endmodule + + +// +// address & data generator +// +// compute pseudo-random 32-bit address +// and 64-bit data on request +// + +module adgen(clk, rst, + next, addr, data); + input clk; + input rst; + input next; + output [21:0] addr; + output [63:0] data; + + reg [31:0] a; + reg [63:0] d; + + always @(posedge clk) begin + if (rst) begin + a[31: 0] <= 32'hC70337DB; + d[63:32] <= 32'h7F4D514F; + d[31: 0] <= 32'h75377599; + end else begin + if (next) begin + if (a[0] == 0) begin + a[31:0] <= a[31:0] >> 1; + end else begin + a[31:0] <= (a[31:0] >> 1) ^ 32'hD0000001; + end + if (d[32] == 0) begin + d[63:32] <= d[63:32] >> 1; + end else begin + d[63:32] <= (d[63:32] >> 1) ^ 32'hD0000001; + end + if (d[0] == 0) begin + d[31:0] <= d[31:0] >> 1; + end else begin + d[31:0] <= (d[31:0] >> 1) ^ 32'hD0000001; + end + end + end + end + + assign addr[21:0] = a[21:0]; + assign data[63:0] = d[63:0]; + +endmodule Index: fpga/experiments/memctrl/fpga/memctrl-1/src/clk_rst/clk_rst.v =================================================================== --- fpga/experiments/memctrl/fpga/memctrl-1/src/clk_rst/clk_rst.v (nonexistent) +++ fpga/experiments/memctrl/fpga/memctrl-1/src/clk_rst/clk_rst.v (revision 318) @@ -0,0 +1,123 @@ +// +// clk_rst.v -- clock and reset generator +// + + +`timescale 1ns/10ps +`default_nettype none + + +module clk_rst(clk_in, rst_inout_n, + sdram_clk, sdram_fb, + clk_ok, clk, rst); + input clk_in; + inout rst_inout_n; + output sdram_clk; + input sdram_fb; + output clk_ok; + output clk; + output rst; + + wire clk_in_buf; + wire int_clk; + wire int_locked; + wire ext_rst_n; + wire ext_fb; + wire ext_clk; + wire ext_locked; + + wire rst_counting; + reg [23:0] rst_counter; + reg rst_p_n; + reg rst_s_n; + + // + // internal DCM, 100 MHz + // + + IBUF clk_in_buffer( + .I(clk_in), + .O(clk_in_buf) + ); + + DCM int_dcm( + .CLKIN(clk_in_buf), + .CLKFB(clk), + .RST(1'b0), + .CLK0(int_clk), + .LOCKED(int_locked) + ); + + BUFG int_clk_buffer( + .I(int_clk), + .O(clk) + ); + + // + // reset circuit for external DCM + // + + SRL16 ext_dll_rst_gen( + .CLK(clk_in_buf), + .D(int_locked), + .Q(ext_rst_n), + .A0(1'b1), + .A1(1'b1), + .A2(1'b1), + .A3(1'b1) + ); + + defparam ext_dll_rst_gen.INIT = 16'h0000; + + // + // external DCM, 100 MHz + // + + IBUF ext_fb_buffer( + .I(sdram_fb), + .O(ext_fb) + ); + + DCM ext_dcm( + .CLKIN(clk_in_buf), + .CLKFB(ext_fb), + .RST(~ext_rst_n), + .CLK0(ext_clk), + .LOCKED(ext_locked), + .PSEN(1'b0), + .PSCLK(1'b0), + .PSINCDEC(1'b0) + ); + + defparam ext_dcm.CLKOUT_PHASE_SHIFT = "FIXED"; + defparam ext_dcm.PHASE_SHIFT = 0; + + OBUF ext_clk_buffer( + .I(ext_clk), + .O(sdram_clk) + ); + + assign clk_ok = int_locked & ext_locked; + + // + // reset generator + // + + assign rst_counting = (rst_counter == 24'hFFFFFF) ? 0 : 1; + assign rst_inout_n = (rst_counter[23] == 0) ? 1'b0 : 1'bz; + + always @(posedge clk) begin + rst_p_n <= rst_inout_n; + rst_s_n <= rst_p_n; + if (rst_counting) begin + rst_counter <= rst_counter + 1; + end else begin + if (~rst_s_n | ~clk_ok) begin + rst_counter <= 24'h000000; + end + end + end + + assign rst = rst_counting; + +endmodule Index: fpga/experiments/memctrl/fpga/memctrl-1/src/ramctrl/ramctrl.v =================================================================== --- fpga/experiments/memctrl/fpga/memctrl-1/src/ramctrl/ramctrl.v (nonexistent) +++ fpga/experiments/memctrl/fpga/memctrl-1/src/ramctrl/ramctrl.v (revision 318) @@ -0,0 +1,533 @@ +// +// ramctrl.v -- RAM controller +// + + +`timescale 1ns/10ps +`default_nettype none + + +`define MODE 13'h0032 // CL = 3, sequ. burst length = 4 + +`define CMD_MRSET 3'b000 // mode register set +`define CMD_ARFRS 3'b001 // auto refresh +`define CMD_PRCHG 3'b010 // precharge (deactivate row/rows) +`define CMD_ACTV 3'b011 // select bank, activate row +`define CMD_WRITE 3'b100 // select bank & column, start write +`define CMD_READ 3'b101 // select bank & column, start read +`define CMD_BSTOP 3'b110 // burst stop +`define CMD_NOP 3'b111 // no operation + +// +// Note: The FSM is a registered Mealy machine. Its actions, which +// are noted here for a specific state, take place in the next +// clock cycle. This is only a notational problem: the actions +// should in fact be associated with state transitions. +// +// ST_RESET // NOP, CKE=0, CS_N=1, wait 100 us +`define ST_INIT0 5'd0 // NOP, CKE=1, CS_N=0, wait 100 us +`define ST_INIT1 5'd1 // PRECHARGE ALL +`define ST_INIT2 5'd2 // NOP, wait tRP - 1 cycle +`define ST_INIT3 5'd3 // AUTO REFRESH +`define ST_INIT4 5'd4 // NOP, wait tRFC - 1 cycle +`define ST_INIT5 5'd5 // AUTO REFRESH +`define ST_INIT6 5'd6 // NOP, wait tRFC - 1 cycle +`define ST_INIT7 5'd7 // MODE REGISTER SET +`define ST_INIT8 5'd8 // NOP, wait tMRD - 1 cycle +`define ST_IDLE 5'd9 // AUTO REFRESH, ACTIVE, or NOP +`define ST_RFRSH 5'd10 // NOP, wait tRFC - 1 cycle +`define ST_WRDATA0 5'd11 // NOP, wait tRCD - 1 cycle +`define ST_WRDATA1 5'd12 // WRITE, de=1 +`define ST_WRDATA2 5'd13 // NOP, wait 3 cycles +`define ST_WRDATA3 5'd14 // NOP, ack=1, de=0 +`define ST_WRDATA4 5'd15 // NOP, ack=0, wait 3 cycles +`define ST_RDDATA0 5'd16 // NOP, wait tRCD - 1 cycle +`define ST_RDDATA1 5'd17 // READ +`define ST_RDDATA2 5'd18 // NOP, wait 2 cycles +`define ST_RDDATA3 5'd19 // NOP, ld=1, wait 4 cycles +`define ST_RDDATA4 5'd20 // NOP, ack=1, ld=0 +`define ST_RDDATA5 5'd21 // NOP, ack=0, wait 4 cycles +`define ST_RDINST0 5'd22 // NOP, wait tRCD - 1 cycle +`define ST_RDINST1 5'd23 // READ +`define ST_RDINST2 5'd24 // NOP, wait 2 cycles +`define ST_RDINST3 5'd25 // NOP, ld=1, wait 4 cycles +`define ST_RDINST4 5'd26 // NOP, ack=1, ld=0 +`define ST_RDINST5 5'd27 // NOP, ack=0, wait 4 cycles +`define ST_ILLDA0 5'd28 // NOP, data_timeout=1 +`define ST_ILLDA1 5'd29 // NOP, data_timeout=0 +`define ST_ILLIA0 5'd30 // NOP, inst_timeout=1 +`define ST_ILLIA1 5'd31 // NOP, inst_timeout=0 + +`define T_INIT0 14'd10000 // min 100 usec with CKE = 0 +`define T_INIT1 14'd10000 // min 100 usec with CKE = 1 +`define T_RP 14'd3 // min 20 ns row precharge time +`define T_RFC 14'd9 // min 66 ns auto refresh period +`define T_MRD 14'd3 // min load mode register delay +`define T_RCD 14'd3 // min 20 ns active-to-rw delay + +`define REFCNT 10'd780 // 8192 refresh cycles per 64 ms + + +module ramctrl(clk_ok, clk, + inst_stb, inst_addr, + inst_dout, inst_ack, + inst_timeout, + data_stb, data_we, + data_addr, data_din, + data_dout, data_ack, + data_timeout, + sdram_cke, sdram_cs_n, + sdram_ras_n, sdram_cas_n, + sdram_we_n, sdram_ba, sdram_a, + sdram_udqm, sdram_ldqm, sdram_dq); + // internal interface signals + input clk_ok; + input clk; + input inst_stb; + input [25:0] inst_addr; + output [63:0] inst_dout; + output reg inst_ack; + output reg inst_timeout; + input data_stb; + input data_we; + input [25:0] data_addr; + input [63:0] data_din; + output [63:0] data_dout; + output reg data_ack; + output reg data_timeout; + // external interface signals + output reg sdram_cke; + output reg sdram_cs_n; + output sdram_ras_n; + output sdram_cas_n; + output sdram_we_n; + output reg [1:0] sdram_ba; + output reg [12:0] sdram_a; + output sdram_udqm; + output sdram_ldqm; + inout [15:0] sdram_dq; + + reg [1:0] ram_cnt; + wire [15:0] ram_dout; + reg ram_de; + reg [63:0] data; + reg data_ld; + + wire inst_addr_out_of_range; + wire data_addr_out_of_range; + + reg [2:0] ram_cmd; + reg [1:0] ram_dqm; + reg [13:0] count; + reg [4:0] state; + + reg [9:0] refcnt; + reg refflg; + reg refrst; + + // + // data output to ram + // + + assign ram_dout[15:0] = + ~ram_cnt[1] ? (~ram_cnt[0] ? data_din[63:48] : data_din[47:32]) : + (~ram_cnt[0] ? data_din[31:16] : data_din[15: 0]); + assign sdram_dq[15:0] = ram_de ? ram_dout[15:0] : 16'hzzzz; + + // + // data output to cache + // + + always @(posedge clk) begin + if (data_ld & (ram_cnt[1:0] == 2'b00)) begin + data[63:48] <= sdram_dq[15:0]; + end + if (data_ld & (ram_cnt[1:0] == 2'b01)) begin + data[47:32] <= sdram_dq[15:0]; + end + if (data_ld & (ram_cnt[1:0] == 2'b10)) begin + data[31:16] <= sdram_dq[15:0]; + end + if (data_ld & (ram_cnt[1:0] == 2'b11)) begin + data[15: 0] <= sdram_dq[15:0]; + end + end + + assign inst_dout[63:0] = data[63:0]; + assign data_dout[63:0] = data[63:0]; + + // + // address range check + // + + assign inst_addr_out_of_range = | inst_addr[25:22]; + assign data_addr_out_of_range = | data_addr[25:22]; + + // + // ramctrl state machine + // + + assign sdram_ras_n = ram_cmd[2]; + assign sdram_cas_n = ram_cmd[1]; + assign sdram_we_n = ram_cmd[0]; + + assign sdram_udqm = ram_dqm[1]; + assign sdram_ldqm = ram_dqm[0]; + + always @(posedge clk or negedge clk_ok) begin + // asynchronous reset + if (~clk_ok) begin + inst_ack <= 0; + inst_timeout <= 0; + data_ack <= 0; + data_timeout <= 0; + sdram_cke <= 0; + sdram_cs_n <= 1; + ram_cnt <= 0; + ram_de <= 0; + data_ld <= 0; + ram_cmd <= `CMD_NOP; + ram_dqm <= 2'b11; + count <= `T_INIT0 - 1; + state <= `ST_INIT0; + refrst <= 0; + end else begin + if (|count[13:0]) begin + // wait until count = 0 + // if count is loaded with N on a state transition, the + // new state will last for (N+1)/fclk cycles before (!) + // any action specified in the new state will take place + count <= count - 1; + // ram_cnt cycles through the 16-bit half-words in SDRAM + // during burst read/writes while the main state machine + // waits, thus it must be incremented here + ram_cnt <= ram_cnt + 1; + end else begin + case (state) + //---------------------------- + // init + //---------------------------- + `ST_INIT0: + begin + sdram_cke <= 1; + sdram_cs_n <= 0; + ram_cmd <= `CMD_NOP; + count <= `T_INIT1 - 1; + state <= `ST_INIT1; + end + `ST_INIT1: + begin + ram_cmd <= `CMD_PRCHG; + sdram_ba <= 2'b00; // don't care + sdram_a <= 13'h0400; // precharge all + state <= `ST_INIT2; + end + `ST_INIT2: + begin + ram_cmd <= `CMD_NOP; + count <= `T_RP - 2; + state <= `ST_INIT3; + end + `ST_INIT3: + begin + ram_cmd <= `CMD_ARFRS; + state <= `ST_INIT4; + end + `ST_INIT4: + begin + ram_cmd <= `CMD_NOP; + count <= `T_RFC - 2; + state <= `ST_INIT5; + end + `ST_INIT5: + begin + ram_cmd <= `CMD_ARFRS; + state <= `ST_INIT6; + end + `ST_INIT6: + begin + ram_cmd <= `CMD_NOP; + count <= `T_RFC - 2; + state <= `ST_INIT7; + end + `ST_INIT7: + begin + ram_cmd <= `CMD_MRSET; + sdram_ba <= 2'b00; + sdram_a <= `MODE; + state <= `ST_INIT8; + end + `ST_INIT8: + begin + ram_cmd <= `CMD_NOP; + ram_dqm <= 2'b00; + count <= `T_MRD - 2; + state <= `ST_IDLE; + end + //---------------------------- + // idle + //---------------------------- + `ST_IDLE: + begin + if (refflg) begin + // refresh request + ram_cmd <= `CMD_ARFRS; + state <= `ST_RFRSH; + refrst <= 1; + end else begin + if (data_stb) begin + if (data_addr_out_of_range) begin + // illegal data address + ram_cmd <= `CMD_NOP; + state <= `ST_ILLDA0; + end else begin + // data address is ok + if (data_we) begin + // data write request + ram_cmd <= `CMD_ACTV; + sdram_ba <= data_addr[21:20]; + sdram_a <= data_addr[19:7]; + state <= `ST_WRDATA0; + end else begin + // data read request + ram_cmd <= `CMD_ACTV; + sdram_ba <= data_addr[21:20]; + sdram_a <= data_addr[19:7]; + state <= `ST_RDDATA0; + end + end + end else begin + if (inst_stb) begin + if (inst_addr_out_of_range) begin + // illegal inst address + ram_cmd <= `CMD_NOP; + state <= `ST_ILLIA0; + end else begin + // inst address is ok + // inst read request + ram_cmd <= `CMD_ACTV; + sdram_ba <= inst_addr[21:20]; + sdram_a <= inst_addr[19:7]; + state <= `ST_RDINST0; + end + end else begin + // no request + ram_cmd <= `CMD_NOP; + state <= `ST_IDLE; + end + end + end + end + //---------------------------- + // refresh + //---------------------------- + `ST_RFRSH: + begin + ram_cmd <= `CMD_NOP; + count <= `T_RFC - 2; + state <= `ST_IDLE; + refrst <= 0; + end + //---------------------------- + // write data + //---------------------------- + `ST_WRDATA0: + begin + ram_cmd <= `CMD_NOP; + count <= `T_RCD - 2; + state <= `ST_WRDATA1; + end + `ST_WRDATA1: + begin + ram_cnt <= 0; + ram_de <= 1; + ram_cmd <= `CMD_WRITE; + sdram_ba <= data_addr[21:20]; + sdram_a <= { 6'b0010, data_addr[6:0], 2'b00 }; + state <= `ST_WRDATA2; + end + `ST_WRDATA2: + begin + ram_cnt <= ram_cnt + 1; + ram_cmd <= `CMD_NOP; + count <= 2; + state <= `ST_WRDATA3; + end + `ST_WRDATA3: + begin + data_ack <= 1; + ram_de <= 0; + ram_cmd <= `CMD_NOP; + state <= `ST_WRDATA4; + end + `ST_WRDATA4: + begin + data_ack <= 0; + ram_cmd <= `CMD_NOP; + count <= 2; + state <= `ST_IDLE; + end + //---------------------------- + // read data + //---------------------------- + `ST_RDDATA0: + begin + ram_cmd <= `CMD_NOP; + count <= `T_RCD - 2; + state <= `ST_RDDATA1; + end + `ST_RDDATA1: + begin + ram_cmd <= `CMD_READ; + sdram_ba <= data_addr[21:20]; + sdram_a <= { 6'b0010, data_addr[6:0], 2'b00 }; + state <= `ST_RDDATA2; + end + `ST_RDDATA2: + begin + ram_cmd <= `CMD_NOP; + count <= 1; + state <= `ST_RDDATA3; + end + `ST_RDDATA3: + begin + ram_cnt <= 0; + data_ld <= 1; + ram_cmd <= `CMD_NOP; + count <= 3; + state <= `ST_RDDATA4; + end + `ST_RDDATA4: + begin + data_ack <= 1; + data_ld <= 0; + ram_cmd <= `CMD_NOP; + state <= `ST_RDDATA5; + end + `ST_RDDATA5: + begin + data_ack <= 0; + ram_cmd <= `CMD_NOP; + count <= 3; + state <= `ST_IDLE; + end + //---------------------------- + // read inst + //---------------------------- + `ST_RDINST0: + begin + ram_cmd <= `CMD_NOP; + count <= `T_RCD - 2; + state <= `ST_RDINST1; + end + `ST_RDINST1: + begin + ram_cmd <= `CMD_READ; + sdram_ba <= inst_addr[21:20]; + sdram_a <= { 6'b0010, inst_addr[6:0], 2'b00 }; + state <= `ST_RDINST2; + end + `ST_RDINST2: + begin + ram_cmd <= `CMD_NOP; + count <= 1; + state <= `ST_RDINST3; + end + `ST_RDINST3: + begin + ram_cnt <= 0; + data_ld <= 1; + ram_cmd <= `CMD_NOP; + count <= 3; + state <= `ST_RDINST4; + end + `ST_RDINST4: + begin + inst_ack <= 1; + data_ld <= 0; + ram_cmd <= `CMD_NOP; + state <= `ST_RDINST5; + end + `ST_RDINST5: + begin + inst_ack <= 0; + ram_cmd <= `CMD_NOP; + count <= 3; + state <= `ST_IDLE; + end + //---------------------------- + // illegal data address + //---------------------------- + `ST_ILLDA0: + begin + data_timeout <= 1; + ram_cmd <= `CMD_NOP; + state <= `ST_ILLDA1; + end + `ST_ILLDA1: + begin + data_timeout <= 0; + ram_cmd <= `CMD_NOP; + state <= `ST_IDLE; + end + //---------------------------- + // illegal inst address + //---------------------------- + `ST_ILLIA0: + begin + inst_timeout <= 1; + ram_cmd <= `CMD_NOP; + state <= `ST_ILLIA1; + end + `ST_ILLIA1: + begin + inst_timeout <= 0; + ram_cmd <= `CMD_NOP; + state <= `ST_IDLE; + end + //---------------------------- + // not used + //---------------------------- + default: + begin + inst_ack <= 0; + inst_timeout <= 0; + data_ack <= 0; + data_timeout <= 0; + sdram_cke <= 0; + sdram_cs_n <= 1; + ram_cnt <= 0; + ram_de <= 0; + data_ld <= 0; + ram_cmd <= `CMD_NOP; + ram_dqm <= 2'b11; + count <= `T_INIT0 - 1; + state <= `ST_INIT0; + refrst <= 0; + end + endcase + end + end + end + + // + // refresh counter + // + + always @(posedge clk or negedge clk_ok) begin + if (~clk_ok) begin + refcnt <= 10'd0; + end else begin + if (refcnt == 10'd0) begin + refcnt <= `REFCNT; + refflg <= 1; + end else begin + refcnt <= refcnt - 1; + if (refrst) begin + refflg <= 0; + end + end + end + end + +endmodule Index: fpga/experiments/memctrl/fpga/memctrl-1/src/toplevel/memtest.v =================================================================== --- fpga/experiments/memctrl/fpga/memctrl-1/src/toplevel/memtest.v (nonexistent) +++ fpga/experiments/memctrl/fpga/memctrl-1/src/toplevel/memtest.v (revision 318) @@ -0,0 +1,137 @@ +// +// memtest.v -- top-level for memory test +// + + +`timescale 1ns/10ps +`default_nettype none + + +module memtest(clk_in, + rst_inout_n, + sdram_clk, + sdram_fb, + sdram_cke, + sdram_cs_n, + sdram_ras_n, + sdram_cas_n, + sdram_we_n, + sdram_ba, + sdram_a, + sdram_udqm, + sdram_ldqm, + sdram_dq, + ssl); + + // clock and reset + input clk_in; + inout rst_inout_n; + // SDRAM + output sdram_clk; + input sdram_fb; + output sdram_cke; + output sdram_cs_n; + output sdram_ras_n; + output sdram_cas_n; + output sdram_we_n; + output [1:0] sdram_ba; + output [12:0] sdram_a; + output sdram_udqm; + output sdram_ldqm; + inout [15:0] sdram_dq; + // 7 segment LED output + output [6:0] ssl; + + // clk_rst + wire clk_ok; + wire clk; + wire rst; + // ramctrl + wire inst_stb; + wire [25:0] inst_addr; + wire [63:0] inst_to_test; + wire inst_ack; + wire inst_timeout; + wire data_stb; + wire data_we; + wire [25:0] data_addr; + wire [63:0] data_to_ram; + wire [63:0] data_to_test; + wire data_ack; + wire data_timeout; + // ramtest + wire test_ended; + wire test_error; + reg [25:0] heartbeat; + + // + // module instances + // + + clk_rst clk_rst_1( + .clk_in(clk_in), + .rst_inout_n(rst_inout_n), + .sdram_clk(sdram_clk), + .sdram_fb(sdram_fb), + .clk_ok(clk_ok), + .clk(clk), + .rst(rst) + ); + + ramctrl ramctrl_1( + .clk_ok(clk_ok), + .clk(clk), + .inst_stb(inst_stb), + .inst_addr({ test_ended ^ inst_addr[25], inst_addr[24:0] }), + .inst_dout(inst_to_test[63:0]), + .inst_ack(inst_ack), + .inst_timeout(inst_timeout), + .data_stb(data_stb), + .data_we(data_we), + .data_addr({ test_ended ^ data_addr[25], data_addr[24:0] }), + .data_din(data_to_ram[63:0]), + .data_dout(data_to_test[63:0]), + .data_ack(data_ack), + .data_timeout(data_timeout), + .sdram_cke(sdram_cke), + .sdram_cs_n(sdram_cs_n), + .sdram_ras_n(sdram_ras_n), + .sdram_cas_n(sdram_cas_n), + .sdram_we_n(sdram_we_n), + .sdram_ba(sdram_ba[1:0]), + .sdram_a(sdram_a[12:0]), + .sdram_udqm(sdram_udqm), + .sdram_ldqm(sdram_ldqm), + .sdram_dq(sdram_dq[15:0]) + ); + + ramtest ramtest_1( + .clk(clk), + .rst(rst), + .inst_stb(inst_stb), + .inst_addr(inst_addr[25:0]), + .inst_din(inst_to_test[63:0]), + .inst_ack(inst_ack | inst_timeout), + .data_stb(data_stb), + .data_we(data_we), + .data_addr(data_addr[25:0]), + .data_dout(data_to_ram[63:0]), + .data_din(data_to_test[63:0]), + .data_ack(data_ack | data_timeout), + .test_ended(test_ended), + .test_error(test_error) + ); + + always @(posedge clk) begin + heartbeat <= heartbeat + 1; + end + + assign ssl[0] = heartbeat[25]; + assign ssl[1] = clk_ok; + assign ssl[2] = rst; + assign ssl[3] = 0; + assign ssl[4] = test_ended; + assign ssl[5] = test_error; + assign ssl[6] = 0; + +endmodule Index: fpga/experiments/memctrl/fpga/memctrl-1/src/toplevel/memtest.ucf =================================================================== --- fpga/experiments/memctrl/fpga/memctrl-1/src/toplevel/memtest.ucf (nonexistent) +++ fpga/experiments/memctrl/fpga/memctrl-1/src/toplevel/memtest.ucf (revision 318) @@ -0,0 +1,65 @@ +# +# memtest.ucf -- user constraints for XSA-3S1000 + XST-3 board +# + +# +# clock and reset +# +NET "clk_in" PERIOD = 10.0ns HIGH 40%; +NET "clk_in" LOC = "t9"; +NET "rst_inout_n" LOC = "d15"; + +# +# SDRAM +# +NET "sdram_clk" LOC = "e10"; +NET "sdram_fb" LOC = "n8"; +NET "sdram_cke" LOC = "d7"; +NET "sdram_cs_n" LOC = "b8"; +NET "sdram_ras_n" LOC = "a9"; +NET "sdram_cas_n" LOC = "a10"; +NET "sdram_we_n" LOC = "b10"; +NET "sdram_ba<1>" LOC = "c7"; +NET "sdram_ba<0>" LOC = "a7"; +NET "sdram_a<12>" LOC = "c6"; +NET "sdram_a<11>" LOC = "c5"; +NET "sdram_a<10>" LOC = "b6"; +NET "sdram_a<9>" LOC = "a3"; +NET "sdram_a<8>" LOC = "c2"; +NET "sdram_a<7>" LOC = "d3"; +NET "sdram_a<6>" LOC = "e4"; +NET "sdram_a<5>" LOC = "c1"; +NET "sdram_a<4>" LOC = "e3"; +NET "sdram_a<3>" LOC = "e6"; +NET "sdram_a<2>" LOC = "b4"; +NET "sdram_a<1>" LOC = "a4"; +NET "sdram_a<0>" LOC = "b5"; +NET "sdram_udqm" LOC = "d9"; +NET "sdram_ldqm" LOC = "c10"; +NET "sdram_dq<15>" LOC = "f13"; +NET "sdram_dq<14>" LOC = "f12"; +NET "sdram_dq<13>" LOC = "c16"; +NET "sdram_dq<12>" LOC = "d14"; +NET "sdram_dq<11>" LOC = "b14"; +NET "sdram_dq<10>" LOC = "c12"; +NET "sdram_dq<9>" LOC = "b12"; +NET "sdram_dq<8>" LOC = "b11"; +NET "sdram_dq<7>" LOC = "d10"; +NET "sdram_dq<6>" LOC = "c11"; +NET "sdram_dq<5>" LOC = "a12"; +NET "sdram_dq<4>" LOC = "d11"; +NET "sdram_dq<3>" LOC = "b13"; +NET "sdram_dq<2>" LOC = "a14"; +NET "sdram_dq<1>" LOC = "d12"; +NET "sdram_dq<0>" LOC = "c15"; + +# +# 7 segment LED +# +NET "ssl<6>" LOC = "r10"; +NET "ssl<5>" LOC = "t7"; +NET "ssl<4>" LOC = "p10"; +NET "ssl<3>" LOC = "r7"; +NET "ssl<2>" LOC = "n6"; +NET "ssl<1>" LOC = "m11"; +NET "ssl<0>" LOC = "m6"; Index: fpga/experiments/memctrl/fpga/memctrl-1/Makefile =================================================================== --- fpga/experiments/memctrl/fpga/memctrl-1/Makefile (nonexistent) +++ fpga/experiments/memctrl/fpga/memctrl-1/Makefile (revision 318) @@ -0,0 +1,19 @@ +# +# Makefile for memory test on XESS XSA-XST-3 board +# + +BUILD = ../../../../../build + +.PHONY: all install clean + +all: build/memtest.bit + +install: build/memtest.bit + +clean: + mv build/memtest.xise . + mv build/memtest.bit . + rm -rf build/* + mv memtest.xise build + mv memtest.bit build + rm -f *~