OpenCores

/trunk/sim/rtl_sim/ncsim_sim/bin/sim.nc File deleted

/trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll

trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/sim/rtl_sim/ncsim_sim/bin/cds.lib =================================================================== --- trunk/sim/rtl_sim/ncsim_sim/bin/cds.lib (revision 6) +++ trunk/sim/rtl_sim/ncsim_sim/bin/cds.lib (nonexistent) @@ -1,2 +0,0 @@ -DEFINE work ./worknc -INCLUDE /root/home/lib/cds.lib Index: trunk/sim/rtl_sim/ncsim_sim/bin/hdl.var =================================================================== --- trunk/sim/rtl_sim/ncsim_sim/bin/hdl.var (revision 6) +++ trunk/sim/rtl_sim/ncsim_sim/bin/hdl.var (nonexistent) @@ -1 +0,0 @@ -DEFINE WORK work Index: trunk/sim/rtl_sim/ncsim_sim/bin/vlog.list =================================================================== --- trunk/sim/rtl_sim/ncsim_sim/bin/vlog.list (revision 6) +++ trunk/sim/rtl_sim/ncsim_sim/bin/vlog.list (nonexistent) @@ -1,38 +0,0 @@ -../../../../rtl/verilog/TECH/CLK_SWITCH.v -../../../../rtl/verilog/TECH/CLK_DIV2.v -../../../../rtl/verilog/TECH/duram.v -../../../../rtl/verilog/TECH/afifo.v - -../../../../rtl/verilog/MAC_tx/MAC_tx_FF.v -../../../../rtl/verilog/MAC_tx/Ramdon_gen.v -../../../../rtl/verilog/MAC_tx/CRC_gen.v -../../../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v -../../../../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v -../../../../rtl/verilog/MAC_tx/flow_ctrl.v - -../../../../rtl/verilog/MAC_rx/CRC_chk.v -../../../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v -../../../../rtl/verilog/MAC_rx/MAC_rx_FF.v -../../../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v -../../../../rtl/verilog/MAC_rx/Broadcast_filter.v - -../../../../rtl/verilog/miim/eth_clockgen.v -../../../../rtl/verilog/miim/eth_outputcontrol.v -../../../../rtl/verilog/miim/eth_shiftreg.v - -../../../../rtl/verilog/RMON/RMON_addr_gen.v -../../../../rtl/verilog/RMON/RMON_ctrl.v -../../../../rtl/verilog/RMON/RMON_dpram.v - -../../../../rtl/verilog/RMON.v -../../../../rtl/verilog/MAC_rx.v -../../../../rtl/verilog/MAC_tx.v -../../../../rtl/verilog/eth_miim.v -../../../../rtl/verilog/MAC_top.v -../../../../rtl/verilog/Phy_int.v -../../../../rtl/verilog/Clk_ctrl.v - -../../../../bench/verilog/Phy_sim.v -../../../../bench/verilog/User_int_sim.v -../../../../bench/verilog/reg_int_sim.v -../../../../bench/verilog/tb_top.v \ No newline at end of file Index: trunk/sim/rtl_sim/ncsim_sim/bin/config.ini =================================================================== --- trunk/sim/rtl_sim/ncsim_sim/bin/config.ini (revision 6) +++ trunk/sim/rtl_sim/ncsim_sim/bin/config.ini (nonexistent) @@ -1,3 +0,0 @@ -46,1500,1,0 - -#Pkt_begin_length,Pkt_end_length,Pkt_number,Random_en Index: trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll =================================================================== --- trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll (revision 6) +++ trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll (nonexistent)

trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/syn/syn.prj =================================================================== --- trunk/syn/syn.prj (revision 6) +++ trunk/syn/syn.prj (nonexistent) @@ -1,88 +0,0 @@ -#-- Synplicity, Inc. -#-- Version Synplify Pro 8.1 -#-- Project file D:\root\home\primitive\primitive_tri_mode_mac(NA)\syn\syn.prj -#-- Written on Mon Dec 05 14:10:50 2005 - - -#add_file options -add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v" -add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v" -add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v" -add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v" -add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v" -add_file -verilog "../rtl/verilog/MAC_tx/flow_ctrl.v" -add_file -verilog "../rtl/verilog/MAC_rx/CRC_chk.v" -add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_add_chk.v" -add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_FF.v" -add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v" -add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v" -add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v" -add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v" -add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v" -add_file -verilog "../cores/afifo.v" -add_file -verilog "../cores/duram.v" -add_file -verilog "../rtl/verilog/RMON.v" -add_file -verilog "../rtl/verilog/MAC_rx.v" -add_file -verilog "../rtl/verilog/MAC_tx.v" -add_file -verilog "../rtl/verilog/miim/eth_clockgen.v" -add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v" -add_file -verilog "../rtl/verilog/miim/eth_shiftreg.v" -add_file -verilog "../rtl/verilog/miim/timescale.v" -add_file -verilog "../rtl/verilog/TECH/CLK_SWITCH.v" -add_file -verilog "../rtl/verilog/TECH/CLK_DIV2.v" -add_file -verilog "../rtl/verilog/eth_miim.v" -add_file -verilog "../rtl/verilog/Clk_ctrl.v" -add_file -verilog "../rtl/verilog/Phy_int.v" -add_file -verilog "../rtl/verilog/MAC_top.v" - - -#implementation: "syn" -impl -add syn - -#device options -set_option -technology STRATIX -set_option -part EP1S10 -set_option -package FC780 -set_option -speed_grade -5 - -#compilation/mapping options -set_option -default_enum_encoding onehot -set_option -symbolic_fsm_compiler 0 -set_option -resource_sharing 1 -set_option -use_fsm_explorer 0 - -#map options -set_option -frequency auto -set_option -run_prop_extract 0 -set_option -fanout_limit 500 -set_option -disable_io_insertion 0 -set_option -pipe 1 -set_option -update_models_cp 0 -set_option -retiming 0 -set_option -verification_mode 0 -set_option -fixgatedclocks 0 -set_option -no_sequential_opt 0 - -#simulation options -set_option -write_verilog 1 -set_option -write_vhdl 0 - -#VIF options -set_option -write_vif 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 0 - -#set result format/file last -project -result_file "./MAC_top.vqm" - -# -#implementation attributes - -set_option -vlog_std v2001 -set_option -project_relative_includes 1 - -#par_1 attributes -set_option -job par_1 -add par -set_option -job par_1 -option run_backannotation 0 -impl -active "syn" Index: trunk/bench/verilog/User_int_sim.v =================================================================== --- trunk/bench/verilog/User_int_sim.v (revision 6) +++ trunk/bench/verilog/User_int_sim.v (nonexistent) @@ -1,121 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// User_input_sim.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// -//// //// -//// Author(s): //// -//// - Jon Gao (gaojon@yahoo.com) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// -// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator -// no message -// -module User_int_sim ( -input Reset , -input Clk_user , - //user inputerface -input Rx_mac_ra , -output Rx_mac_rd , -input [31:0] Rx_mac_data , -input [1:0] Rx_mac_BE , -input Rx_mac_pa , -input Rx_mac_sop , -input Rx_mac_eop , - //user inputerface -input Tx_mac_wa , -output Tx_mac_wr , -output [31:0] Tx_mac_data , -output [1:0] Tx_mac_BE ,//big endian -output Tx_mac_sop , -output Tx_mac_eop -); -////////////////////////////////////////////////////////////////////// -// inputernal signals -////////////////////////////////////////////////////////////////////// -reg[4:0] operation; -reg[31:0] data; -reg Rx_mac_rd; -reg Start_tran; -////////////////////////////////////////////////////////////////////// -//generate Tx user data -////////////////////////////////////////////////////////////////////// -initial - begin - operation =0; - data =0; - end - -always @ (posedge Clk_user or posedge Reset) - if (Reset) - Start_tran <=0; - else if (Tx_mac_eop&&!Tx_mac_wa) - Start_tran <=0; - else if (Tx_mac_wa) - Start_tran <=1; - - -always @ (posedge Clk_user ) - if (Tx_mac_wa) - $ip_32W_gen("config.ini",operation,data); - else - begin - operation <=0; - data <=0; - end - -assign Tx_mac_data =data; -assign Tx_mac_wr =operation[4]; -assign Tx_mac_sop =operation[3]; -assign Tx_mac_eop =operation[2]; -assign Tx_mac_BE =operation[1:0]; -////////////////////////////////////////////////////////////////////// -//verify Rx user data -////////////////////////////////////////////////////////////////////// -always @ (posedge Clk_user or posedge Reset) - if (Reset) - Rx_mac_rd <=0; - else if(Rx_mac_ra) - Rx_mac_rd <=1; - else - Rx_mac_rd <=0; - - -always @ (posedge Clk_user ) - if (Rx_mac_pa) - $ip_32W_check( Rx_mac_data, - {Rx_mac_sop,Rx_mac_eop,Rx_mac_eop?Rx_mac_BE:2'b0}); - -endmodule - \ No newline at end of file Index: trunk/bench/verilog/reg_int_sim.v =================================================================== --- trunk/bench/verilog/reg_int_sim.v (revision 6) +++ trunk/bench/verilog/reg_int_sim.v (nonexistent) @@ -1,132 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// reg_int_sim.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// -//// //// -//// Author(s): //// -//// - Jon Gao (gaojon@yahoo.com) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ - -module reg_int_sim ( -input Reset , -input Clk_reg , - //Tx host interface -output [4:0] Tx_Hwmark , -output [4:0] Tx_Lwmark , -output pause_frame_send_en , -output [15:0] pause_quanta_set , -output MAC_tx_add_en , -output FullDuplex , -output [3:0] MaxRetry , -output [5:0] IFGset , -output [7:0] MAC_tx_add_prom_data , -output [2:0] MAC_tx_add_prom_add , -output MAC_tx_add_prom_wr , -output tx_pause_en , -output xoff_cpu , -output xon_cpu , - //Rx host interface -output MAC_rx_add_chk_en , -output [7:0] MAC_rx_add_prom_data , -output [2:0] MAC_rx_add_prom_add , -output MAC_rx_add_prom_wr , -output broadcast_filter_en , -output [15:0] broadcast_MAX , -output RX_APPEND_CRC , -output CRC_chk_en , -output [5:0] RX_IFG_SET , -output [15:0] RX_MAX_LENGTH ,// 1518 -output [6:0] RX_MIN_LENGTH ,// 64 - //RMON host interface -output [5:0] CPU_rd_addr , -output CPU_rd_apply , -input CPU_rd_grant , -input [31:0] CPU_rd_dout , - //Phy int host interface -output Line_loop_en , -output [2:0] Speed , - //MII to CPU -output [7:0] Divider ,// Divider for the host clock -output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.) -output [4:0] Rgad ,// Register Address (within the PHY) -output [4:0] Fiad ,// PHY Address -output NoPre ,// No Preamble (no 32-bit preamble) -output WCtrlData ,// Write Control Data operation -output RStat ,// Read Status operation -output ScanStat ,// Scan Status operation -input Busy ,// Busy Signal -input LinkFail ,// Link Integrity Signal -input Nvalid ,// Invalid Status (qualifier for the valid scan result) -input [15:0] Prsd ,// Read Status Data (data read from the PHY) -input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register -input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register -input UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data -); - -assign Tx_Hwmark =5'h1e; -assign Tx_Lwmark =5'h19; -assign pause_frame_send_en =0; -assign pause_quanta_set =0; -assign MAC_tx_add_en =0; -assign FullDuplex =1; -assign MaxRetry =2; -assign IFGset =10; -assign MAC_tx_add_prom_data =0; -assign MAC_tx_add_prom_add =0; -assign MAC_tx_add_prom_wr =0; -assign tx_pause_en =0; -assign xoff_cpu =0; -assign xon_cpu =0; - -assign MAC_rx_add_chk_en =0; -assign MAC_rx_add_prom_data =0; -assign MAC_rx_add_prom_add =0; -assign MAC_rx_add_prom_wr =0; -assign broadcast_filter_en =0; -assign broadcast_MAX =10; -assign RX_APPEND_CRC =0; -assign CRC_chk_en =1; -assign RX_IFG_SET =10; -assign RX_MAX_LENGTH =1518; -assign RX_MIN_LENGTH =64; - -assign CPU_rd_addr =0; -assign CPU_rd_apply =0; - -assign Line_loop_en =0; -assign Speed =3'b001; - -endmodule \ No newline at end of file Index: trunk/bench/verilog/Phy_sim.v =================================================================== --- trunk/bench/verilog/Phy_sim.v (revision 6) +++ trunk/bench/verilog/Phy_sim.v (nonexistent) @@ -1,96 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Phy_sim.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// -//// //// -//// Author(s): //// -//// - Jon Gao (gaojon@yahoo.com) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator -// no message -// - -`timescale 1ns/100ps - -module Phy_sim ( -input Gtx_clk ,//used only in GMII mode -output Rx_clk , -output Tx_clk ,//used only in MII mode -input Tx_er , -input Tx_en , -input [7:0] Txd , -output Rx_er , -output Rx_dv , -output [7:0] Rxd , -output Crs , -output Col , -input [2:0] Speed -); -////////////////////////////////////////////////////////////////////// -// this file used to simulate Phy. -// generate clk and loop the Tx data to Rx data -// full duplex mode can be verified on loop mode. -////////////////////////////////////////////////////////////////////// -////////////////////////////////////////////////////////////////////// -// internal signals -////////////////////////////////////////////////////////////////////// -reg Clk_25m ;//used for 100 Mbps mode -reg Clk_2_5m ;//used for 10 Mbps mode -wire Rx_clk ; -wire Tx_clk ;//used only in MII mode -////////////////////////////////////////////////////////////////////// -always - begin - #20 Clk_25m=0; - #20 Clk_25m=1; - end - -always - begin - #200 Clk_2_5m=0; - #200 Clk_2_5m=1; - end - -assign Rx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0; -assign Tx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0; - -assign Rx_dv =Tx_en ; -assign Rxd =Txd ; -assign Rx_er =0 ; -assign Crs =Tx_en ; -assign Col =0 ; - -endmodule \ No newline at end of file Index: trunk/bench/verilog/tb_top.v =================================================================== --- trunk/bench/verilog/tb_top.v (revision 6) +++ trunk/bench/verilog/tb_top.v (revision 5) @@ -1,7 +1,6 @@ -`timescale 1 ns/100ps ////////////////////////////////////////////////////////////////////// //// //// -//// tb_top.v //// +//// tb_top.v //// //// //// //// This file is part of the Ethernet IP core project //// //// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// @@ -39,10 +38,7 @@ // // CVS Revision History // -// $Log: not supported by cvs2svn $ -// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator -// no message -// +// $Log: not supported by cvs2svn $ module tb_top ( ); @@ -50,135 +46,104 @@ //internal signals //****************************************************************************** //system signals -reg Reset ; -reg Clk_125M ; -reg Clk_user ; -reg Clk_reg ; +input Reset , +input Clk_125M , +input Clk_user , +input Clk_reg , //user interface -wire Rx_mac_ra ; -wire Rx_mac_rd ; -wire [31:0] Rx_mac_data ; -wire [1:0] Rx_mac_BE ; -wire Rx_mac_pa ; -wire Rx_mac_sop ; -wire Rx_mac_eop ; +output Rx_mac_ra , +input Rx_mac_rd , +output [31:0] Rx_mac_data , +output [1:0] Rx_mac_BE , +output Rx_mac_pa , +output Rx_mac_sop , +output Rx_mac_eop , //user interface -wire Tx_mac_wa ; -wire Tx_mac_wr ; -wire [31:0] Tx_mac_data ; -wire [1:0] Tx_mac_BE ;//big endian -wire Tx_mac_sop ; -wire Tx_mac_eop ; +output Tx_mac_wa , +input Tx_mac_wr , +input [31:0] Tx_mac_data , +input [1:0] Tx_mac_BE ,//big endian +input Tx_mac_sop , +input Tx_mac_eop , //Phy interface //Phy interface -wire Gtx_clk ;//used only in GMII mode -wire Rx_clk ; -wire Tx_clk ;//used only in MII mode -wire Tx_er ; -wire Tx_en ; -wire [7:0] Txd ; -wire Rx_er ; -wire Rx_dv ; -wire [7:0] Rxd ; -wire Crs ; -wire Col ; +output Gtx_clk ,//used only in GMII mode +input Rx_clk , +input Tx_clk ,//used only in MII mode +output Tx_er , +output Tx_en , +output [7:0] Txd , +input Rx_er , +input Rx_dv , +input [7:0] Rxd , +input Crs , +input Col , //Tx host interface -wire [4:0] Tx_Hwmark ; -wire [4:0] Tx_Lwmark ; -wire pause_frame_send_en ; -wire [15:0] pause_quanta_set ; -wire MAC_tx_add_en ; -wire FullDuplex ; -wire [3:0] MaxRetry ; -wire [5:0] IFGset ; -wire [7:0] MAC_tx_add_prom_data ; -wire [2:0] MAC_tx_add_prom_add ; -wire MAC_tx_add_prom_wr ; -wire tx_pause_en ; -wire xoff_cpu ; -wire xon_cpu ; +input [4:0] Tx_Hwmark , +input [4:0] Tx_Lwmark , +input pause_frame_send_en , +input [15:0] pause_quanta_set , +input MAC_tx_add_en , +input FullDuplex , +input [3:0] MaxRetry , +input [5:0] IFGset , +input [7:0] MAC_tx_add_prom_data , +input [2:0] MAC_tx_add_prom_add , +input MAC_tx_add_prom_wr , +input tx_pause_en , +input xoff_cpu , +input xon_cpu , //Rx host interface -wire MAC_rx_add_chk_en ; -wire [7:0] MAC_rx_add_prom_data ; -wire [2:0] MAC_rx_add_prom_add ; -wire MAC_rx_add_prom_wr ; -wire broadcast_filter_en ; -wire [15:0] broadcast_MAX ; -wire RX_APPEND_CRC ; -wire CRC_chk_en ; -wire [5:0] RX_IFG_SET ; -wire [15:0] RX_MAX_LENGTH ;// 1518 -wire [6:0] RX_MIN_LENGTH ;// 64 +input MAC_rx_add_chk_en , +input [7:0] MAC_rx_add_prom_data , +input [2:0] MAC_rx_add_prom_add , +input MAC_rx_add_prom_wr , +input broadcast_filter_en , +input [15:0] broadcast_MAX , +input RX_APPEND_CRC , +input CRC_chk_en , +input [5:0] RX_IFG_SET , +input [15:0] RX_MAX_LENGTH ,// 1518 +input [6:0] RX_MIN_LENGTH ,// 64 //RMON host interface -wire [5:0] CPU_rd_addr ; -wire CPU_rd_apply ; -wire CPU_rd_grant ; -wire [31:0] CPU_rd_dout ; +input [5:0] CPU_rd_addr , +input CPU_rd_apply , +output CPU_rd_grant , +output [31:0] CPU_rd_dout , //Phy int host interface -wire Line_loop_en ; -wire [2:0] Speed ; +input Line_loop_en , +input [2:0] Speed , //MII to CPU -wire [7:0] Divider ;// Divider for the host clock -wire [15:0] CtrlData ;// Control Data (to be written to the PHY reg.) -wire [4:0] Rgad ;// Register Address (within the PHY) -wire [4:0] Fiad ;// PHY Address -wire NoPre ;// No Preamble (no 32-bit preamble) -wire WCtrlData ;// Write Control Data operation -wire RStat ;// Read Status operation -wire ScanStat ;// Scan Status operation -wire Busy ;// Busy Signal -wire LinkFail ;// Link Integrity Signal -wire Nvalid ;// Invalid Status (qualifier for the valid scan result) -wire [15:0] Prsd ;// Read Status Data (data read from the PHY) -wire WCtrlDataStart ;// This signals resets the WCTRLDATA bit in the MIIM Command register -wire RStatStart ;// This signal resets the RSTAT BIT in the MIIM Command register -wire UpdateMIIRX_DATAReg ;// Updates MII RX_DATA register with read data +input [7:0] Divider ,// Divider for the host clock +input [15:0] CtrlData ,// Control Data (to be written to the PHY reg.) +input [4:0] Rgad ,// Register Address (within the PHY) +input [4:0] Fiad ,// PHY Address +input NoPre ,// No Preamble (no 32-bit preamble) +input WCtrlData ,// Write Control Data operation +input RStat ,// Read Status operation +input ScanStat ,// Scan Status operation +output Busy ,// Busy Signal +output LinkFail ,// Link Integrity Signal +output Nvalid ,// Invalid Status (qualifier for the valid scan result) +output [15:0] Prsd ,// Read Status Data (data read from the PHY) +output WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register +output RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register +output UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data //MII interface signals -wire Mdio ;// MII Management Data In -wire Mdc ;// MII Management Data Clock +inout Mdio ,// MII Management Data In +output Mdc ,// MII Management Data Clock //****************************************************************************** //internal signals //****************************************************************************** -initial - begin - Reset =1; - #20 Reset =0; - end -always - begin - #4 Clk_125M=0; - #4 Clk_125M=1; - end - -always - begin - #5 Clk_user=0; - #5 Clk_user=1; - end - -always - begin - #10 Clk_reg=0; - #10 Clk_reg=1; - end - - -initial - begin - $shm_open("tb_top.shm",,900000000,); - $shm_probe("AS"); - end - - MAC_top U_MAC_top( - //system signals (//system signals ), +.//system signals (//system signals ), .Reset (Reset ), .Clk_125M (Clk_125M ), .Clk_user (Clk_user ), .Clk_reg (Clk_reg ), - //user interface (//user interface ), +.//user interface (//user interface ), .Rx_mac_ra (Rx_mac_ra ), .Rx_mac_rd (Rx_mac_rd ), .Rx_mac_data (Rx_mac_data ), @@ -186,7 +151,7 @@ .Rx_mac_pa (Rx_mac_pa ), .Rx_mac_sop (Rx_mac_sop ), .Rx_mac_eop (Rx_mac_eop ), - //user interface (//user interface ), +.//user interface (//user interface ), .Tx_mac_wa (Tx_mac_wa ), .Tx_mac_wr (Tx_mac_wr ), .Tx_mac_data (Tx_mac_data ), @@ -193,8 +158,8 @@ .Tx_mac_BE (Tx_mac_BE ), .Tx_mac_sop (Tx_mac_sop ), .Tx_mac_eop (Tx_mac_eop ), - //Phy interface (//Phy interface ), - //Phy interface (//Phy interface ), +.//Phy interface (//Phy interface ), +.//Phy interface (//Phy interface ), .Gtx_clk (Gtx_clk ), .Rx_clk (Rx_clk ), .Tx_clk (Tx_clk ), @@ -206,7 +171,7 @@ .Rxd (Rxd ), .Crs (Crs ), .Col (Col ), - //Tx host interface (//Tx host interface ), +.//Tx host interface (//Tx host interface ), .Tx_Hwmark (Tx_Hwmark ), .Tx_Lwmark (Tx_Lwmark ), .pause_frame_send_en (pause_frame_send_en ), @@ -221,7 +186,7 @@ .tx_pause_en (tx_pause_en ), .xoff_cpu (xoff_cpu ), .xon_cpu (xon_cpu ), - //Rx host interface (//Rx host interface ), +.//Rx host interface (//Rx host interface ), .MAC_rx_add_chk_en (MAC_rx_add_chk_en ), .MAC_rx_add_prom_data (MAC_rx_add_prom_data ), .MAC_rx_add_prom_add (MAC_rx_add_prom_add ), @@ -233,15 +198,15 @@ .RX_IFG_SET (RX_IFG_SET ), .RX_MAX_LENGTH (RX_MAX_LENGTH ), .RX_MIN_LENGTH (RX_MIN_LENGTH ), - //RMON host interface (//RMON host interface ), +.//RMON host interface (//RMON host interface ), .CPU_rd_addr (CPU_rd_addr ), .CPU_rd_apply (CPU_rd_apply ), .CPU_rd_grant (CPU_rd_grant ), .CPU_rd_dout (CPU_rd_dout ), - //Phy int host interface (//Phy int host interface ), +.//Phy int host interface (//Phy int host interface ), .Line_loop_en (Line_loop_en ), .Speed (Speed ), - //MII to CPU (//MII to CPU ), +.//MII to CPU (//MII to CPU ), .Divider (Divider ), .CtrlData (CtrlData ), .Rgad (Rgad ), @@ -257,99 +222,10 @@ .WCtrlDataStart (WCtrlDataStart ), .RStatStart (RStatStart ), .UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ), - //MII interface signals (//MII interface signals ), +.//MII interface signals (//MII interface signals ), .Mdio (Mdio ), .Mdc (Mdc ) -); -Phy_sim U_Phy_sim ( -.Gtx_clk (Gtx_clk ), -.Rx_clk (Rx_clk ), -.Tx_clk (Tx_clk ), -.Tx_er (Tx_er ), -.Tx_en (Tx_en ), -.Txd (Txd ), -.Rx_er (Rx_er ), -.Rx_dv (Rx_dv ), -.Rxd (Rxd ), -.Crs (Crs ), -.Col (Col ), -.Speed (Speed ) -); -User_int_sim U_User_int_sim( -.Reset (Reset ), -.Clk_user (Clk_user ), - //user inputerface (//user inputerface ), -.Rx_mac_ra (Rx_mac_ra ), -.Rx_mac_rd (Rx_mac_rd ), -.Rx_mac_data (Rx_mac_data ), -.Rx_mac_BE (Rx_mac_BE ), -.Rx_mac_pa (Rx_mac_pa ), -.Rx_mac_sop (Rx_mac_sop ), -.Rx_mac_eop (Rx_mac_eop ), - //user inputerface (//user inputerface ), -.Tx_mac_wa (Tx_mac_wa ), -.Tx_mac_wr (Tx_mac_wr ), -.Tx_mac_data (Tx_mac_data ), -.Tx_mac_BE (Tx_mac_BE ), -.Tx_mac_sop (Tx_mac_sop ), -.Tx_mac_eop (Tx_mac_eop ) ); - -reg_int_sim U_reg_int_sim( -.Reset (Reset ), -.Clk_reg (Clk_reg ), - //Tx host interface (//Tx host interface ), -.Tx_Hwmark (Tx_Hwmark ), -.Tx_Lwmark (Tx_Lwmark ), -.pause_frame_send_en (pause_frame_send_en ), -.pause_quanta_set (pause_quanta_set ), -.MAC_tx_add_en (MAC_tx_add_en ), -.FullDuplex (FullDuplex ), -.MaxRetry (MaxRetry ), -.IFGset (IFGset ), -.MAC_tx_add_prom_data (MAC_tx_add_prom_data ), -.MAC_tx_add_prom_add (MAC_tx_add_prom_add ), -.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ), -.tx_pause_en (tx_pause_en ), -.xoff_cpu (xoff_cpu ), -.xon_cpu (xon_cpu ), - //Rx host interface (//Rx host interface ), -.MAC_rx_add_chk_en (MAC_rx_add_chk_en ), -.MAC_rx_add_prom_data (MAC_rx_add_prom_data ), -.MAC_rx_add_prom_add (MAC_rx_add_prom_add ), -.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ), -.broadcast_filter_en (broadcast_filter_en ), -.broadcast_MAX (broadcast_MAX ), -.RX_APPEND_CRC (RX_APPEND_CRC ), -.CRC_chk_en (CRC_chk_en ), -.RX_IFG_SET (RX_IFG_SET ), -.RX_MAX_LENGTH (RX_MAX_LENGTH ), -.RX_MIN_LENGTH (RX_MIN_LENGTH ), - //RMON host interface (//RMON host interface ), -.CPU_rd_addr (CPU_rd_addr ), -.CPU_rd_apply (CPU_rd_apply ), -.CPU_rd_grant (CPU_rd_grant ), -.CPU_rd_dout (CPU_rd_dout ), - //Phy int host interface (//Phy int host interface ), -.Line_loop_en (Line_loop_en ), -.Speed (Speed ), - //MII to CPU (//MII to CPU ), -.Divider (Divider ), -.CtrlData (CtrlData ), -.Rgad (Rgad ), -.Fiad (Fiad ), -.NoPre (NoPre ), -.WCtrlData (WCtrlData ), -.RStat (RStat ), -.ScanStat (ScanStat ), -.Busy (Busy ), -.LinkFail (LinkFail ), -.Nvalid (Nvalid ), -.Prsd (Prsd ), -.WCtrlDataStart (WCtrlDataStart ), -.RStatStart (RStatStart ), -.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ) -); endmodule

/trunk/rtl/verilog/MAC_tx.v

38,10 → 38,7