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/trunk/bench/verilog/tb_top.v
0,0 → 1,231
//////////////////////////////////////////////////////////////////////
//// ////
//// tb_top.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module tb_top (
);
//******************************************************************************
//internal signals
//******************************************************************************
//system signals
input Reset ,
input Clk_125M ,
input Clk_user ,
input Clk_reg ,
//user interface
output Rx_mac_ra ,
input Rx_mac_rd ,
output [31:0] Rx_mac_data ,
output [1:0] Rx_mac_BE ,
output Rx_mac_pa ,
output Rx_mac_sop ,
output Rx_mac_eop ,
//user interface
output Tx_mac_wa ,
input Tx_mac_wr ,
input [31:0] Tx_mac_data ,
input [1:0] Tx_mac_BE ,//big endian
input Tx_mac_sop ,
input Tx_mac_eop ,
//Phy interface
//Phy interface
output Gtx_clk ,//used only in GMII mode
input Rx_clk ,
input Tx_clk ,//used only in MII mode
output Tx_er ,
output Tx_en ,
output [7:0] Txd ,
input Rx_er ,
input Rx_dv ,
input [7:0] Rxd ,
input Crs ,
input Col ,
//Tx host interface
input [4:0] Tx_Hwmark ,
input [4:0] Tx_Lwmark ,
input pause_frame_send_en ,
input [15:0] pause_quanta_set ,
input MAC_tx_add_en ,
input FullDuplex ,
input [3:0] MaxRetry ,
input [5:0] IFGset ,
input [7:0] MAC_tx_add_prom_data ,
input [2:0] MAC_tx_add_prom_add ,
input MAC_tx_add_prom_wr ,
input tx_pause_en ,
input xoff_cpu ,
input xon_cpu ,
//Rx host interface
input MAC_rx_add_chk_en ,
input [7:0] MAC_rx_add_prom_data ,
input [2:0] MAC_rx_add_prom_add ,
input MAC_rx_add_prom_wr ,
input broadcast_filter_en ,
input [15:0] broadcast_MAX ,
input RX_APPEND_CRC ,
input CRC_chk_en ,
input [5:0] RX_IFG_SET ,
input [15:0] RX_MAX_LENGTH ,// 1518
input [6:0] RX_MIN_LENGTH ,// 64
//RMON host interface
input [5:0] CPU_rd_addr ,
input CPU_rd_apply ,
output CPU_rd_grant ,
output [31:0] CPU_rd_dout ,
//Phy int host interface
input Line_loop_en ,
input [2:0] Speed ,
//MII to CPU
input [7:0] Divider ,// Divider for the host clock
input [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
input [4:0] Rgad ,// Register Address (within the PHY)
input [4:0] Fiad ,// PHY Address
input NoPre ,// No Preamble (no 32-bit preamble)
input WCtrlData ,// Write Control Data operation
input RStat ,// Read Status operation
input ScanStat ,// Scan Status operation
output Busy ,// Busy Signal
output LinkFail ,// Link Integrity Signal
output Nvalid ,// Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd ,// Read Status Data (data read from the PHY)
output WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
//MII interface signals
inout Mdio ,// MII Management Data In
output Mdc ,// MII Management Data Clock
 
//******************************************************************************
//internal signals
//******************************************************************************
 
MAC_top U_MAC_top(
.//system signals (//system signals ),
.Reset (Reset ),
.Clk_125M (Clk_125M ),
.Clk_user (Clk_user ),
.Clk_reg (Clk_reg ),
.//user interface (//user interface ),
.Rx_mac_ra (Rx_mac_ra ),
.Rx_mac_rd (Rx_mac_rd ),
.Rx_mac_data (Rx_mac_data ),
.Rx_mac_BE (Rx_mac_BE ),
.Rx_mac_pa (Rx_mac_pa ),
.Rx_mac_sop (Rx_mac_sop ),
.Rx_mac_eop (Rx_mac_eop ),
.//user interface (//user interface ),
.Tx_mac_wa (Tx_mac_wa ),
.Tx_mac_wr (Tx_mac_wr ),
.Tx_mac_data (Tx_mac_data ),
.Tx_mac_BE (Tx_mac_BE ),
.Tx_mac_sop (Tx_mac_sop ),
.Tx_mac_eop (Tx_mac_eop ),
.//Phy interface (//Phy interface ),
.//Phy interface (//Phy interface ),
.Gtx_clk (Gtx_clk ),
.Rx_clk (Rx_clk ),
.Tx_clk (Tx_clk ),
.Tx_er (Tx_er ),
.Tx_en (Tx_en ),
.Txd (Txd ),
.Rx_er (Rx_er ),
.Rx_dv (Rx_dv ),
.Rxd (Rxd ),
.Crs (Crs ),
.Col (Col ),
.//Tx host interface (//Tx host interface ),
.Tx_Hwmark (Tx_Hwmark ),
.Tx_Lwmark (Tx_Lwmark ),
.pause_frame_send_en (pause_frame_send_en ),
.pause_quanta_set (pause_quanta_set ),
.MAC_tx_add_en (MAC_tx_add_en ),
.FullDuplex (FullDuplex ),
.MaxRetry (MaxRetry ),
.IFGset (IFGset ),
.MAC_tx_add_prom_data (MAC_tx_add_prom_data ),
.MAC_tx_add_prom_add (MAC_tx_add_prom_add ),
.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ),
.tx_pause_en (tx_pause_en ),
.xoff_cpu (xoff_cpu ),
.xon_cpu (xon_cpu ),
.//Rx host interface (//Rx host interface ),
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ),
.broadcast_filter_en (broadcast_filter_en ),
.broadcast_MAX (broadcast_MAX ),
.RX_APPEND_CRC (RX_APPEND_CRC ),
.CRC_chk_en (CRC_chk_en ),
.RX_IFG_SET (RX_IFG_SET ),
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
.//RMON host interface (//RMON host interface ),
.CPU_rd_addr (CPU_rd_addr ),
.CPU_rd_apply (CPU_rd_apply ),
.CPU_rd_grant (CPU_rd_grant ),
.CPU_rd_dout (CPU_rd_dout ),
.//Phy int host interface (//Phy int host interface ),
.Line_loop_en (Line_loop_en ),
.Speed (Speed ),
.//MII to CPU (//MII to CPU ),
.Divider (Divider ),
.CtrlData (CtrlData ),
.Rgad (Rgad ),
.Fiad (Fiad ),
.NoPre (NoPre ),
.WCtrlData (WCtrlData ),
.RStat (RStat ),
.ScanStat (ScanStat ),
.Busy (Busy ),
.LinkFail (LinkFail ),
.Nvalid (Nvalid ),
.Prsd (Prsd ),
.WCtrlDataStart (WCtrlDataStart ),
.RStatStart (RStatStart ),
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ),
.//MII interface signals (//MII interface signals ),
.Mdio (Mdio ),
.Mdc (Mdc )
 
 
);
endmodule
/trunk/rtl/verilog/MAC_tx.v
0,0 → 1,250
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_tx.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
module MAC_tx(
input Reset ,
input Clk ,
input Clk_user ,
//PHY interface
output[7:0] TxD ,
output TxEn ,
input CRS ,
//RMON
output[2:0] Tx_pkt_type_rmon ,
output[15:0] Tx_pkt_length_rmon ,
output Tx_apply_rmon ,
output[2:0] Tx_pkt_err_type_rmon,
//user interface
output Tx_mac_wa ,
input Tx_mac_wr ,
input[31:0] Tx_mac_data ,
input [1:0] Tx_mac_BE ,//big endian
input Tx_mac_sop ,
input Tx_mac_eop ,
//host interface
input[4:0] Tx_Hwmark ,
input[4:0] Tx_Lwmark ,
input pause_frame_send_en ,
input[15:0] pause_quanta_set ,
input MAC_tx_add_en ,
input FullDuplex ,
input[3:0] MaxRetry ,
input[5:0] IFGset ,
input[7:0] MAC_add_prom_data ,
input[2:0] MAC_add_prom_add ,
input MAC_add_prom_wr ,
input tx_pause_en ,
input xoff_cpu ,
input xon_cpu ,
//MAC_rx_flow ,
input [15:0] pause_quanta ,
input pause_quanta_val ,
);
//******************************************************************************
//internal signals
//******************************************************************************
//CRC_gen Interface
wire CRC_init ;
wire[7:0] Frame_data ;
wire Data_en ;
wire CRC_rd ;
wire CRC_end ;
wire[7:0] CRC_out ;
//Ramdon_gen interface
wire Random_init ;
wire[3:0] RetryCnt ;
wire Random_time_meet ;//levle hight indicate random time passed away
//flow control
wire pause_apply ;
wire pause_quanta_sub ;
wire xoff_gen ;
wire xoff_gen_complete ;
wire xon_gen ;
wire xon_gen_complete ;
//MAC_rx_FF
wire[7:0] Fifo_data ;
wire Fifo_rd ;
wire Fifo_eop ;
wire Fifo_da ;
wire Fifo_rd_finish ;
wire Fifo_rd_retry ;
wire Fifo_ra ;
wire Fifo_data_err_empty ;
wire Fifo_data_err_full ;
//MAC_tx_addr_add
wire MAC_tx_addr_init ;
wire MAC_tx_addr_rd ;
wire[7:0] MAC_tx_addr_data ;
 
//******************************************************************************
//instantiation
//******************************************************************************
MAC_tx_ctrl U_MAC_tx_ctrl(
.Reset (Reset ),
.Clk (Clk ),
//CRC_gen Interface (//CRC_gen Interface ),
.CRC_init (CRC_init ),
.Frame_data (Frame_data ),
.Data_en (Data_en ),
.CRC_rd (CRC_rd ),
.CRC_end (CRC_end ),
.CRC_out (CRC_out ),
//Ramdon_gen interfac (//Ramdon_gen interfac ),
.Random_init (Random_init ),
.RetryCnt (RetryCnt ),
.Random_time_meet (Random_time_meet ),
//flow control (//flow control ),
.pause_apply (pause_apply ),
.pause_quanta_sub (pause_quanta_sub ),
.xoff_gen (xoff_gen ),
.xoff_gen_complete (xoff_gen_complete ),
.xon_gen (xon_gen ),
.xon_gen_complete (xon_gen_complete ),
//MAC_tx_FF (//MAC_tx_FF ),
.Fifo_data (Fifo_data ),
.Fifo_rd (Fifo_rd ),
.Fifo_eop (Fifo_eop ),
.Fifo_da (Fifo_da ),
.Fifo_rd_finish (Fifo_rd_finish ),
.Fifo_rd_retry (Fifo_rd_retry ),
.Fifo_ra (Fifo_ra ),
.Fifo_data_err_empty (Fifo_data_err_empty ),
.Fifo_data_err_full (Fifo_data_err_full ),
//RMII (//RMII ),
.TxD (TxD ),
.TxEn (TxEn ),
.CRS (CRS ),
//MAC_tx_addr_add (//MAC_tx_addr_add ),
.MAC_tx_addr_rd (MAC_tx_addr_rd ),
.MAC_tx_addr_data (MAC_tx_addr_data ),
.MAC_tx_addr_init (MAC_tx_addr_init ),
//RMON (//RMON ),
.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),
.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),
.Tx_apply_rmon (Tx_apply_rmon ),
.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
//CPU (//CPU ),
.pause_frame_send_en (pause_frame_send_en ),
.pause_quanta_set (pause_quanta_set ),
.MAC_tx_add_en (MAC_tx_add_en ),
.FullDuplex (FullDuplex ),
.MaxRetry (MaxRetry ),
.IFGset (IFGset )
);
 
CRC_gen U_CRC_gen(
.Reset (Reset ),
.Clk (Clk ),
.Init (CRC_init ),
.Frame_data (Frame_data ),
.Data_en (Data_en ),
.CRC_rd (CRC_rd ),
.CRC_out (CRC_out ),
.CRC_end (CRC_end )
);
 
flow_ctrl U_flow_ctrl(
.Reset (Reset ),
.Clk (Clk ),
//host processor (//host processor ),
.tx_pause_en (tx_pause_en ),
.xoff_cpu (xoff_cpu ),
.xon_cpu (xon_cpu ),
//MAC_rx_flow (//MAC_rx_flow ),
.pause_quanta (pause_quanta ),
.pause_quanta_val (pause_quanta_val ),
//MAC_tx_ctrl (//MAC_tx_ctrl ),
.pause_apply (pause_apply ),
.pause_quanta_sub (pause_quanta_sub ),
.xoff_gen (xoff_gen ),
.xoff_gen_complete (xoff_gen_complete ),
.xon_gen (xon_gen ),
.xon_gen_complete (xon_gen_complete )
);
 
MAC_tx_addr_add U_MAC_tx_addr_add(
.Reset (Reset ),
.Clk (Clk ),
.MAC_tx_addr_rd (MAC_tx_addr_rd ),
.MAC_tx_addr_init (MAC_tx_addr_init ),
.MAC_tx_addr_data (MAC_tx_addr_data ),
//CPU (//CPU ),
.MAC_add_prom_data (MAC_add_prom_data ),
.MAC_add_prom_add (MAC_add_prom_add ),
.MAC_add_prom_wr (MAC_add_prom_wr )
);
 
MAC_tx_FF U_MAC_tx_FF(
.Reset (Reset ),
.Clk_MAC (Clk ),
.Clk_SYS (Clk_user ),
//MAC_rx_ctrl interf (//MAC_rx_ctrl interf ),
.Fifo_data (Fifo_data ),
.Fifo_rd (Fifo_rd ),
.Fifo_rd_finish (Fifo_rd_finish ),
.Fifo_rd_retry (Fifo_rd_retry ),
.Fifo_eop (Fifo_eop ),
.Fifo_da (Fifo_da ),
.Fifo_ra (Fifo_ra ),
.Fifo_data_err_empty (Fifo_data_err_empty ),
.Fifo_data_err_full (Fifo_data_err_full ),
//user interface (//user interface ),
.Tx_mac_wa (Tx_mac_wa ),
.Tx_mac_wr (Tx_mac_wr ),
.Tx_mac_data (Tx_mac_data ),
.Tx_mac_BE (Tx_mac_BE ),
.Tx_mac_sop (Tx_mac_sop ),
.Tx_mac_eop (Tx_mac_eop ),
//host interface (//host interface ),
.FullDuplex (FullDuplex ),
.Tx_Hwmark (Tx_Hwmark ),
.Tx_Lwmark (Tx_Lwmark )
);
 
Ramdon_gen U_Ramdon_gen(
.Reset (Reset ),
.Clk (Clk ),
.Init (Random_init ),
.RetryCnt (RetryCnt ),
.Random_time_meet (Random_time_meet )
);
 
endmodule
/trunk/rtl/verilog/RMON.v
0,0 → 1,170
//////////////////////////////////////////////////////////////////////
//// ////
//// RMON.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module RMON (
Clk ,
Reset ,
//Tx_RMON
Tx_pkt_type_rmon ,
Tx_pkt_length_rmon ,
Tx_apply_rmon ,
Tx_pkt_err_type_rmon,
//Tx_RMON
Rx_pkt_type_rmon ,
Rx_pkt_length_rmon ,
Rx_apply_rmon ,
Rx_pkt_err_type_rmon,
//CPU
CPU_rd_addr ,
CPU_rd_apply ,
CPU_rd_grant ,
CPU_rd_dout
 
);
input Clk ;
input Reset ;
//Tx_RMON
input [2:0] Tx_pkt_type_rmon ;
input [15:0] Tx_pkt_length_rmon ;
input Tx_apply_rmon ;
input [2:0] Tx_pkt_err_type_rmon;
//Tx_RMON
input [2:0] Rx_pkt_type_rmon ;
input [15:0] Rx_pkt_length_rmon ;
input Rx_apply_rmon ;
input [2:0] Rx_pkt_err_type_rmon;
//CPU
input [5:0] CPU_rd_addr ;
input CPU_rd_apply ;
output CPU_rd_grant ;
output [31:0] CPU_rd_dout ;
 
//******************************************************************************
//interface signals
//******************************************************************************
wire Reg_apply_0 ;
wire [4:0] Reg_addr_0 ;
wire [15:0] Reg_data_0 ;
wire Reg_next_0 ;
wire Reg_apply_1 ;
wire [4:0] Reg_addr_1 ;
wire [15:0] Reg_data_1 ;
wire Reg_next_1 ;
wire [5:0] Addra ;
wire [31:0] Dina ;
wire [31:0] Douta ;
wire Wea ;
 
//******************************************************************************
 
assign RxAddrb=0;
assign TxAddrb=0;
 
RMON_addr_gen U_0_Rx_RMON_addr_gen(
.Clk (Clk ),
.Reset (Reset ),
//RMON (//RMON ),
.Pkt_type_rmon (Rx_pkt_type_rmon ),
.Pkt_length_rmon (Rx_pkt_length_rmon ),
.Apply_rmon (Rx_apply_rmon ),
.Pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
//Rmon_ctrl (//Rron_ctrl ),
.Reg_apply (Reg_apply_0 ),
.Reg_addr (Reg_addr_0 ),
.Reg_data (Reg_data_0 ),
.Reg_next (Reg_next_0 ),
//CPU (//CPU ),
.Reg_drop_apply ( ));
 
RMON_addr_gen U_0_Tx_RMON_addr_gen(
.Clk (Clk ),
.Reset (Reset ),
//RMON (//RMON ),
.Pkt_type_rmon (Tx_pkt_type_rmon ),
.Pkt_length_rmon (Tx_pkt_length_rmon ),
.Apply_rmon (Tx_apply_rmon ),
.Pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
//Rmon_ctrl (//Rron_ctrl ),
.Reg_apply (Reg_apply_1 ),
.Reg_addr (Reg_addr_1 ),
.Reg_data (Reg_data_1 ),
.Reg_next (Reg_next_1 ),
//CPU (//CPU ),
.Reg_drop_apply ( ));
 
RMON_CTRL U_RMON_CTRL(
.Clk (Clk ),
.Reset (Reset ),
//RMON_CTRL (//RMON_CTRL ),
.Reg_apply_0 (Reg_apply_0 ),
.Reg_addr_0 (Reg_addr_0 ),
.Reg_data_0 (Reg_data_0 ),
.Reg_next_0 (Reg_next_0 ),
.Reg_apply_1 (Reg_apply_1 ),
.Reg_addr_1 (Reg_addr_1 ),
.Reg_data_1 (Reg_data_1 ),
.Reg_next_1 (Reg_next_1 ),
//dual-port ram (//dual-port ram ),
.Addra (Addra ),
.Dina (Dina ),
.Douta (Douta ),
.Wea (Wea ),
//CPU (//CPU ),
.CPU_rd_addr (CPU_rd_addr ),
.CPU_rd_apply (CPU_rd_apply ),
.CPU_rd_grant (CPU_rd_grant ),
.CPU_rd_dout (CPU_rd_dout )
);
 
RMON_dpram U_Rx_RMON_dpram(
.Reset (Reset ),
.Clk (Clk ),
//port-a for Rmon (//port-a for Rmon ),
.Addra (Addra ),
.Dina (Dina ),
.Douta (Douta ),
.Wea (Wea ),
//port-b for CPU (//port-b for CPU ),
.Addrb (RxAddrb ),
.Doutb (RxDoutb ));
 
endmodule
/trunk/rtl/verilog/eth_miim.v
0,0 → 1,469
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_miim.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2005/08/16 12:07:57 Administrator
// no message
//
// Revision 1.3 2005/05/19 07:04:29 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:46 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.5 2003/05/16 10:08:27 mohor
// Busy was set 2 cycles too late. Reported by Dennis Scott.
//
// Revision 1.4 2002/08/14 18:32:10 mohor
// - Busy signal was not set on time when scan status operation was performed
// and clock was divided with more than 2.
// - Nvalid remains valid two more clocks (was previously cleared too soon).
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
 
`timescale 1ns/10ps
 
 
module eth_miim
(
Clk,
Reset,
Divider,
NoPre,
CtrlData,
Rgad,
Fiad,
WCtrlData,
RStat,
ScanStat,
Mdio,
Mdc,
Busy,
Prsd,
LinkFail,
Nvalid,
WCtrlDataStart,
RStatStart,
UpdateMIIRX_DATAReg
);
 
 
 
input Clk; // Host Clock
input Reset; // General Reset
input [7:0] Divider; // Divider for the host clock
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
inout Mdio; // MII Management Data In
 
output Mdc; // MII Management Data Clock
 
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
 
output [15:0] Prsd; // Read Status Data (data read from the PHY)
 
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
 
parameter Tp = 1;
 
 
reg Nvalid;
reg EndBusy_d; // Pre-end Busy signal
reg EndBusy; // End Busy signal (stops the operation in progress)
 
reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle
reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles
reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles
reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)
reg WCtrlDataStart_q;
reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle
reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles
 
reg RStat_q1; // Read Status operation delayed 1 Clk cycle
reg RStat_q2; // Read Status operation delayed 2 Clk cycles
reg RStat_q3; // Read Status operation delayed 3 Clk cycles
reg RStatStart; // Start Read Status Command (positive edge detected)
reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle
reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles
 
reg ScanStat_q1; // Scan Status operation delayed 1 cycle
reg ScanStat_q2; // Scan Status operation delayed 2 cycles
reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn
 
wire WriteDataOp; // Write Data Operation (positive edge detected)
wire ReadStatusOp; // Read Status Operation (positive edge detected)
wire ScanStatusOp; // Scan Status Operation (positive edge detected)
wire StartOp; // Start Operation (start of any of the preceding operations)
wire EndOp; // End of Operation
 
reg InProgress; // Operation in progress
reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle
reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles
reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles
 
reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
reg [6:0] BitCounter; // Bit Counter
 
 
wire MdcFrame; // Frame window for limiting the Mdc
wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
 
 
wire LatchByte1_d2;
wire LatchByte0_d2;
reg LatchByte1_d;
reg LatchByte0_d;
reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
 
reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
 
wire Mdo; // MII Management Data Output
wire MdoEn; // MII Management Data Output Enable
wire Mdi;
 
assign Mdi=Mdio;
assign Mdio=MdoEn?Mdo:1'bz;
 
 
 
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
EndBusy_d <= #Tp 1'b0;
EndBusy <= #Tp 1'b0;
end
else
begin
EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
EndBusy <= #Tp EndBusy_d;
end
end
 
 
// Update MII RX_DATA register
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
UpdateMIIRX_DATAReg <= #Tp 0;
else
if(EndBusy & ~WCtrlDataStart_q)
UpdateMIIRX_DATAReg <= #Tp 1;
else
UpdateMIIRX_DATAReg <= #Tp 0;
end
 
 
 
// Generation of the delayed signals used for positive edge triggering.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlData_q1 <= #Tp 1'b0;
WCtrlData_q2 <= #Tp 1'b0;
WCtrlData_q3 <= #Tp 1'b0;
RStat_q1 <= #Tp 1'b0;
RStat_q2 <= #Tp 1'b0;
RStat_q3 <= #Tp 1'b0;
 
ScanStat_q1 <= #Tp 1'b0;
ScanStat_q2 <= #Tp 1'b0;
SyncStatMdcEn <= #Tp 1'b0;
end
else
begin
WCtrlData_q1 <= #Tp WCtrlData;
WCtrlData_q2 <= #Tp WCtrlData_q1;
WCtrlData_q3 <= #Tp WCtrlData_q2;
 
RStat_q1 <= #Tp RStat;
RStat_q2 <= #Tp RStat_q1;
RStat_q3 <= #Tp RStat_q2;
 
ScanStat_q1 <= #Tp ScanStat;
ScanStat_q2 <= #Tp ScanStat_q1;
if(MdcEn)
SyncStatMdcEn <= #Tp ScanStat_q2;
end
end
 
 
// Generation of the Start Commands (Write Control Data or Read Status)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart <= #Tp 1'b0;
WCtrlDataStart_q <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(EndBusy)
begin
WCtrlDataStart <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(WCtrlData_q2 & ~WCtrlData_q3)
WCtrlDataStart <= #Tp 1'b1;
if(RStat_q2 & ~RStat_q3)
RStatStart <= #Tp 1'b1;
WCtrlDataStart_q <= #Tp WCtrlDataStart;
end
end
end
 
 
// Generation of the Nvalid signal (indicates when the status is invalid)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Nvalid <= #Tp 1'b0;
else
begin
if(~InProgress_q2 & InProgress_q3)
begin
Nvalid <= #Tp 1'b0;
end
else
begin
if(ScanStat_q2 & ~SyncStatMdcEn)
Nvalid <= #Tp 1'b1;
end
end
end
 
// Signals used for the generation of the Operation signals (positive edge)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart_q1 <= #Tp 1'b0;
WCtrlDataStart_q2 <= #Tp 1'b0;
 
RStatStart_q1 <= #Tp 1'b0;
RStatStart_q2 <= #Tp 1'b0;
 
InProgress_q1 <= #Tp 1'b0;
InProgress_q2 <= #Tp 1'b0;
InProgress_q3 <= #Tp 1'b0;
 
LatchByte0_d <= #Tp 1'b0;
LatchByte1_d <= #Tp 1'b0;
 
LatchByte <= #Tp 2'b00;
end
else
begin
if(MdcEn)
begin
WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
 
RStatStart_q1 <= #Tp RStatStart;
RStatStart_q2 <= #Tp RStatStart_q1;
 
LatchByte[0] <= #Tp LatchByte0_d;
LatchByte[1] <= #Tp LatchByte1_d;
 
LatchByte0_d <= #Tp LatchByte0_d2;
LatchByte1_d <= #Tp LatchByte1_d2;
 
InProgress_q1 <= #Tp InProgress;
InProgress_q2 <= #Tp InProgress_q1;
InProgress_q3 <= #Tp InProgress_q2;
end
end
end
 
 
// Generation of the Operation signals
assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
 
// Busy
reg Busy;
always @ (posedge Clk or posedge Reset)
if (Reset)
Busy <=0;
else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid)
Busy <=1;
else
Busy <=0;
//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
 
 
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
else
begin
if(MdcEn)
begin
if(StartOp)
begin
if(~InProgress)
WriteOp <= #Tp WriteDataOp;
InProgress <= #Tp 1'b1;
end
else
begin
if(EndOp)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
end
end
end
end
 
 
 
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
BitCounter[6:0] <= #Tp 7'h0;
else
begin
if(MdcEn)
begin
if(InProgress)
begin
if(NoPre & ( BitCounter == 7'h0 ))
BitCounter[6:0] <= #Tp 7'h21;
else
BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
end
else
BitCounter[6:0] <= #Tp 7'h0;
end
end
end
 
 
// Operation ends when the Bit Counter reaches 63
assign EndOp = BitCounter==63;
 
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
 
 
// Latch Byte selects which part of Read Status Data is updated from the shift register
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
 
 
// Connecting the Clock Generator Module
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
);
 
// Connecting the Shift Register Module
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
);
 
// Connecting the Output Control Module
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
.Mdo(Mdo), .MdoEn(MdoEn)
);
 
endmodule
/trunk/rtl/verilog/Clk_ctrl.v
0,0 → 1,115
//////////////////////////////////////////////////////////////////////
//// ////
//// Clk_ctrl.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module Clk_ctrl(
Reset ,
Clk_125M ,
//host interface,
Speed ,
//Phy interface ,
Gtx_clk ,
Rx_clk ,
Tx_clk ,
//interface clk ,
MAC_tx_clk ,
MAC_rx_clk ,
MAC_tx_clk_div ,
MAC_rx_clk_div
);
input Reset ;
input Clk_125M ;
//host interface
input [2:0] Speed ;
//Phy interface
output Gtx_clk ;//used only in GMII mode
input Rx_clk ;
input Tx_clk ;//used only in MII mode
//interface clk signals
output MAC_tx_clk ;
output MAC_rx_clk ;
output MAC_tx_clk_div ;
output MAC_rx_clk_div ;
 
 
//******************************************************************************
//internal signals
//******************************************************************************
wire Rx_clk_div2 ;
wire Tx_clk_div2 ;
//******************************************************************************
//
//******************************************************************************
assign Gtx_clk =Clk_125M ;
assign MAC_rx_clk =Rx_clk ;
 
CLK_DIV2 U_0_CLK_DIV2(
.IN (Rx_clk ),
.OUT (Rx_clk_div2 )
);
 
CLK_DIV2 U_1_CLK_DIV2(
.IN (Tx_clk ),
.OUT (Tx_clk_div2 )
);
 
CLK_SWITCH U_0_CLK_SWITCH(
.IN_0 (Rx_clk_div2 ),
.IN_1 (Rx_clk ),
.SW (Speed[2] ),
.OUT (MAC_rx_clk_div )
);
 
CLK_SWITCH U_1_CLK_SWITCH(
.IN_0 (Tx_clk ),
.IN_1 (Clk_125M ),
.SW (Speed[2] ),
.OUT (MAC_tx_clk )
);
 
 
CLK_SWITCH U_2_CLK_SWITCH(
.IN_0 (Tx_clk_div2 ),
.IN_1 (Clk_125M ),
.SW (Speed[2] ),
.OUT (MAC_tx_clk_div )
);
endmodule
/trunk/rtl/verilog/TECH/CLK_DIV2.v
0,0 → 1,57
//////////////////////////////////////////////////////////////////////
//// ////
//// CLK_DIV2.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
 
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
 
module CLK_DIV2 (
input IN,
output reg OUT
);
 
always @ (posedge IN)
OUT <=!OUT;
endmodule
/trunk/rtl/verilog/TECH/CLK_SWITCH.v
0,0 → 1,58
//////////////////////////////////////////////////////////////////////
//// ////
//// CLK_SWITCH.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
 
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
module CLK_SWITCH (
input IN_0,
input IN_1,
input SW ,
output OUT
 
);
 
assign OUT=SW?IN_1:IN_0;
 
endmodule
/trunk/rtl/verilog/MAC_top.v
0,0 → 1,342
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_top.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module MAC_top(
//system signals
input Reset ,
input Clk_125M ,
input Clk_user ,
input Clk_reg ,
//user interface
output Rx_mac_ra ,
input Rx_mac_rd ,
output [31:0] Rx_mac_data ,
output [1:0] Rx_mac_BE ,
output Rx_mac_pa ,
output Rx_mac_sop ,
output Rx_mac_eop ,
//user interface
output Tx_mac_wa ,
input Tx_mac_wr ,
input [31:0] Tx_mac_data ,
input [1:0] Tx_mac_BE ,//big endian
input Tx_mac_sop ,
input Tx_mac_eop ,
//Phy interface
//Phy interface
output Gtx_clk ,//used only in GMII mode
input Rx_clk ,
input Tx_clk ,//used only in MII mode
output Tx_er ,
output Tx_en ,
output [7:0] Txd ,
input Rx_er ,
input Rx_dv ,
input [7:0] Rxd ,
input Crs ,
input Col ,
//Tx host interface
input [4:0] Tx_Hwmark ,
input [4:0] Tx_Lwmark ,
input pause_frame_send_en ,
input [15:0] pause_quanta_set ,
input MAC_tx_add_en ,
input FullDuplex ,
input [3:0] MaxRetry ,
input [5:0] IFGset ,
input [7:0] MAC_tx_add_prom_data ,
input [2:0] MAC_tx_add_prom_add ,
input MAC_tx_add_prom_wr ,
input tx_pause_en ,
input xoff_cpu ,
input xon_cpu ,
//Rx host interface
input MAC_rx_add_chk_en ,
input [7:0] MAC_rx_add_prom_data ,
input [2:0] MAC_rx_add_prom_add ,
input MAC_rx_add_prom_wr ,
input broadcast_filter_en ,
input [15:0] broadcast_MAX ,
input RX_APPEND_CRC ,
input CRC_chk_en ,
input [5:0] RX_IFG_SET ,
input [15:0] RX_MAX_LENGTH ,// 1518
input [6:0] RX_MIN_LENGTH ,// 64
//RMON host interface
input [5:0] CPU_rd_addr ,
input CPU_rd_apply ,
output CPU_rd_grant ,
output [31:0] CPU_rd_dout ,
//Phy int host interface
input Line_loop_en ,
input [2:0] Speed ,
//MII to CPU
input [7:0] Divider ,// Divider for the host clock
input [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
input [4:0] Rgad ,// Register Address (within the PHY)
input [4:0] Fiad ,// PHY Address
input NoPre ,// No Preamble (no 32-bit preamble)
input WCtrlData ,// Write Control Data operation
input RStat ,// Read Status operation
input ScanStat ,// Scan Status operation
output Busy ,// Busy Signal
output LinkFail ,// Link Integrity Signal
output Nvalid ,// Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd ,// Read Status Data (data read from the PHY)
output WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
//MII interface signals
inout Mdio ,// MII Management Data In
output Mdc ,// MII Management Data Clock
 
);
//******************************************************************************
//internal signals
//******************************************************************************
//RMON interface
wire [15:0] Rx_pkt_length_rmon ;
wire Rx_apply_rmon ;
wire [2:0] Rx_pkt_err_type_rmon ;
wire [2:0] Rx_pkt_type_rmon ;
wire [2:0] Tx_pkt_type_rmon ;
wire [15:0] Tx_pkt_length_rmon ;
wire Tx_apply_rmon ;
wire [2:0] Tx_pkt_err_type_rmon ;
//PHY interface
wire MCrs_dv ;
wire [7:0] MRxD ;
wire MRxErr ;
//flow_control signals
wire [15:0] pause_quanta ;
wire pause_quanta_val ;
//PHY interface
wire [7:0] MTxD ;
wire MTxEn ;
wire MCRS ;
//interface clk signals
wire MAC_tx_clk ;
wire MAC_rx_clk ;
wire MAC_tx_clk_div ;
wire MAC_rx_clk_div ;
//******************************************************************************
//internal signals
//******************************************************************************
MAC_rx U_MAC_rx(
.Reset (Reset ),
.Clk_user (Clk_user ),
.Clk (MAC_rx_clk_div ),
//RMII interface (//PHY interface ),
.MCrs_dv (MCrs_dv ),
.MRxD (MRxD ),
.MRxErr (MRxErr ),
//flow_control signals (//flow_control signals ),
.pause_quanta (pause_quanta ),
.pause_quanta_val (pause_quanta_val ),
//user interface (//user interface ),
.Rx_mac_ra (Rx_mac_ra ),
.Rx_mac_rd (Rx_mac_rd ),
.Rx_mac_data (Rx_mac_data ),
.Rx_mac_BE (Rx_mac_BE ),
.Rx_mac_pa (Rx_mac_pa ),
.Rx_mac_sop (Rx_mac_sop ),
.Rx_mac_eop (Rx_mac_eop ),
//CPU (//CPU ),
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
.MAC_add_prom_data (MAC_rx_add_prom_data ),
.MAC_add_prom_add (MAC_rx_add_prom_add ),
.MAC_add_prom_wr (MAC_rx_add_prom_wr ),
.broadcast_filter_en (broadcast_filter_en ),
.broadcast_MAX (broadcast_MAX ),
.RX_APPEND_CRC (RX_APPEND_CRC ),
.CRC_chk_en (CRC_chk_en ),
.RX_IFG_SET (RX_IFG_SET ),
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
//RMON interface (//RMON interface ),
.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),
.Rx_apply_rmon (Rx_apply_rmon ),
.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
.Rx_pkt_type_rmon (Rx_pkt_type_rmon )
);
 
MAC_tx U_MAC_tx(
.Reset (Reset ),
.Clk (MAC_tx_clk_div ),
.Clk_user (Clk_user ),
//PHY interface (//PHY interface ),
.TxD (MTxD ),
.TxEn (MTxEn ),
.CRS (MCRS ),
//RMON (//RMON ),
.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),
.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),
.Tx_apply_rmon (Tx_apply_rmon ),
.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
//user interface (//user interface ),
.Tx_mac_wa (Tx_mac_wa ),
.Tx_mac_wr (Tx_mac_wr ),
.Tx_mac_data (Tx_mac_data ),
.Tx_mac_BE (Tx_mac_BE ),
.Tx_mac_sop (Tx_mac_sop ),
.Tx_mac_eop (Tx_mac_eop ),
//host interface (//host interface ),
.Tx_Hwmark (Tx_Hwmark ),
.Tx_Lwmark (Tx_Lwmark ),
.pause_frame_send_en (pause_frame_send_en ),
.pause_quanta_set (pause_quanta_set ),
.MAC_tx_add_en (MAC_tx_add_en ),
.FullDuplex (FullDuplex ),
.MaxRetry (MaxRetry ),
.IFGset (IFGset ),
.MAC_add_prom_data (MAC_tx_add_prom_data ),
.MAC_add_prom_add (MAC_tx_add_prom_add ),
.MAC_add_prom_wr (MAC_tx_add_prom_wr ),
.tx_pause_en (tx_pause_en ),
.xoff_cpu (xoff_cpu ),
.xon_cpu (xon_cpu ),
//MAC_rx_flow (//MAC_rx_flow ),
.pause_quanta (pause_quanta ),
.pause_quanta_val (pause_quanta_val )
);
 
RMON U_RMON(
.Clk (Clk_reg ),
.Reset (Reset ),
//Tx_RMON (//Tx_RMON ),
.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),
.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),
.Tx_apply_rmon (Tx_apply_rmon ),
.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
//Tx_RMON (//Tx_RMON ),
.Rx_pkt_type_rmon (Rx_pkt_type_rmon ),
.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),
.Rx_apply_rmon (Rx_apply_rmon ),
.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
//CPU (//CPU ),
.CPU_rd_addr (CPU_rd_addr ),
.CPU_rd_apply (CPU_rd_apply ),
.CPU_rd_grant (CPU_rd_grant ),
.CPU_rd_dout (CPU_rd_dout )
);
 
Phy_int U_Phy_int(
.Reset (Reset ),
.MAC_rx_clk (MAC_rx_clk ),
.MAC_tx_clk (MAC_tx_clk ),
//Rx interface (//Rx interface ),
.MCrs_dv (MCrs_dv ),
.MRxD (MRxD ),
.MRxErr (MRxErr ),
//Tx interface (//Tx interface ),
.MTxD (MTxD ),
.MTxEn (MTxEn ),
.MCRS (MCRS ),
//Phy interface (//Phy interface ),
.Tx_er (Tx_er ),
.Tx_en (Tx_en ),
.Txd (Txd ),
.Rx_er (Rx_er ),
.Rx_dv (Rx_dv ),
.Rxd (Rxd ),
.Crs (Crs ),
.Col (Col ),
//host interface (//host interface ),
.Line_loop_en (Line_loop_en ),
.Speed (Speed )
);
 
Clk_ctrl U_Clk_ctrl(
.Reset (Reset ),
.Clk_125M (Clk_125M ),
//host interface (//host interface ),
.Speed (Speed ),
//Phy interface (//Phy interface ),
.Gtx_clk (Gtx_clk ),
.Rx_clk (Rx_clk ),
.Tx_clk (Tx_clk ),
//interface clk (//interface clk ),
.MAC_tx_clk (MAC_tx_clk ),
.MAC_rx_clk (MAC_rx_clk ),
.MAC_tx_clk_div (MAC_tx_clk_div ),
.MAC_rx_clk_div (MAC_rx_clk_div )
);
 
eth_miim U_eth_miim(
.Clk (Clk_reg ),
.Reset (Reset ),
.Divider (Divider ),
.NoPre (NoPre ),
.CtrlData (CtrlData ),
.Rgad (Rgad ),
.Fiad (Fiad ),
.WCtrlData (WCtrlData ),
.RStat (RStat ),
.ScanStat (ScanStat ),
.Mdio (Mdio ),
.Mdc (Mdc ),
.Busy (Busy ),
.Prsd (Prsd ),
.LinkFail (LinkFail ),
.Nvalid (Nvalid ),
.WCtrlDataStart (WCtrlDataStart ),
.RStatStart (RStatStart ),
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ));
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/trunk/rtl/verilog/MAC_rx/CRC_chk.v
0,0 → 1,119
//////////////////////////////////////////////////////////////////////
//// ////
//// CRC_chk.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module CRC_chk(
Reset ,
Clk ,
CRC_data ,
CRC_init ,
CRC_en ,
//From CPU
CRC_chk_en ,
CRC_err
);
input Reset ;
input Clk ;
input[7:0] CRC_data ;
input CRC_init ;
input CRC_en ;
//From CPU
input CRC_chk_en ;
output CRC_err ;
//******************************************************************************
//internal signals
//******************************************************************************
reg[31:0] CRC_reg;
wire[31:0] Next_CRC;
//******************************************************************************
//input data width is 8bit, and the first bit is bit[0]
function[31:0] NextCRC;
input[7:0] D;
input[31:0] C;
reg[31:0] NewCRC;
begin
NewCRC[0]=C[24]^C[30]^D[1]^D[7];
NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
NewCRC[20]=C[12]^C[28]^D[3];
NewCRC[21]=C[13]^C[29]^D[2];
NewCRC[22]=C[14]^C[24]^D[7];
NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
NewCRC[31]=C[23]^C[29]^D[2];
NextCRC=NewCRC;
end
endfunction
 
always @ (posedge Clk or posedge Reset)
if (Reset)
CRC_reg <=32'hffffffff;
else if (CRC_init)
CRC_reg <=32'hffffffff;
else if (CRC_en)
CRC_reg <=NextCRC(CRC_data,CRC_reg);
 
assign CRC_err = CRC_chk_en&(Next_CRC[31:0] != 32'hc704dd7b);
 
endmodule
/trunk/rtl/verilog/MAC_rx/MAC_rx_ctrl.v
0,0 → 1,501
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_rx_ctrl.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module MAC_rx_ctrl (
Reset ,
Clk ,
//RMII interface
MCrs_dv , //
MRxD , //
MRxErr , //
//CRC_chk interface
CRC_en ,
CRC_init ,
CRC_err ,
//MAC_rx_add_chk interface
MAC_add_en ,
MAC_rx_add_chk_err ,
//broadcast_filter
broadcast_ptr ,
broadcast_drop ,
//flow_control signals
pause_quanta ,
pause_quanta_val ,
//MAC_rx_FF interface
Fifo_data ,
Fifo_data_en ,
Fifo_data_err ,
Fifo_data_end ,
Fifo_full ,
//RMON interface
Rx_pkt_type_rmon ,
Rx_pkt_length_rmon ,
Rx_apply_rmon ,
Rx_pkt_err_type_rmon ,
//CPU
RX_IFG_SET ,
RX_MAX_LENGTH,
RX_MIN_LENGTH
);
 
input Reset ;
input Clk ;
//RMII interface
input MCrs_dv ;
input [7:0] MRxD ;
input MRxErr ;
//CRC_chk interface
output CRC_en ;
output CRC_init;
input CRC_err ;
//MAC_rx_add_chk interface
output MAC_add_en ;
input MAC_rx_add_chk_err ;
//broadcast_filter
output broadcast_ptr ;
input broadcast_drop ;
//flow_control signals
output [15:0] pause_quanta ;
output pause_quanta_val ;
//MAC_rx_FF interface
output [7:0] Fifo_data ;
output Fifo_data_en ;
output Fifo_data_err ;
output Fifo_data_end ;
input Fifo_full;
//RMON interface
output [15:0] Rx_pkt_length_rmon ;
output Rx_apply_rmon ;
output [2:0] Rx_pkt_err_type_rmon ;
output [2:0] Rx_pkt_type_rmon ;
//CPU
input [5:0] RX_IFG_SET ;
input [15:0] RX_MAX_LENGTH ;// 1518
input [6:0] RX_MIN_LENGTH ;// 64
 
//******************************************************************************
//internal signals
//******************************************************************************
parameter State_idle =4'd00;
parameter State_preamble =4'd01;
parameter State_SFD =4'd02;
parameter State_data =4'd03;
parameter State_OkEnd =4'd07;
parameter State_drop =4'd08;
parameter State_ErrEnd =4'd09;
parameter State_CRCErrEnd =4'd10;
parameter State_FFFullDrop =4'd11;
parameter State_FFFullErrEnd =4'd12;
parameter State_IFG =4'd13;
 
parameter Pause_idle =4'd0;
parameter Pause_pre_syn =4'd1;
parameter Pause_quanta_hi =4'd2;
parameter Pause_quanta_lo =4'd3;
parameter Pause_syn =4'd4;
reg [3:0] Current_state /* synthesis syn_keep=1 */;
reg [3:0] Next_state;
reg [3:0] Pause_current /* synthesis syn_keep=1 */;
reg [3:0] Pause_next;
reg [5:0] IFG_counter;
reg Crs_dv ;
reg [7:0] RxD ;
reg [7:0] RxD_dl1 ;
reg RxErr ;
reg [15:0] Frame_length_counter;
reg Too_long;
reg Too_short;
reg Fifo_data_en;
reg Fifo_data_end;
reg Fifo_data_err;
reg CRC_en;
reg CRC_init;
reg Rx_apply_rmon;
reg [2:0] Rx_pkt_err_type_rmon;
reg MAC_add_en;
reg [2:0] Rx_pkt_type_rmon;
reg [7:0] pause_quanta_h ;
reg [15:0] pause_quanta ;
reg pause_quanta_val ;
reg pause_quanta_val_tmp;
reg pause_frame_ptr ;
reg broadcast_ptr ;
//******************************************************************************
//delay signals
//******************************************************************************
always @ (posedge Reset or posedge Clk)
if (Reset)
begin
Crs_dv <=0;
RxD <=0;
RxErr <=0;
end
else
begin
Crs_dv <=MCrs_dv ;
RxD <=MRxD ;
RxErr <=MRxErr ;
end
 
always @ (posedge Reset or posedge Clk)
if (Reset)
RxD_dl1 <=0;
else
RxD_dl1 <=RxD;
//******************************************************************************
//State_machine
//******************************************************************************
always @ (posedge Reset or posedge Clk)
if (Reset)
Current_state <=State_idle;
else
Current_state <=Next_state;
always @ (*)
case (Current_state)
State_idle:
if (Crs_dv&&RxD==8'h55)
Next_state =State_preamble;
else
Next_state =Current_state;
State_preamble:
if (!Crs_dv)
Next_state =State_ErrEnd;
else if (RxErr)
Next_state =State_drop;
else if (RxD==8'hd5)
Next_state =State_SFD;
else if (RxD==8'h55)
Next_state =Current_state;
else
Next_state =State_drop;
State_SFD:
if (!Crs_dv)
Next_state =State_ErrEnd;
else if (RxErr)
Next_state =State_drop;
else
Next_state =State_data;
State_data:
if (!Crs_dv&&!CRC_err&&!Too_short&&!Too_long)
Next_state =State_OkEnd;
else if (!Crs_dv&&(Too_short||Too_long))
Next_state =State_ErrEnd;
else if (!Crs_dv&&CRC_err)
Next_state =State_CRCErrEnd;
else if (Fifo_full)
Next_state =State_FFFullErrEnd;
else if (RxErr||MAC_rx_add_chk_err||Too_long||broadcast_drop)
Next_state =State_drop;
else
Next_state =State_data;
State_drop:
if (!Crs_dv)
Next_state =State_ErrEnd;
else
Next_state =Current_state;
State_OkEnd:
Next_state =State_IFG;
State_ErrEnd:
Next_state =State_IFG;
State_CRCErrEnd:
Next_state =State_IFG;
State_FFFullDrop:
if (!Crs_dv)
Next_state =State_IFG;
else
Next_state =Current_state;
State_FFFullErrEnd:
Next_state =State_FFFullDrop;
State_IFG:
if (IFG_counter==RX_IFG_SET)
Next_state =State_idle;
else
Next_state =Current_state;
default:
Next_state =State_idle;
endcase
always @ (posedge Reset or posedge Clk)
if (Reset)
IFG_counter <=0;
else if (Current_state!=State_IFG)
IFG_counter <=0;
else
IFG_counter <=IFG_counter + 1;
//******************************************************************************
//gen fifo interface signals
//******************************************************************************
 
assign Fifo_data =RxD_dl1;
 
always @(Current_state)
if (Current_state==State_data)
Fifo_data_en =1;
else
Fifo_data_en =0;
always @(Current_state)
if (Current_state==State_ErrEnd||Current_state==State_OkEnd
||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
Fifo_data_end =1;
else
Fifo_data_end =0;
 
always @(Current_state)
if (Current_state==State_ErrEnd||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
Fifo_data_err =1;
else
Fifo_data_err =0;
 
//******************************************************************************
//CRC_chk interface
//******************************************************************************
 
always @(Current_state)
if (Current_state==State_data)
CRC_en =1;
else
CRC_en =0;
always @(Current_state)
if (Current_state==State_SFD)
CRC_init =1;
else
CRC_init =0;
//******************************************************************************
//gen rmon signals
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
Frame_length_counter <=0;
else if (Current_state==State_SFD)
Frame_length_counter <=0;
else if (Current_state==State_data)
Frame_length_counter <=Frame_length_counter+ 1;
always @ (Frame_length_counter or RX_MIN_LENGTH)
if (Frame_length_counter<RX_MIN_LENGTH)
Too_short =1;
else
Too_short =0;
always @ (*)
if (Frame_length_counter>RX_MAX_LENGTH)
Too_long =1;
else
Too_long =0;
assign Rx_pkt_length_rmon=Frame_length_counter;
 
always @ (posedge Clk or posedge Reset)
if (Reset)
Rx_apply_rmon <=0;
else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
Rx_apply_rmon <=1;
else
Rx_apply_rmon <=0;
always @ (posedge Clk or posedge Reset)
if (Reset)
Rx_pkt_err_type_rmon <=0;
else if (Current_state==State_CRCErrEnd)
Rx_pkt_err_type_rmon <=3'b001 ;//
else if (Current_state==State_FFFullErrEnd)
Rx_pkt_err_type_rmon <=3'b010 ;//
else if (Current_state==State_ErrEnd)
Rx_pkt_err_type_rmon <=3'b011 ;//
else if(Current_state==State_OkEnd)
Rx_pkt_err_type_rmon <=3'b100 ;
 
 
always @ (posedge Clk or posedge Reset)
if (Reset)
Rx_pkt_type_rmon <=0;
else if (Current_state==State_OkEnd&&pause_frame_ptr)
Rx_pkt_type_rmon <=3'b100 ;//
else if(Current_state==State_SFD&&Next_state==State_data)
Rx_pkt_type_rmon <={1'b0,MRxD[7:6]};
 
always @ (posedge Clk or posedge Reset)
if (Reset)
broadcast_ptr <=0;
else if(Current_state==State_IFG)
broadcast_ptr <=0;
else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11)
broadcast_ptr <=1;
 
//******************************************************************************
//MAC add checker signals
//******************************************************************************
always @ (Frame_length_counter or Fifo_data_en)
if(Frame_length_counter>=0&&Frame_length_counter<=5)
MAC_add_en <=Fifo_data_en;
else
MAC_add_en <=0;
 
//******************************************************************************
//flow control signals
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
Pause_current <=Pause_idle;
else
Pause_current <=Pause_next;
always @ (*)
case (Pause_current)
Pause_idle :
if(Current_state==State_SFD)
Pause_next =Pause_pre_syn;
else
Pause_next =Pause_current;
Pause_pre_syn:
case (Frame_length_counter)
16'd0: if (RxD_dl1==8'h01)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd1: if (RxD_dl1==8'h80)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd2: if (RxD_dl1==8'hc2)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd3: if (RxD_dl1==8'h00)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd4: if (RxD_dl1==8'h00)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd5: if (RxD_dl1==8'h01)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd12: if (RxD_dl1==8'h88)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd13: if (RxD_dl1==8'h08)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd14: if (RxD_dl1==8'h00)
Pause_next =Pause_current;
else
Pause_next =Pause_idle;
16'd15: if (RxD_dl1==8'h01)
Pause_next =Pause_quanta_hi;
else
Pause_next =Pause_idle;
default: Pause_next =Pause_current;
endcase
Pause_quanta_hi :
Pause_next =Pause_quanta_lo;
Pause_quanta_lo :
Pause_next =Pause_syn;
Pause_syn :
if (Current_state==State_IFG)
Pause_next =Pause_idle;
else
Pause_next =Pause_current;
default
Pause_next =Pause_idle;
endcase
 
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta_h <=0;
else if(Pause_current==Pause_quanta_hi)
pause_quanta_h <=RxD_dl1;
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta <=0;
else if(Pause_current==Pause_quanta_lo)
pause_quanta <={pause_quanta_h,RxD_dl1};
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta_val_tmp <=0;
else if(Current_state==State_OkEnd&&Pause_current==Pause_syn)
pause_quanta_val_tmp <=1;
else
pause_quanta_val_tmp <=0;
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta_val <=0;
else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp)
pause_quanta_val <=1;
else
pause_quanta_val <=0;
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_frame_ptr <=0;
else if(Pause_current==Pause_syn)
pause_frame_ptr <=1;
else
pause_frame_ptr <=0;
endmodule
/trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v
0,0 → 1,570
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_rx_FF.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module MAC_rx_FF (
Reset ,
Clk_MAC ,
Clk_SYS ,
//MAC_rx_ctrl interface
Fifo_data ,
Fifo_data_en ,
Fifo_full ,
Fifo_data_err ,
Fifo_data_end ,
//CPU
RX_APPEND_CRC,
//user interface
Rx_mac_ra ,
Rx_mac_rd ,
Rx_mac_data ,
Rx_mac_BE ,
Rx_mac_sop ,
Rx_mac_pa,
Rx_mac_eop
);
input Reset ;
input Clk_MAC ;
input Clk_SYS ;
//MAC_rx_ctrl interface
input[7:0] Fifo_data ;
input Fifo_data_en ;
output Fifo_full ;
input Fifo_data_err ;
input Fifo_data_end ;
//CPU
input RX_APPEND_CRC;
//user interface
output Rx_mac_ra ;//
input Rx_mac_rd ;
output[31:0] Rx_mac_data ;
output[1:0] Rx_mac_BE ;
output Rx_mac_pa ;
output Rx_mac_sop ;
output Rx_mac_eop ;
 
//******************************************************************************
//internal signals
//******************************************************************************
parameter State_byte3 =4'd0;
parameter State_byte2 =4'd1;
parameter State_byte1 =4'd2;
parameter State_byte0 =4'd3;
parameter State_be0 =4'd4;
parameter State_be3 =4'd5;
parameter State_be2 =4'd6;
parameter State_be1 =4'd7;
parameter State_err_end =4'd8;
parameter State_idle =4'd9;
 
parameter SYS_read =3'd0;
parameter SYS_wait_end =3'd1;
parameter SYS_idle =3'd2;
parameter FF_emtpy_err =3'd3;
 
reg [8:0] Add_wr;
reg [8:0] Add_wr_ungray;
reg [8:0] Add_wr_gray;
reg [8:0] Add_wr_gray_dl1;
reg [8:0] Add_wr_reg;
 
reg [8:0] Add_rd;
reg [8:0] Add_rd_gray;
reg [8:0] Add_rd_gray_dl1;
reg [8:0] Add_rd_ungray;
reg [35:0] Din;
wire[35:0] Dout;
reg Wr_en;
wire[8:0] Add_wr_pluse;
reg Full;
reg Empty /* synthesis syn_keep=1 */;
reg [3:0] Current_state /* synthesis syn_keep=1 */;
reg [3:0] Next_state;
reg [7:0] Fifo_data_byte0;
reg [7:0] Fifo_data_byte1;
reg [7:0] Fifo_data_byte2;
reg [7:0] Fifo_data_byte3;
reg Fifo_data_en_dl1;
reg [7:0] Fifo_data_dl1;
reg Rx_mac_sop_tmp ;
reg Rx_mac_sop ;
reg Rx_mac_eop ;
reg Rx_mac_ra ;
reg Rx_mac_pa ;
 
 
 
reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;
reg [2:0] Next_state_SYS ;
reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;
reg Packet_number_sub ;
wire Packet_number_add_edge;
reg Packet_number_add_dl1;
reg Packet_number_add_dl2;
reg Packet_number_add ;
 
reg Rx_mac_sop_tmp_dl1;
reg[35:0] Dout_dl1;
reg[1:0] Rx_mac_BE ;
//******************************************************************************
//domain Clk_MAC,write data to dprom.a-port for write
//******************************************************************************
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Current_state <=State_idle;
else
Current_state <=Next_state;
always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
case (Current_state)
State_idle:
if (Fifo_data_en)
Next_state =State_byte3;
else
Next_state =Current_state;
State_byte3:
if (Fifo_data_en)
Next_state =State_byte2;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be1;
else
Next_state =Current_state;
State_byte2:
if (Fifo_data_en)
Next_state =State_byte1;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be2;
else
Next_state =Current_state;
State_byte1:
if (Fifo_data_en)
Next_state =State_byte0;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be3;
else
Next_state =Current_state;
State_byte0:
if (Fifo_data_en)
Next_state =State_byte3;
else if (Fifo_data_err)
Next_state =State_err_end;
else if (Fifo_data_end)
Next_state =State_be0;
else
Next_state =Current_state;
State_be1:
Next_state =State_idle;
State_be2:
Next_state =State_idle;
State_be3:
Next_state =State_idle;
State_be0:
Next_state =State_idle;
State_err_end:
Next_state =State_idle;
default:
Next_state =State_idle;
endcase
 
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_reg <=0;
else if (Current_state==State_idle)
Add_wr_reg <=Add_wr;
//
 
always @ (posedge Reset or posedge Clk_MAC)
if (Reset)
Add_wr_gray <=0;
else
Add_wr_gray <={ Add_wr[8],
Add_wr[8]^Add_wr[7],
Add_wr[7]^Add_wr[6],
Add_wr[6]^Add_wr[5],
Add_wr[5]^Add_wr[4],
Add_wr[4]^Add_wr[3],
Add_wr[3]^Add_wr[2],
Add_wr[2]^Add_wr[1],
Add_wr[1]^Add_wr[0]};
 
//
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd_gray_dl1 <=0;
else
Add_rd_gray_dl1 <=Add_rd_gray;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd_ungray <=0;
else
Add_rd_ungray <={
Add_rd_gray_dl1[8],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1]^Add_rd_gray_dl1[0] };
assign Add_wr_pluse=Add_wr+1;
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Full <=0;
else if (Add_wr_pluse==Add_rd_ungray)
Full <=1;
else
Full <=0;
 
assign Fifo_full =Full;
 
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr <=0;
else if (Current_state==State_err_end)
Add_wr <=Add_wr_reg;
else if (Wr_en&&!Full)
Add_wr <=Add_wr +1;
//
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_en_dl1 <=0;
else
Fifo_data_en_dl1 <=Fifo_data_en;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_dl1 <=0;
else
Fifo_data_dl1 <=Fifo_data;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte3 <=0;
else if (Current_state==State_byte3&&Fifo_data_en_dl1)
Fifo_data_byte3 <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte2 <=0;
else if (Current_state==State_byte2&&Fifo_data_en_dl1)
Fifo_data_byte2 <=Fifo_data_dl1;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte1 <=0;
else if (Current_state==State_byte1&&Fifo_data_en_dl1)
Fifo_data_byte1 <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_byte0 <=0;
else if (Current_state==State_byte0&&Fifo_data_en_dl1)
Fifo_data_byte0 <=Fifo_data_dl1;
always @ (Current_state or Fifo_data_byte3 or Fifo_data_byte2 or Fifo_data_byte1 or Fifo_data_byte0 )
case (Current_state)
State_be0:
Din ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_byte0};
State_be1:
Din ={4'b1001,Fifo_data_byte3,24'h0};
State_be2:
Din ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
State_be3:
Din ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
default:
Din ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_byte0};
endcase
always @ (Current_state or Fifo_data_en)
if (Current_state==State_be0||Current_state==State_be1||
Current_state==State_be2||Current_state==State_be3||
(Current_state==State_byte0&&Fifo_data_en))
Wr_en <=1;
else
Wr_en <=0;
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Packet_number_add <=0;
else if (Current_state==State_be0||Current_state==State_be1||
Current_state==State_be2||Current_state==State_be3)
Packet_number_add <=1;
else
Packet_number_add <=0;
//******************************************************************************
//domain Clk_SYS,read data from dprom.b-port for read
//******************************************************************************
 
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Current_state_SYS <=SYS_idle;
else
Current_state_SYS <=Next_state_SYS;
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
case (Current_state_SYS)
SYS_idle:
if (Rx_mac_rd&&Rx_mac_ra)
Next_state_SYS =SYS_read;
else
Next_state_SYS =Current_state_SYS;
SYS_read:
if (Dout[35])
Next_state_SYS =SYS_wait_end;
// else if (Empty)
// Next_state_SYS =FF_emtpy_err;
else
Next_state_SYS =Current_state_SYS;
FF_emtpy_err:
if (!Empty)
Next_state_SYS =SYS_read;
else
Next_state_SYS =Current_state_SYS;
SYS_wait_end:
if (!Rx_mac_rd)
Next_state_SYS =SYS_idle;
else
Next_state_SYS =Current_state_SYS;
default:
Next_state_SYS =SYS_idle;
endcase
//gen Rx_mac_ra
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Packet_number_add_dl1 <=0;
Packet_number_add_dl2 <=0;
end
else
begin
Packet_number_add_dl1 <=Packet_number_add;
Packet_number_add_dl2 <=Packet_number_add_dl1;
end
assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
 
always @ (Current_state_SYS or Next_state_SYS)
if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
Packet_number_sub =1;
else
Packet_number_sub =0;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Packet_number_inFF <=0;
else if (Packet_number_add_edge&&!Packet_number_sub)
Packet_number_inFF <=Packet_number_inFF + 1;
else if (!Packet_number_add_edge&&Packet_number_sub)
Packet_number_inFF <=Packet_number_inFF - 1;
always @ (Packet_number_inFF)
if (Packet_number_inFF==0)
Rx_mac_ra =0;
else
Rx_mac_ra =1;
//control Add_rd signal;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_rd <=0;
else if (Current_state_SYS==SYS_read&&!Dout[35])
Add_rd <=Add_rd + 1;
 
//
always @ (posedge Reset or posedge Clk_SYS)
if (Reset)
Add_rd_gray <=0;
else
Add_rd_gray <={ Add_rd[8],
Add_rd[8]^Add_rd[7],
Add_rd[7]^Add_rd[6],
Add_rd[6]^Add_rd[5],
Add_rd[5]^Add_rd[4],
Add_rd[4]^Add_rd[3],
Add_rd[3]^Add_rd[2],
Add_rd[2]^Add_rd[1],
Add_rd[1]^Add_rd[0]};
//
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr_gray_dl1 <=0;
else
Add_wr_gray_dl1 <=Add_wr_gray;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr_ungray <=0;
else
Add_wr_ungray <={
Add_wr_gray_dl1[8],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };
//empty signal gen
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Empty <=1;
else if (Add_rd==Add_wr_ungray)
Empty <=1;
else
Empty <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Dout_dl1 <=0;
else
Dout_dl1 <=Dout;
 
assign Rx_mac_data =Dout_dl1[31:0];
 
always @ (RX_APPEND_CRC or Dout_dl1 or Dout)
if (RX_APPEND_CRC)
Rx_mac_BE =Dout_dl1[33:32];
else
Rx_mac_BE =Dout[33:32];
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_pa <=0;
else if (Rx_mac_sop_tmp_dl1&&Next_state_SYS==SYS_read)
Rx_mac_pa <=1;
else if(Rx_mac_eop)
Rx_mac_pa <=0;
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Rx_mac_sop_tmp <=0;
else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
Rx_mac_sop_tmp <=1;
else
Rx_mac_sop_tmp <=0;
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Rx_mac_sop_tmp_dl1 <=0;
Rx_mac_sop <=0;
end
else
begin
Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;
Rx_mac_sop <=Rx_mac_sop_tmp_dl1;
end
 
always @(RX_APPEND_CRC or Dout_dl1 or Dout)
if(RX_APPEND_CRC)
Rx_mac_eop =Dout_dl1[35];
else
Rx_mac_eop =Dout[35];
//******************************************************************************
 
duram #(36,9,"M4K") U_duram(
.data_a (Din ),
.wren_a (Wr_en ),
.address_a (Add_wr ),
.address_b (Add_rd ),
.clock_a (Clk_MAC ),
.clock_b (Clk_SYS ),
.q_b (Dout ));
 
endmodule
 
 
 
 
 
/trunk/rtl/verilog/MAC_rx/MAC_rx_add_chk.v
0,0 → 1,131
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_rx_add_chk.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module MAC_rx_add_chk (
Reset ,
Clk ,
Init ,
data ,
MAC_add_en ,
MAC_rx_add_chk_err ,
//From CPU
MAC_rx_add_chk_en ,
MAC_add_prom_data ,
MAC_add_prom_add ,
MAC_add_prom_wr
 
);
input Reset ;
input Clk ;
input Init ;
input[7:0] data ;
input MAC_add_en ;
output MAC_rx_add_chk_err ;
//From CPU
input MAC_rx_add_chk_en ;
input[7:0] MAC_add_prom_data ;
input[2:0] MAC_add_prom_add ;
input MAC_add_prom_wr ;
 
//******************************************************************************
//internal signals
//******************************************************************************
reg[2:0] addra;
wire[2:0] addrb;
wire[7:0] dinb;
wire[7:0] douta;
wire web;
 
reg MAC_rx_add_chk_err;
reg MAC_add_prom_wr_dl1;
reg MAC_add_prom_wr_dl2;
//******************************************************************************
//write data from cpu to prom
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
MAC_add_prom_wr_dl1 <=0;
MAC_add_prom_wr_dl2 <=0;
end
else
begin
MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;
MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;
end
assign web =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;
assign addrb =MAC_add_prom_add;
assign dinb =MAC_add_prom_data;
 
//******************************************************************************
//mac add verify
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
addra <=0;
else if (Init)
addra <=0;
else if (MAC_add_en)
addra <=addra + 1;
always @ (posedge Clk or posedge Reset)
if (Reset)
MAC_rx_add_chk_err <=0;
else if (Init)
MAC_rx_add_chk_err <=0;
else if (MAC_rx_add_chk_en&&MAC_add_en&&douta!=data)
MAC_rx_add_chk_err <=1;
 
//******************************************************************************
//a port for read ,b port for write .
//******************************************************************************
duram #(8,3,"M512","DUAL_PORT") U_duram(
.data_a (dinb ),
.wren_a (web ),
.address_a (addra ),
.address_b (addrb ),
.clock_a (Clk ),
.clock_b (Clk ),
.q_b (douta ));
 
endmodule
/trunk/rtl/verilog/MAC_rx/Broadcast_filter.v
0,0 → 1,94
//////////////////////////////////////////////////////////////////////
//// ////
//// Broadcast_filter.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module Broadcast_filter (
Reset ,
Clk ,
//MAC_rx_ctrl ,
broadcast_ptr ,
broadcast_drop ,
//FromCPU ,
broadcast_filter_en ,
broadcast_MAX ,
 
);
input Reset ;
input Clk ;
//MAC_rx_ctrl
input broadcast_ptr ;
output broadcast_drop ;
//FromCPU ;
input broadcast_filter_en ;
input [15:0] broadcast_MAX ;
 
//******************************************************************************
//internal signals
//******************************************************************************
reg [15:0] time_counter ;
reg [15:0] broadcast_counter ;
reg broadcast_drop ;
//******************************************************************************
//
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
time_counter <=0;
else
time_counter <=time_counter+1;
 
always @ (posedge Clk or posedge Reset)
if (Reset)
broadcast_counter <=0;
else if (time_counter==16'hffff)
broadcast_counter <=0;
else if (broadcast_ptr)
broadcast_counter <=broadcast_counter+1;
always @ (posedge Clk or posedge Reset)
if (Reset)
broadcast_drop <=0;
else if(broadcast_counter>broadcast_MAX)
broadcast_drop <=1;
else
broadcast_drop <=0;
 
endmodule
/trunk/rtl/verilog/MAC_tx/flow_ctrl.v
0,0 → 1,193
//////////////////////////////////////////////////////////////////////
//// ////
//// flow_ctrl.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module flow_ctrl
(
Reset ,
Clk ,
//host processor ,
tx_pause_en ,
xoff_cpu ,
xon_cpu ,
//MAC_rx_flow ,
pause_quanta ,
pause_quanta_val ,
//MAC_tx_ctrl ,
pause_apply ,
pause_quanta_sub ,
xoff_gen ,
xoff_gen_complete ,
xon_gen ,
xon_gen_complete
 
);
 
input Reset ;
input Clk ;
//host processor ;
input tx_pause_en ;
input xoff_cpu ;
input xon_cpu ;
//MAC_rx_flow ;
input [15:0] pause_quanta ;
input pause_quanta_val ;
//MAC_tx_ctrl ;
output pause_apply ;
input pause_quanta_sub ;
output xoff_gen ;
input xoff_gen_complete ;
output xon_gen ;
input xon_gen_complete ;
//******************************************************************************
//internal signals
//******************************************************************************
reg xoff_cpu_dl1 ;
reg xoff_cpu_dl2 ;
reg xon_cpu_dl1 ;
reg xon_cpu_dl2 ;
reg [15:0] pause_quanta_dl1 ;
reg pause_quanta_val_dl1 ;
reg pause_quanta_val_dl2 ;
reg pause_apply ;
reg xoff_gen ;
reg xon_gen ;
reg [15:0] pause_quanta_counter ;
reg tx_pause_en_dl1 ;
reg tx_pause_en_dl2 ;
//******************************************************************************
//boundery signal processing
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
xoff_cpu_dl1 <=0;
xoff_cpu_dl2 <=0;
end
else
begin
xoff_cpu_dl1 <=xoff_cpu;
xoff_cpu_dl2 <=xoff_cpu_dl1;
end
 
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
xon_cpu_dl1 <=0;
xon_cpu_dl2 <=0;
end
else
begin
xon_cpu_dl1 <=xon_cpu;
xon_cpu_dl2 <=xon_cpu_dl1;
end
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
pause_quanta_dl1 <=0;
end
else
begin
pause_quanta_dl1 <=pause_quanta;
end
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
pause_quanta_val_dl1 <=0;
pause_quanta_val_dl2 <=0;
end
else
begin
pause_quanta_val_dl1 <=pause_quanta_val;
pause_quanta_val_dl2 <=pause_quanta_val_dl1;
end
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
tx_pause_en_dl1 <=0;
tx_pause_en_dl2 <=0;
end
else
begin
tx_pause_en_dl1 <=tx_pause_en;
tx_pause_en_dl2 <=tx_pause_en_dl1;
end
 
//******************************************************************************
//gen output signals
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
xoff_gen <=0;
else if (xoff_gen_complete)
xoff_gen <=0;
else if (xoff_cpu_dl1&&!xoff_cpu_dl2)
xoff_gen <=1;
 
always @ (posedge Clk or posedge Reset)
if (Reset)
xon_gen <=0;
else if (xon_gen_complete)
xon_gen <=0;
else if (xon_cpu_dl1&&!xon_cpu_dl2)
xon_gen <=1;
 
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta_counter <=0;
else if(pause_quanta_val_dl1&&!pause_quanta_val_dl2)
pause_quanta_counter <=pause_quanta_dl1;
else if(pause_quanta_sub&&pause_quanta_counter!=0)
pause_quanta_counter <=pause_quanta_counter-1;
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_apply <=0;
else if(pause_quanta_counter==0)
pause_apply <=0;
else if (tx_pause_en_dl2)
pause_apply <=1;
endmodule
/trunk/rtl/verilog/MAC_tx/MAC_tx_addr_add.v
0,0 → 1,119
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_tx_addr_add.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module MAC_tx_addr_add (
Reset ,
Clk ,
MAC_tx_addr_init ,
MAC_tx_addr_rd ,
MAC_tx_addr_data ,
//CPU ,
MAC_add_prom_data ,
MAC_add_prom_add ,
MAC_add_prom_wr
 
);
 
input Reset ;
input Clk ;
input MAC_tx_addr_rd ;
input MAC_tx_addr_init ;
output[7:0] MAC_tx_addr_data ;
//CPU ;
input[7:0] MAC_add_prom_data ;
input[2:0] MAC_add_prom_add ;
input MAC_add_prom_wr ;
 
//******************************************************************************
//internal signals
//******************************************************************************
reg[2:0] addra;
wire[2:0] addrb;
wire[7:0] dinb;
wire[7:0] douta;
wire web;
 
 
reg MAC_add_prom_wr_dl1;
reg MAC_add_prom_wr_dl2;
//******************************************************************************
//write data from cpu to prom
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
MAC_add_prom_wr_dl1 <=0;
MAC_add_prom_wr_dl2 <=0;
end
else
begin
MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;
MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;
end
assign web =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;
assign addrb =MAC_add_prom_add;
assign dinb =MAC_add_prom_data;
 
//******************************************************************************
//read data from cpu to prom
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
addra <=0;
else if (MAC_tx_addr_init)
addra <=0;
else if (MAC_tx_addr_rd)
addra <=addra + 1;
assign MAC_tx_addr_data=douta;
//******************************************************************************
//a port for read ,b port for write .
//******************************************************************************
duram #(8,3,"M512","DUAL_PORT") U_duram(
.data_a (dinb ),
.wren_a (web ),
.address_a (addra ),
.address_b (addrb ),
.clock_a (Clk ),
.clock_b (Clk ),
.q_b (douta ));
endmodule
 
/trunk/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v
0,0 → 1,632
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_tx_ctrl.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module MAC_tx_ctrl (
Reset ,
Clk ,
//CRC_gen Interface
CRC_init ,
Frame_data ,
Data_en ,
CRC_rd ,
CRC_end ,
CRC_out ,
//Ramdon_gen interfac
Random_init ,
RetryCnt ,
Random_time_meet ,
//flow control
pause_apply ,
pause_quanta_sub ,
xoff_gen ,
xoff_gen_complete ,
xon_gen ,
xon_gen_complete ,
//MAC_tx_FF
Fifo_data ,
Fifo_rd ,
Fifo_eop ,
Fifo_da ,
Fifo_rd_finish ,
Fifo_rd_retry ,
Fifo_ra ,
Fifo_data_err_empty ,
Fifo_data_err_full ,
//RMII
TxD ,
TxEn ,
CRS ,
//MAC_tx_addr_add
MAC_tx_addr_rd ,
MAC_tx_addr_data ,
MAC_tx_addr_init ,
//RMON
Tx_pkt_type_rmon ,
Tx_pkt_length_rmon ,
Tx_apply_rmon ,
Tx_pkt_err_type_rmon,
//CPU
pause_frame_send_en ,
pause_quanta_set ,
MAC_tx_add_en ,
FullDuplex ,
MaxRetry ,
IFGset
);
 
input Reset ;
input Clk ;
//CRC_gen Interface
output CRC_init ;
output[7:0] Frame_data ;
output Data_en ;
output CRC_rd ;
input CRC_end ;
input[7:0] CRC_out ;
//Ramdon_gen interface
output Random_init ;
output[3:0] RetryCnt ;
input Random_time_meet ;//levle hight indicate random time passed away
//flow control
input pause_apply ;
output pause_quanta_sub ;
input xoff_gen ;
output xoff_gen_complete ;
input xon_gen ;
output xon_gen_complete ;
//MAC_rx_FF
input[7:0] Fifo_data ;
output Fifo_rd ;
input Fifo_eop ;
input Fifo_da ;
output Fifo_rd_finish ;
output Fifo_rd_retry ;
input Fifo_ra ;
input Fifo_data_err_empty ;
input Fifo_data_err_full ;
//RMII
output[7:0] TxD ;
output TxEn ;
input CRS ;
//MAC_tx_addr_add
output MAC_tx_addr_init ;
output MAC_tx_addr_rd ;
input[7:0] MAC_tx_addr_data ;
//RMON
output[2:0] Tx_pkt_type_rmon ;
output[15:0] Tx_pkt_length_rmon ;
output Tx_apply_rmon ;
output[2:0] Tx_pkt_err_type_rmon;
//CPU
input pause_frame_send_en ;
input[15:0] pause_quanta_set ;
input MAC_tx_add_en ;
input FullDuplex ;
input[3:0] MaxRetry ;
input[5:0] IFGset ;
//******************************************************************************
//internal signals
//******************************************************************************
parameter StateIdle =4'd00;
parameter StatePreamble =4'd01;
parameter StateSFD =4'd02;
parameter StateData =4'd03;
parameter StatePause =4'd04;
parameter StatePAD =4'd05;
parameter StateFCS =4'd06;
parameter StateIFG =4'd07;
parameter StateJam =4'd08;
parameter StateBackOff =4'd09;
parameter StateJamDrop =4'd10;
parameter StateFFEmptyDrop =4'd11;
parameter StateSwitchNext =4'd12;
parameter StateDefer =4'd13;
parameter StateSendPauseFrame =4'd14;
 
reg[3:0] Current_state /*synthesis syn_keep=1 */;
reg[3:0] Next_state;
reg[5:0] IFG_counter;
reg[4:0] Preamble_counter;//
reg[7:0] TxD_tmp ;
reg TxEn_tmp ;
reg[15:0] Tx_pkt_length_rmon ;
reg Tx_apply_rmon ;
reg[2:0] Tx_pkt_err_type_rmon;
reg[3:0] RetryCnt ;
reg Random_init ;
reg Fifo_rd_finish ;
reg Fifo_rd_retry ;
reg[7:0] TxD ;
reg TxEn ;
reg CRC_init ;
reg Data_en ;
reg CRC_rd ;
reg Fifo_rd ;
reg MAC_tx_addr_rd ;
reg MAC_header_slot ;
reg MAC_header_slot_tmp ;
reg[2:0] Tx_pkt_type_rmon ;
wire Collision ;
reg MAC_tx_addr_init ;
reg Src_MAC_ptr ;
reg[7:0] IPLengthCounter ;//for pad append
reg[1:0] PADCounter ;
reg[7:0] JamCounter ;
reg PktDrpEvenPtr ;
reg[7:0] pause_counter ;
reg pause_quanta_sub ;
reg pause_frame_send_en_dl1 ;
reg[15:0] pause_quanta_set_dl1 ;
reg [4:0] send_pause_frame_counter ;
reg xoff_gen_reg ;
reg xon_gen_reg ;
reg xoff_gen_complete ;
reg xon_gen_complete ;
//******************************************************************************
//boundery signal processing
//******************************************************************************
always @(posedge Clk or posedge Reset)
if (Reset)
begin
pause_frame_send_en_dl1 <=0;
pause_quanta_set_dl1 <=0;
end
else
begin
pause_frame_send_en_dl1 <=pause_frame_send_en ;
pause_quanta_set_dl1 <=pause_quanta_set ;
end
 
//******************************************************************************
//state machine
//******************************************************************************
assign Collision=TxEn&CRS;
 
always @(posedge Clk or posedge Reset)
if (Reset)
send_pause_frame_counter <=0;
else if(Current_state!=StateSendPauseFrame)
send_pause_frame_counter <=0;
else
send_pause_frame_counter <=send_pause_frame_counter +1;
 
always @(posedge Clk or posedge Reset)
if (Reset)
pause_counter <=0;
else if (Current_state!=StatePause)
pause_counter <=0;
else
pause_counter <=pause_counter+1;
always @(posedge Clk or posedge Reset)
if (Reset)
IPLengthCounter <=0;
else if (Current_state==StateSwitchNext)
IPLengthCounter <=0;
else if (IPLengthCounter!=8'hff&&((Current_state==StateData)||
(PADCounter==0&&Current_state==StatePAD)))
IPLengthCounter <=IPLengthCounter+1;
 
always @(posedge Clk or posedge Reset)
if (Reset)
PADCounter <=0;
else if (Current_state!=StatePAD)
PADCounter <=0;
else
PADCounter <=PADCounter+1;
 
always @(posedge Clk or posedge Reset)
if (Reset)
Current_state <=StateDefer;
else
Current_state <=Next_state;
always @ (*)
case (Current_state)
StateDefer:
if ((FullDuplex)||(!FullDuplex&&!CRS))
Next_state=StateIFG;
else
Next_state=Current_state;
StateIFG:
if (!FullDuplex&&CRS)
Next_state=StateDefer;
 
Next_state=StateIdle;
else
Next_state=Current_state;
StateIdle:
if (!FullDuplex&&CRS)
Next_state=StateDefer;
else if (pause_apply)
Next_state=StatePause;
else if ((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg)))
Next_state=StatePreamble;
else
Next_state=Current_state;
StatePause:
if (pause_counter==512/8)
Next_state=StateDefer;
else
Next_state=Current_state;
StatePreamble:
if (!FullDuplex&&Collision)
Next_state=StateJam;
else if ((FullDuplex&&Preamble_counter==7)||(!FullDuplex&&!Collision&&Preamble_counter==7))
Next_state=StateSFD;
else
Next_state=Current_state;
StateSFD:
if (!FullDuplex&&Collision)
Next_state=StateJam;
else if (pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg))
Next_state=StateSendPauseFrame;
else
Next_state=StateData;
StateSendPauseFrame:
if (send_pause_frame_counter==19)
Next_state=StatePAD;
else
Next_state=Current_state;
StateData:
if (!FullDuplex&&Collision)
Next_state=StateJam;
else if (Fifo_data_err_empty)
Next_state=StateFFEmptyDrop;
else if (Fifo_eop&&IPLengthCounter>=60)//IP+MAC+TYPE=60
Next_state=StateFCS;
else if (Fifo_eop)
Next_state=StatePAD;
else
Next_state=StateData;
StatePAD:
if (!FullDuplex&&Collision)
Next_state=StateJam;
else if (IPLengthCounter>=60)
Next_state=StateFCS;
else
Next_state=Current_state;
StateJam:
if (RetryCnt<=MaxRetry&&JamCounter==16)
Next_state=StateBackOff;
else if (RetryCnt>MaxRetry)
Next_state=StateJamDrop;
else
Next_state=Current_state;
StateBackOff:
if (Random_time_meet)
Next_state =StateDefer;
else
Next_state =Current_state;
StateFCS:
if (!FullDuplex&&Collision)
Next_state =StateJam;
else if (pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg))
Next_state =StateDefer;
else if (CRC_end)
Next_state =StateSwitchNext;
else
Next_state =Current_state;
StateFFEmptyDrop:
if (Fifo_eop)
Next_state =StateSwitchNext;
else
Next_state =Current_state;
StateJamDrop:
if (Fifo_eop)
Next_state =StateSwitchNext;
else
Next_state =Current_state;
StateSwitchNext:
Next_state =StateDefer;
default:
Next_state =StateDefer;
endcase
 
always @ (posedge Clk or posedge Reset)
if (Reset)
JamCounter <=0;
else if (Current_state!=StateJam)
JamCounter <=0;
else if (Current_state==StateJam)
JamCounter <=JamCounter+1;
always @ (posedge Clk or posedge Reset)
if (Reset)
RetryCnt <=0;
else if (Current_state==StateSwitchNext)
RetryCnt <=0;
else if (Current_state==StateJam&&Next_state==StateBackOff)
RetryCnt <=RetryCnt + 1;
always @ (posedge Clk or posedge Reset)
if (Reset)
IFG_counter <=0;
else if (Current_state!=StateIFG)
IFG_counter <=0;
else
IFG_counter <=IFG_counter + 1;
 
always @ (posedge Clk or posedge Reset)
if (Reset)
Preamble_counter <=0;
else if (Current_state!=StatePreamble)
Preamble_counter <=0;
else
Preamble_counter <=Preamble_counter+ 1;
always @ (posedge Clk or posedge Reset)
if (Reset)
PktDrpEvenPtr <=0;
else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop)
PktDrpEvenPtr <=~PktDrpEvenPtr;
//******************************************************************************
//generate output signals
//******************************************************************************
//CRC related
always @(Current_state)
if (Current_state==StateSFD)
CRC_init =1;
else
CRC_init =0;
assign Frame_data=TxD_tmp;
 
always @(Current_state)
if (Current_state==StateData||Current_state==StatePAD)
Data_en =1;
else
Data_en =0;
always @(Current_state)
if (Current_state==StateFCS)
CRC_rd =1;
else
CRC_rd =0;
//Ramdon_gen interface
always @(Current_state or Next_state)
if (Current_state==StateJam&&Next_state==StateBackOff)
Random_init =1;
else
Random_init =0;
 
//MAC_rx_FF
//data have one cycle delay after fifo read signals
always @ (*)
if (Current_state==StateData ||
Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg)) ||
Current_state==StateJamDrop&&PktDrpEvenPtr||
Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )
Fifo_rd =1;
else
Fifo_rd =0;
always @ (Current_state)
if (Current_state==StateSwitchNext)
Fifo_rd_finish =1;
else
Fifo_rd_finish =0;
always @ (Current_state)
if (Current_state==StateJam)
Fifo_rd_retry =1;
else
Fifo_rd_retry =0;
//RMII
always @(Current_state)
if (Current_state==StatePreamble||Current_state==StateSFD||
Current_state==StateData||
Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)
TxEn_tmp =1;
else
TxEn_tmp =0;
 
//gen txd data
always @(*)
case (Current_state)
StatePreamble:
TxD_tmp =8'h55;
StateSFD:
TxD_tmp =8'hd5;
StateData:
if (Src_MAC_ptr)
TxD_tmp =MAC_tx_addr_data;
else
TxD_tmp =Fifo_data;
StateSendPauseFrame:
if (Src_MAC_ptr)
TxD_tmp =MAC_tx_addr_data;
else
case (send_pause_frame_counter)
5'd0: TxD_tmp =8'h01;
5'd1: TxD_tmp =8'h80;
5'd2: TxD_tmp =8'hc2;
5'd3: TxD_tmp =8'h00;
5'd4: TxD_tmp =8'h00;
5'd5: TxD_tmp =8'h01;
5'd12: TxD_tmp =8'h88;//type
5'd13: TxD_tmp =8'h08;//
5'd14: TxD_tmp =8'h00;//opcode
5'd15: TxD_tmp =8'h01;
5'd16: TxD_tmp =pause_quanta_set_dl1[15:8];
5'd17: TxD_tmp =pause_quanta_set_dl1[7:0];
default:TxD_tmp =0;
endcase
StatePAD:
TxD_tmp =8'h00;
StateJam:
TxD_tmp =8'h01; //jam sequence
StateFCS:
TxD_tmp =CRC_out;
default:
TxD_tmp =2'b0;
endcase
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
TxD <=0;
TxEn <=0;
end
else
begin
TxD <=TxD_tmp;
TxEn <=TxEn_tmp;
end
//RMON
 
 
always @ (posedge Clk or posedge Reset)
if (Reset)
Tx_pkt_length_rmon <=0;
else if (Current_state==StateSFD)
Tx_pkt_length_rmon <=4;
else if (Current_state==StateData)
Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1;
always @ (posedge Clk or posedge Reset)
if (Reset)
Tx_apply_rmon <=0;
else if ((Fifo_eop&&Current_state==StateJamDrop)||
(Fifo_eop&&Current_state==StateFFEmptyDrop)||
CRC_end)
Tx_apply_rmon <=1;
else
Tx_apply_rmon <=0;
always @ (posedge Clk or posedge Reset)
if (Reset)
Tx_pkt_err_type_rmon <=0;
else if(Fifo_eop&&Current_state==StateJamDrop)
Tx_pkt_err_type_rmon <=3'b001;//
else if(Fifo_eop&&Current_state==StateFFEmptyDrop)
Tx_pkt_err_type_rmon <=3'b010;//underflow
else if(Fifo_eop&&Fifo_data_err_full)
Tx_pkt_err_type_rmon <=3'b011;//overflow
else if(CRC_end)
Tx_pkt_err_type_rmon <=3'b100;
always @ (posedge Clk or posedge Reset)
if (Reset)
MAC_header_slot_tmp <=0;
else if(Current_state==StateSFD&&Next_state==StateData)
MAC_header_slot_tmp <=1;
else
MAC_header_slot_tmp <=0;
always @ (posedge Clk or posedge Reset)
if (Reset)
MAC_header_slot <=0;
else
MAC_header_slot <=MAC_header_slot_tmp;
 
always @ (posedge Clk or posedge Reset)
if (Reset)
Tx_pkt_type_rmon <=0;
else if (Current_state==StateSendPauseFrame)
Tx_pkt_type_rmon <=3'b100;
else if(MAC_header_slot)
Tx_pkt_type_rmon <={1'b0,TxD_tmp};
 
always @(Tx_pkt_length_rmon)
if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)
Src_MAC_ptr =1;
else
Src_MAC_ptr =0;
 
//MAC_tx_addr_add
always @ (Tx_pkt_length_rmon or Fifo_rd or Src_MAC_ptr)
if (Src_MAC_ptr&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))
MAC_tx_addr_rd =1;
else
MAC_tx_addr_rd =0;
 
always @ (Tx_pkt_length_rmon or Fifo_rd)
if ((Tx_pkt_length_rmon==5)&&Fifo_rd)
MAC_tx_addr_init=1;
else
MAC_tx_addr_init=0;
 
//flow control
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta_sub <=0;
else if(pause_counter==512/8)
pause_quanta_sub <=1;
else
pause_quanta_sub <=0;
 
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
xoff_gen_reg <=0;
xon_gen_reg <=0;
end
else if (Current_state==StateDefer)
begin
xoff_gen_reg <=xoff_gen;
xon_gen_reg <=xon_gen;
end
always @ (posedge Clk or posedge Reset)
if (Reset)
xoff_gen_complete <=0;
else if(Current_state==StateDefer&&xoff_gen_reg)
xoff_gen_complete <=1;
else
xoff_gen_complete <=0;
always @ (posedge Clk or posedge Reset)
if (Reset)
xon_gen_complete <=0;
else if(Current_state==StateDefer&&xon_gen_reg)
xon_gen_complete <=1;
else
xon_gen_complete <=0;
 
endmodule
/trunk/rtl/verilog/MAC_tx/CRC_gen.v
0,0 → 1,158
//////////////////////////////////////////////////////////////////////
//// ////
//// CRC_gen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module CRC_gen (
Reset ,
Clk ,
Init ,
Frame_data ,
Data_en ,
CRC_rd ,
CRC_end ,
CRC_out
 
);
input Reset ;
input Clk ;
input Init ;
input[7:0] Frame_data ;
input Data_en ;
input CRC_rd ;
output[7:0] CRC_out ;
output CRC_end ;
 
//******************************************************************************
//internal signals
//******************************************************************************
reg[7:0] CRC_out ;
reg[31:0] CRC_reg;
reg CRC_end;
reg[3:0] Counter;
//******************************************************************************
//******************************************************************************
//input data width is 8bit, and the first bit is bit[0]
function[31:0] NextCRC;
input[7:0] D;
input[31:0] C;
reg[31:0] NewCRC;
begin
NewCRC[0]=C[24]^C[30]^D[1]^D[7];
NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
NewCRC[20]=C[12]^C[28]^D[3];
NewCRC[21]=C[13]^C[29]^D[2];
NewCRC[22]=C[14]^C[24]^D[7];
NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
NewCRC[31]=C[23]^C[29]^D[2];
NextCRC=NewCRC;
end
endfunction
//******************************************************************************
 
always @ (posedge Clk or posedge Reset)
if (Reset)
CRC_reg <=32'hffffffff;
else if (Init)
CRC_reg <=32'hffffffff;
else if (Data_en)
CRC_reg <=NextCRC(Frame_data,CRC_reg);
else if (CRC_rd)
CRC_reg <={CRC_reg[23:0],8'hff};
always @ (CRC_rd or CRC_reg)
if (CRC_rd)
CRC_out <=~{
CRC_reg[24],
CRC_reg[25],
CRC_reg[26],
CRC_reg[27],
CRC_reg[28],
CRC_reg[29],
CRC_reg[30],
CRC_reg[31]
};
else
CRC_out <=0;
//caculate CRC out length ,4 cycles
//CRC_end aligned to last CRC checksum data
always @(posedge Clk or posedge Reset)
if (Reset)
Counter <=0;
else if (!CRC_rd)
Counter <=0;
else
Counter <=Counter + 1;
always @ (Counter)
if (Counter==3)
CRC_end=1;
else
CRC_end=0;
 
endmodule
 
 
/trunk/rtl/verilog/MAC_tx/MAC_tx_FF.v
0,0 → 1,738
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_tx_FF.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module MAC_tx_FF (
Reset ,
Clk_MAC ,
Clk_SYS ,
//MAC_rx_ctrl interface
Fifo_data ,
Fifo_rd ,
Fifo_rd_finish ,
Fifo_rd_retry ,
Fifo_eop ,
Fifo_da ,
Fifo_ra ,
Fifo_data_err_empty ,
Fifo_data_err_full ,
//user interface
Tx_mac_wa ,
Tx_mac_wr ,
Tx_mac_data ,
Tx_mac_BE ,
Tx_mac_sop ,
Tx_mac_eop ,
//host interface
FullDuplex ,
Tx_Hwmark ,
Tx_Lwmark
 
);
input Reset ;
input Clk_MAC ;
input Clk_SYS ;
//MAC_tx_ctrl
output[7:0] Fifo_data ;
input Fifo_rd ;
input Fifo_rd_finish ;
input Fifo_rd_retry ;
output Fifo_eop ;
output Fifo_da ;
output Fifo_ra ;
output Fifo_data_err_empty ;
output Fifo_data_err_full ;
//user interface
output Tx_mac_wa ;
input Tx_mac_wr ;
input[31:0] Tx_mac_data ;
input [1:0] Tx_mac_BE ;//big endian
input Tx_mac_sop ;
input Tx_mac_eop ;
//host interface
input FullDuplex ;
input[4:0] Tx_Hwmark ;
input[4:0] Tx_Lwmark ;
//******************************************************************************
//internal signals
//******************************************************************************
parameter MAC_byte3 =4'd00;
parameter MAC_byte2 =4'd01;
parameter MAC_byte1 =4'd02;
parameter MAC_byte0 =4'd03;
parameter MAC_BE0 =4'd04;
parameter MAC_BE3 =4'd05;
parameter MAC_BE2 =4'd06;
parameter MAC_BE1 =4'd07;
parameter MAC_retry =4'd08;
parameter MAC_idle =4'd09;
parameter MAC_FFEmpty =4'd10;
parameter MAC_FFEmpty_drop =4'd11;
parameter MAC_pkt_sub =4'd12;
parameter MAC_FF_Err =4'd13;
 
 
reg[3:0] Current_state_MAC /* synthesis syn_preserve =1 */ ;
reg[3:0] Current_state_MAC_reg /* synthesis syn_preserve =1 */ ;
reg[3:0] Next_state_MAC ;
 
 
parameter SYS_idle =4'd0;
parameter SYS_WaitSop =4'd1;
parameter SYS_SOP =4'd2;
parameter SYS_MOP =4'd3;
parameter SYS_DROP =4'd4;
parameter SYS_EOP_ok =4'd5;
parameter SYS_FFEmpty =4'd6;
parameter SYS_EOP_err =4'd7;
parameter SYS_SOP_err =4'd8;
 
reg[3:0] Current_state_SYS /* synthesis syn_preserve =1 */;
reg[3:0] Next_state_SYS;
 
reg [8:0] Add_wr ;
reg [8:0] Add_wr_ungray ;
reg [8:0] Add_wr_gray ;
reg [8:0] Add_wr_gray_dl1 ;
wire[8:0] Add_wr_gray_tmp ;
 
reg [8:0] Add_rd ;
reg [8:0] Add_rd_reg ;
reg [8:0] Add_rd_gray ;
reg [8:0] Add_rd_gray_dl1 ;
wire[8:0] Add_rd_gray_tmp ;
reg [8:0] Add_rd_ungray ;
wire[35:0] Din ;
wire[35:0] Dout ;
reg Wr_en ;
wire[8:0] Add_wr_pluse ;
wire[8:0] Add_wr_pluse_pluse;
wire[8:0] Add_rd_pluse ;
reg [8:0] Add_rd_reg_dl1 ;
reg Full /* synthesis syn_keep=1 */;
reg AlmostFull /* synthesis syn_keep=1 */;
reg Empty /* synthesis syn_keep=1 */;
 
reg Tx_mac_wa ;
reg Tx_mac_wr_dl1 ;
reg[31:0] Tx_mac_data_dl1 ;
reg[1:0] Tx_mac_BE_dl1 ;
reg Tx_mac_sop_dl1 ;
reg Tx_mac_eop_dl1 ;
reg FF_FullErr ;
wire[1:0] Dout_BE ;
wire Dout_eop ;
wire Dout_err ;
wire[31:0] Dout_data ;
reg[35:0] Dout_reg /* synthesis syn_preserve=1 */;
reg Packet_number_sub_dl1 ;
reg Packet_number_sub_dl2 ;
reg Packet_number_sub_edge /* synthesis syn_preserve=1 */;
reg Packet_number_add /* synthesis syn_preserve=1 */;
reg[4:0] Fifo_data_count ;
reg Fifo_ra /* synthesis syn_keep=1 */;
reg[7:0] Fifo_data ;
reg Fifo_da ;
reg Fifo_data_err_empty /* synthesis syn_preserve=1 */;
reg Fifo_eop ;
reg Fifo_rd_dl1 ;
reg Fifo_ra_tmp ;
reg[5:0] Packet_number_inFF /* synthesis syn_keep=1 */;
reg[5:0] Packet_number_inFF_reg /* synthesis syn_preserve=1 */;
reg Pkt_sub_apply_tmp ;
reg Pkt_sub_apply ;
reg Add_rd_reg_rdy_tmp ;
reg Add_rd_reg_rdy ;
reg Add_rd_reg_rdy_dl1 ;
reg Add_rd_reg_rdy_dl2 ;
//******************************************************************************
//write data to from FF .
//domain Clk_SYS
//******************************************************************************
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Current_state_SYS <=SYS_idle;
else
Current_state_SYS <=Next_state_SYS;
always @ (Current_state_SYS or Tx_mac_wr or Tx_mac_sop or Full or AlmostFull
or Tx_mac_eop )
case (Current_state_SYS)
SYS_idle:
if (Tx_mac_wr&&Tx_mac_sop&&!Full)
Next_state_SYS =SYS_SOP;
else
Next_state_SYS =Current_state_SYS ;
SYS_SOP:
Next_state_SYS =SYS_MOP;
SYS_MOP:
if (AlmostFull)
Next_state_SYS =SYS_DROP;
else if (Tx_mac_wr&&Tx_mac_sop)
Next_state_SYS =SYS_SOP_err;
else if (Tx_mac_wr&&Tx_mac_eop)
Next_state_SYS =SYS_EOP_ok;
else
Next_state_SYS =Current_state_SYS ;
SYS_EOP_ok:
Next_state_SYS =SYS_idle;
SYS_EOP_err:
Next_state_SYS =SYS_idle;
SYS_SOP_err:
Next_state_SYS =SYS_DROP;
SYS_DROP: //FIFO overflow
if (Tx_mac_wr&&Tx_mac_eop)
Next_state_SYS =SYS_EOP_err;
else
Next_state_SYS =Current_state_SYS ;
default:
Next_state_SYS =SYS_idle;
endcase
//delay signals
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Tx_mac_wr_dl1 <=0;
Tx_mac_data_dl1 <=0;
Tx_mac_BE_dl1 <=0;
Tx_mac_sop_dl1 <=0;
Tx_mac_eop_dl1 <=0;
end
else
begin
Tx_mac_wr_dl1 <=Tx_mac_wr ;
Tx_mac_data_dl1 <=Tx_mac_data ;
Tx_mac_BE_dl1 <=Tx_mac_BE ;
Tx_mac_sop_dl1 <=Tx_mac_sop ;
Tx_mac_eop_dl1 <=Tx_mac_eop ;
end
 
always @(Current_state_SYS)
if (Current_state_SYS==SYS_EOP_err)
FF_FullErr =1;
else
FF_FullErr =0;
 
reg Tx_mac_eop_gen;
 
always @(Current_state_SYS)
if (Current_state_SYS==SYS_EOP_err||Current_state_SYS==SYS_EOP_ok)
Tx_mac_eop_gen =1;
else
Tx_mac_eop_gen =0;
assign Din={Tx_mac_eop_gen,FF_FullErr,Tx_mac_BE_dl1,Tx_mac_data_dl1};
 
always @(Current_state_SYS or Tx_mac_wr_dl1)
if ((Current_state_SYS==SYS_SOP||Current_state_SYS==SYS_EOP_ok||
Current_state_SYS==SYS_MOP||Current_state_SYS==SYS_EOP_err)&&Tx_mac_wr_dl1)
Wr_en = 1;
else
Wr_en = 0;
//
always @ (posedge Reset or posedge Clk_SYS)
if (Reset)
Add_wr_gray <=0;
else
Add_wr_gray <={ Add_wr[8],
Add_wr[8]^Add_wr[7],
Add_wr[7]^Add_wr[6],
Add_wr[6]^Add_wr[5],
Add_wr[5]^Add_wr[4],
Add_wr[4]^Add_wr[3],
Add_wr[3]^Add_wr[2],
Add_wr[2]^Add_wr[1],
Add_wr[1]^Add_wr[0]};
 
//
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_rd_gray_dl1 <=0;
else
Add_rd_gray_dl1 <=Add_rd_gray;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_rd_ungray <=0;
else
Add_rd_ungray <={
Add_rd_gray_dl1[8],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1],
Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1]^Add_rd_gray_dl1[0] };
assign Add_wr_pluse =Add_wr+1;
assign Add_wr_pluse_pluse =Add_wr+4;
 
always @ (Add_wr_pluse or Add_rd_ungray)
if (Add_wr_pluse==Add_rd_ungray)
Full =1;
else
Full =0;
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
AlmostFull <=0;
else if (Add_wr_pluse_pluse==Add_rd_ungray)
AlmostFull <=1;
else
AlmostFull <=0;
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_wr <= 0;
else if (Wr_en&&!Full)
Add_wr <= Add_wr +1;
//
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Packet_number_sub_dl1 <=0;
Packet_number_sub_dl2 <=0;
end
else
begin
Packet_number_sub_dl1 <=Pkt_sub_apply;
Packet_number_sub_dl2 <=Packet_number_sub_dl1;
end
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Packet_number_sub_edge <=0;
else if (Packet_number_sub_dl1&!Packet_number_sub_dl2)
Packet_number_sub_edge <=1;
else
Packet_number_sub_edge <=0;
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Packet_number_add <=0;
else if (Current_state_SYS==SYS_EOP_ok||Current_state_SYS==SYS_EOP_err)
Packet_number_add <=1;
else
Packet_number_add <=0;
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Packet_number_inFF <=0;
else if (Packet_number_add&&!Packet_number_sub_edge)
Packet_number_inFF <=Packet_number_inFF + 1'b1;
else if (!Packet_number_add&&Packet_number_sub_edge)
Packet_number_inFF <=Packet_number_inFF - 1'b1;
 
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Packet_number_inFF_reg <=0;
else
Packet_number_inFF_reg <=Packet_number_inFF;
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
begin
Add_rd_reg_rdy_dl1 <=0;
Add_rd_reg_rdy_dl2 <=0;
end
else
begin
Add_rd_reg_rdy_dl1 <=Add_rd_reg_rdy;
Add_rd_reg_rdy_dl2 <=Add_rd_reg_rdy_dl1;
end
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Add_rd_reg_dl1 <=0;
else if (Add_rd_reg_rdy_dl1&!Add_rd_reg_rdy_dl2)
Add_rd_reg_dl1 <=Add_rd_reg;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Fifo_data_count <=0;
else if (FullDuplex)
Fifo_data_count <=Add_wr[8:4]-Add_rd_ungray[8:4];
else
Fifo_data_count <=Add_wr[8:4]-Add_rd_reg_dl1[8:4]; //for half duplex backoff requirement
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Fifo_ra_tmp <=0;
else if (Packet_number_inFF_reg>=1||Fifo_data_count>=Tx_Hwmark)
Fifo_ra_tmp <=1;
else
Fifo_ra_tmp <=0;
 
always @ (posedge Clk_SYS or posedge Reset)
if (Reset)
Tx_mac_wa <=0;
else if (Fifo_data_count>=Tx_Hwmark)
Tx_mac_wa <=0;
else if (Fifo_data_count<Tx_Lwmark)
Tx_mac_wa <=1;
 
//******************************************************************************
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//******************************************************************************
//rd data to from FF .
//domain Clk_MAC
//******************************************************************************
reg[35:0] Dout_dl1;
reg Dout_reg_en /* synthesis syn_keep=1 */;
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Dout_dl1 <=0;
else
Dout_dl1 <=Dout;
 
always @ (Current_state_MAC or Next_state_MAC)
if ((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3)
Dout_reg_en =1;
else
Dout_reg_en =0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Dout_reg <=0;
else if (Dout_reg_en)
Dout_reg <=Dout_dl1;
assign {Dout_eop,Dout_err,Dout_BE,Dout_data}=Dout_reg;
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Current_state_MAC <=MAC_idle;
else
Current_state_MAC <=Next_state_MAC;
always @ (Current_state_MAC or Fifo_rd or Dout_BE or Dout_eop or Fifo_rd_retry
or Fifo_rd_finish or Empty or Fifo_rd or Fifo_eop)
case (Current_state_MAC)
MAC_idle:
if (Empty&&Fifo_rd)
Next_state_MAC=MAC_FF_Err;
else if (Fifo_rd)
Next_state_MAC=MAC_byte3;
else
Next_state_MAC=Current_state_MAC;
MAC_byte3:
if (Fifo_rd_retry)
Next_state_MAC=MAC_retry;
else if (Fifo_rd_finish)
Next_state_MAC=MAC_pkt_sub;
else if (Fifo_rd)
Next_state_MAC=MAC_byte2;
else
Next_state_MAC=Current_state_MAC;
MAC_byte2:
if (Fifo_rd_retry)
Next_state_MAC=MAC_retry;
else if (Fifo_rd_finish)
Next_state_MAC=MAC_pkt_sub;
else if (Fifo_rd)
Next_state_MAC=MAC_byte1;
else
Next_state_MAC=Current_state_MAC;
MAC_byte1:
if (Fifo_rd_retry)
Next_state_MAC=MAC_retry;
else if (Fifo_rd_finish)
Next_state_MAC=MAC_pkt_sub;
else if (Fifo_rd)
Next_state_MAC=MAC_byte0;
else
Next_state_MAC=Current_state_MAC;
MAC_byte0:
if (Empty&&Fifo_rd)
Next_state_MAC=MAC_FFEmpty;
else if (Fifo_rd_retry)
Next_state_MAC=MAC_retry;
else if (Fifo_rd_finish)
Next_state_MAC=MAC_pkt_sub;
else if (Fifo_rd)
Next_state_MAC=MAC_byte3;
else
Next_state_MAC=Current_state_MAC;
MAC_retry:
Next_state_MAC=MAC_idle;
MAC_pkt_sub:
Next_state_MAC=MAC_idle;
MAC_FFEmpty:
if (!Empty)
Next_state_MAC=MAC_byte3;
else
Next_state_MAC=Current_state_MAC;
MAC_FF_Err: //stopped state-machine need change
Next_state_MAC=Current_state_MAC;
default
Next_state_MAC=MAC_idle;
endcase
//
always @ (posedge Reset or posedge Clk_MAC)
if (Reset)
Add_rd_gray <=0;
else
Add_rd_gray <={ Add_rd[8],
Add_rd[8]^Add_rd[7],
Add_rd[7]^Add_rd[6],
Add_rd[6]^Add_rd[5],
Add_rd[5]^Add_rd[4],
Add_rd[4]^Add_rd[3],
Add_rd[3]^Add_rd[2],
Add_rd[2]^Add_rd[1],
Add_rd[1]^Add_rd[0]};
//
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_gray_dl1 <=0;
else
Add_wr_gray_dl1 <=Add_wr_gray;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_wr_ungray <=0;
else
Add_wr_ungray <={
Add_wr_gray_dl1[8],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };
//empty
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Empty <=1;
else if (Add_rd==Add_wr_ungray)
Empty <=1;
else
Empty <=0;
//ra
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_ra <=0;
else
Fifo_ra <=Fifo_ra_tmp;
 
 
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Pkt_sub_apply_tmp <=0;
else if (Current_state_MAC==MAC_pkt_sub)
Pkt_sub_apply_tmp <=1;
else
Pkt_sub_apply_tmp <=0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Pkt_sub_apply <=0;
else if ((Current_state_MAC==MAC_pkt_sub)||Pkt_sub_apply_tmp)
Pkt_sub_apply <=1;
else
Pkt_sub_apply <=0;
 
//reg Add_rd for collison retry
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd_reg <=0;
else if (Fifo_rd_finish)
Add_rd_reg <=Add_rd;
 
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd_reg_rdy_tmp <=0;
else if (Fifo_rd_finish)
Add_rd_reg_rdy_tmp <=1;
else
Add_rd_reg_rdy_tmp <=0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd_reg_rdy <=0;
else if (Fifo_rd_finish||Add_rd_reg_rdy_tmp)
Add_rd_reg_rdy <=1;
else
Add_rd_reg_rdy <=0;
reg Add_rd_add /* synthesis syn_keep=1 */;
 
always @ (Current_state_MAC or Next_state_MAC)
if ((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3)
Add_rd_add =1;
else
Add_rd_add =0;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Add_rd <=0;
else if (Current_state_MAC==MAC_retry)
Add_rd <= Add_rd_reg;
else if (Add_rd_add)
Add_rd <= Add_rd + 1;
//gen Fifo_data
 
always @ (Dout_data or Current_state_MAC)
case (Current_state_MAC)
MAC_byte3:
Fifo_data =Dout_data[31:24];
MAC_byte2:
Fifo_data =Dout_data[23:16];
MAC_byte1:
Fifo_data =Dout_data[15:8];
MAC_byte0:
Fifo_data =Dout_data[7:0];
default:
Fifo_data =0;
endcase
//gen Fifo_da
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_rd_dl1 <=0;
else
Fifo_rd_dl1 <=Fifo_rd;
always @ (Current_state_MAC or Fifo_rd_dl1)
if (Current_state_MAC==MAC_byte0||Current_state_MAC==MAC_byte1||
Current_state_MAC==MAC_byte2||Current_state_MAC==MAC_byte3)
Fifo_da =Fifo_rd_dl1;
else
Fifo_da =0;
 
//gen Fifo_data_err_empty
assign Fifo_data_err_full=Dout_err;
//gen Fifo_data_err_empty
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Current_state_MAC_reg <=0;
else
Current_state_MAC_reg <=Current_state_MAC;
always @ (posedge Clk_MAC or posedge Reset)
if (Reset)
Fifo_data_err_empty <=0;
else if (Current_state_MAC_reg==MAC_FFEmpty)
Fifo_data_err_empty <=1;
else
Fifo_data_err_empty <=0;
always @ (posedge Clk_MAC)
if (Current_state_MAC_reg==MAC_FF_Err)
begin
$finish(2);
$display("mac_tx_FF meet error status at time :%t",$time);
end
 
always @ (Current_state_MAC or Dout_eop)
if (((Current_state_MAC==MAC_byte0&&Dout_BE==2'b00||
Current_state_MAC==MAC_byte1&&Dout_BE==2'b11||
Current_state_MAC==MAC_byte2&&Dout_BE==2'b10||
Current_state_MAC==MAC_byte3&&Dout_BE==2'b01)&&Dout_eop))
Fifo_eop =1;
else
Fifo_eop =0;
//******************************************************************************
//******************************************************************************
 
duram #(36,9,"M4K") U_duram(
.data_a (Din ),
.wren_a (Wr_en ),
.address_a (Add_wr ),
.address_b (Add_rd ),
.clock_a (Clk_SYS ),
.clock_b (Clk_MAC ),
.q_b (Dout ));
 
endmodule
/trunk/rtl/verilog/MAC_tx/Ramdon_gen.v
0,0 → 1,113
//////////////////////////////////////////////////////////////////////
//// ////
//// Ramdon_gen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module Ramdon_gen(
Reset ,
Clk ,
Init ,
RetryCnt ,
Random_time_meet
);
input Reset ;
input Clk ;
input Init ;
input[3:0] RetryCnt ;
output Random_time_meet;
 
//******************************************************************************
//internal signals
//******************************************************************************
reg[9:0] Random_sequence ;
reg[9:0] Ramdom ;
reg[9:0] Ramdom_counter ;
reg[7:0] Slot_time_counter; //256*2=512bit=1 slot time
reg Random_time_meet;
 
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
Random_sequence <=0;
else
Random_sequence <={Random_sequence[8:0],~(Random_sequence[2]^Random_sequence[9])};
always @ (RetryCnt or Random_sequence)
case (RetryCnt)
4'h0 : Ramdom={9'b0,Random_sequence[0]};
4'h1 : Ramdom={8'b0,Random_sequence[1:0]};
4'h2 : Ramdom={7'b0,Random_sequence[2:0]};
4'h3 : Ramdom={6'b0,Random_sequence[3:0]};
4'h4 : Ramdom={5'b0,Random_sequence[4:0]};
4'h5 : Ramdom={4'b0,Random_sequence[5:0]};
4'h6 : Ramdom={3'b0,Random_sequence[6:0]};
4'h7 : Ramdom={2'b0,Random_sequence[7:0]};
4'h8 : Ramdom={1'b0,Random_sequence[8:0]};
4'h9 : Ramdom={ Random_sequence[9:0]};
default : Ramdom={ Random_sequence[9:0]};
endcase
 
always @ (posedge Clk or posedge Reset)
if (Reset)
Slot_time_counter <=0;
else if(Init)
Slot_time_counter <=0;
else if(!Random_time_meet)
Slot_time_counter <=Slot_time_counter+1;
always @ (posedge Clk or posedge Reset)
if (Reset)
Ramdom_counter <=0;
else if (Init)
Ramdom_counter <=Ramdom;
else if (Ramdom_counter!=0&&Slot_time_counter==255)
Ramdom_counter <=Ramdom_counter -1 ;
always @ (posedge Clk or posedge Reset)
if (Reset)
Random_time_meet <=1;
else if (Init)
Random_time_meet <=0;
else if (Ramdom_counter==0)
Random_time_meet <=1;
endmodule
 
 
/trunk/rtl/verilog/RMON/RMON_addr_gen.v
0,0 → 1,282
//////////////////////////////////////////////////////////////////////
//// ////
//// RMON_addr_gen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
module RMON_addr_gen(
Clk ,
Reset ,
//RMON
Pkt_type_rmon ,
Pkt_length_rmon ,
Apply_rmon ,//pluse signal looks like eop
Pkt_err_type_rmon ,
//
Reg_apply ,
Reg_addr ,
Reg_data ,
Reg_next ,
//CPU
Reg_drop_apply
);
input Clk ;
input Reset ;
//RMON
input[2:0] Pkt_type_rmon ;
input[15:0] Pkt_length_rmon ;
input Apply_rmon ;//pluse signal looks like eop
input[2:0] Pkt_err_type_rmon ;
//RMON_ctrl
output Reg_apply ;
output[4:0] Reg_addr ;
output[15:0] Reg_data ;
input Reg_next ;
//CPU
output Reg_drop_apply ;
 
//******************************************************************************
//internal signals
//******************************************************************************
parameter StateIdle =5'b00001;
parameter StatePktLength =5'b00010;
parameter StatePktNumber =5'b00100;
parameter StatePktType =5'b01000;
parameter StatePktRange =5'b10000;
 
reg[4:0] CurrentState;
reg[4:0] NextState;
 
reg[2:0] PktTypeReg ;
reg[15:0] PktLengthReg ;
reg[2:0] PktErrTypeReg ;
 
reg Reg_apply ;
reg[4:0] Reg_addr ;
reg[15:0] Reg_data ;
reg Reg_drop_apply ;
//******************************************************************************
//register boundery signals
//******************************************************************************
reg Apply_rmon_dl1;
reg Apply_rmon_dl2;
reg Apply_rmon_pulse;
reg[2:0] Pkt_type_rmon_dl1 ;
reg[15:0] Pkt_length_rmon_dl1 ;
reg[2:0] Pkt_err_type_rmon_dl1 ;
 
always @(posedge Clk or posedge Reset)
if (Reset)
begin
Pkt_type_rmon_dl1 <=0;
Pkt_length_rmon_dl1 <=0;
Pkt_err_type_rmon_dl1 <=0;
end
else
begin
Pkt_type_rmon_dl1 <=Pkt_type_rmon ;
Pkt_length_rmon_dl1 <=Pkt_length_rmon ;
Pkt_err_type_rmon_dl1 <=Pkt_err_type_rmon ;
end
 
always @(posedge Clk or posedge Reset)
if (Reset)
begin
Apply_rmon_dl1 <=0;
Apply_rmon_dl2 <=0;
end
else
begin
Apply_rmon_dl1 <=Apply_rmon;
Apply_rmon_dl2 <=Apply_rmon_dl1;
end
always @(Apply_rmon_dl1 or Apply_rmon_dl2)
if (Apply_rmon_dl1&!Apply_rmon_dl2)
Apply_rmon_pulse =1;
else
Apply_rmon_pulse =0;
 
 
always @(posedge Clk or posedge Reset)
if (Reset)
begin
PktTypeReg <=0;
PktLengthReg <=0;
PktErrTypeReg <=0;
end
else if (Apply_rmon_pulse&&CurrentState==StateIdle)
begin
PktTypeReg <=Pkt_type_rmon_dl1 ;
PktLengthReg <=Pkt_length_rmon_dl1 ;
PktErrTypeReg <=Pkt_err_type_rmon_dl1 ;
end
 
//******************************************************************************
//State Machine
//******************************************************************************
always @(posedge Clk or posedge Reset)
if (Reset)
CurrentState <=StateIdle;
else
CurrentState <=NextState;
always @(CurrentState or Apply_rmon_pulse or Reg_next)
case (CurrentState)
StateIdle:
if (Apply_rmon_pulse)
NextState =StatePktLength;
else
NextState =StateIdle;
StatePktLength:
if (Reg_next)
NextState =StatePktNumber;
else
NextState =CurrentState;
StatePktNumber:
if (Reg_next)
NextState =StatePktType;
else
NextState =CurrentState;
StatePktType:
if (Reg_next)
NextState =StatePktRange;
else
NextState =CurrentState;
StatePktRange:
if (Reg_next)
NextState =StateIdle;
else
NextState =CurrentState;
default:
NextState =StateIdle;
endcase
//******************************************************************************
//gen output signals
//******************************************************************************
//Reg_apply
always @ (CurrentState)
if (CurrentState==StatePktLength||CurrentState==StatePktNumber||
CurrentState==StatePktType||CurrentState==StatePktRange)
Reg_apply =1;
else
Reg_apply =0;
//Reg_addr
always @ (posedge Clk or posedge Reset)
if (Reset)
Reg_addr <=0;
else case (CurrentState)
StatePktLength:
Reg_addr <=5'd00;
StatePktNumber:
Reg_addr <=5'd01;
StatePktType:
case(PktTypeReg)
3'b011:
Reg_addr <=5'd02; //broadcast
3'b001:
Reg_addr <=5'd03; //multicast
3'b100:
Reg_addr <=5'd16; //pause frame
default:
Reg_addr <=5'd04; //unicast
endcase
StatePktRange:
case(PktErrTypeReg)
3'b001:
Reg_addr <=5'd05;
3'b010:
Reg_addr <=5'd06;
3'b011:
Reg_addr <=5'd07;
3'b100:
if (PktLengthReg<64)
Reg_addr <=5'd08;
else if (PktLengthReg==64)
Reg_addr <=5'd09;
else if (PktLengthReg<128)
Reg_addr <=5'd10;
else if (PktLengthReg<256)
Reg_addr <=5'd11;
else if (PktLengthReg<512)
Reg_addr <=5'd12;
else if (PktLengthReg<1024)
Reg_addr <=5'd13;
else if (PktLengthReg<1519)
Reg_addr <=5'd14;
else
Reg_addr <=5'd15;
default:
Reg_addr <=5'd05;
endcase
default:
Reg_addr <=5'd05;
endcase
//Reg_data
always @ (CurrentState or PktLengthReg)
case (CurrentState)
StatePktLength:
Reg_data =PktLengthReg;
StatePktNumber:
Reg_data =1;
StatePktType:
Reg_data =1;
StatePktRange:
Reg_data =1;
default:
Reg_data =0;
endcase
//Reg_drop_apply
always @ (posedge Clk or posedge Reset)
if (Reset)
Reg_drop_apply <=0;
else if (CurrentState!=StateIdle&&Apply_rmon_pulse)
Reg_drop_apply <=1;
else
Reg_drop_apply <=0;
 
endmodule
/trunk/rtl/verilog/RMON/RMON_dpram.v
0,0 → 1,47
module RMON_dpram(
Reset ,
Clk ,
//port-a for Rmon
Addra,
Dina,
Douta,
Wea,
//port-b for CPU
Addrb,
Doutb
);
 
input Reset ;
input Clk ;
//port-a for Rmon
input[5:0] Addra;
input[31:0] Dina;
output[31:0] Douta;
input Wea;
//port-b for CPU
input[5:0] Addrb;
output[31:0] Doutb;
wire Clka,Clkb;
assign Clka=Clk;
assign #2 Clkb=Clk;
 
 
//******************************************************************************
//internal signals
//******************************************************************************
 
//******************************************************************************
 
duram #(32,6,"M4K") U_duram(
.data_a (Dina ),
.data_b (32'b0 ),
.wren_a (Wea ),
.wren_b (1'b0 ),
.address_a (Addra ),
.address_b (Addrb ),
.clock_a (Clka ),
.clock_b (Clkb ),
.q_a (Douta ),
.q_b (Doutb ));
 
endmodule
/trunk/rtl/verilog/RMON/RMON_ctrl.v
0,0 → 1,280
//////////////////////////////////////////////////////////////////////
//// ////
//// RMON_CTRL.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
module RMON_CTRL (
Clk ,
Reset ,
//RMON_CTRL
Reg_apply_0 ,
Reg_addr_0 ,
Reg_data_0 ,
Reg_next_0 ,
Reg_apply_1 ,
Reg_addr_1 ,
Reg_data_1 ,
Reg_next_1 ,
//dual-port ram
Addra ,
Dina ,
Douta ,
Wea ,
//CPU
CPU_rd_addr ,
CPU_rd_apply ,
CPU_rd_grant ,
CPU_rd_dout
 
);
input Clk ;
input Reset ;
//RMON_CTRL
input Reg_apply_0 ;
input[4:0] Reg_addr_0 ;
input[15:0] Reg_data_0 ;
output Reg_next_0 ;
 
input Reg_apply_1 ;
input[4:0] Reg_addr_1 ;
input[15:0] Reg_data_1 ;
output Reg_next_1 ;
 
 
//dual-port ram
//port-a for Rmon
output[5:0] Addra ;
output[31:0] Dina ;
input[31:0] Douta ;
output Wea ;
//CPU
input[5:0] CPU_rd_addr ;
input CPU_rd_apply ;
output CPU_rd_grant ;
output[31:0] CPU_rd_dout ;
 
 
 
 
//******************************************************************************
//internal signals
//******************************************************************************
 
parameter StateCPU =5'd00;
parameter StateMAC0 =5'd01;
parameter StateMAC1 =5'd02;
 
 
reg[4:0] CurrentState;
reg[4:0] NextState;
reg[4:0] CurrentState_reg;
 
reg[4:0] StepCounter;
reg[31:0] DoutaReg;
reg[5:0] Addra ;
reg[31:0] Dina;
reg Reg_next_0 ;
reg Reg_next_1 ;
reg Write;
reg Read;
reg Pipeline;
reg[31:0] CPU_rd_dout ;
reg CPU_rd_apply_reg ;
//******************************************************************************
//State Machine
//******************************************************************************
 
always @(posedge Clk or posedge Reset)
if (Reset)
CurrentState <=StateMAC0;
else
CurrentState <=NextState;
always @(posedge Clk or posedge Reset)
if (Reset)
CurrentState_reg <=StateMAC0;
else if(CurrentState!=StateCPU)
CurrentState_reg <=CurrentState;
always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg
or Reg_apply_1
or StepCounter
)
case(CurrentState)
StateMAC0:
if(!Reg_apply_0&&CPU_rd_apply_reg)
NextState =StateCPU;
else if(!Reg_apply_0)
NextState =StateMAC1;
else
NextState =CurrentState;
StateMAC1:
if(!Reg_apply_1&&CPU_rd_apply_reg)
NextState =StateCPU;
else if(!Reg_apply_1)
NextState =StateMAC0;
else
NextState =CurrentState;
StateCPU:
if (StepCounter==3)
case (CurrentState_reg)
StateMAC0 :NextState =StateMAC0 ;
StateMAC1 :NextState =StateMAC1 ;
default :NextState =StateMAC0;
endcase
else
NextState =CurrentState;
default:
NextState =StateMAC0;
endcase
 
 
always @(posedge Clk or posedge Reset)
if (Reset)
StepCounter <=0;
else if(NextState!=CurrentState)
StepCounter <=0;
else if (StepCounter!=4'hf)
StepCounter <=StepCounter + 1;
 
//******************************************************************************
//temp signals
//******************************************************************************
always @(StepCounter)
if( StepCounter==1||StepCounter==4||
StepCounter==7||StepCounter==10)
Read =1;
else
Read =0;
 
always @(StepCounter or CurrentState)
if( StepCounter==2||StepCounter==5||
StepCounter==8||StepCounter==11)
Pipeline =1;
else
Pipeline =0;
always @(StepCounter or CurrentState)
if( StepCounter==3||StepCounter==6||
StepCounter==9||StepCounter==12)
Write =1;
else
Write =0;
always @(posedge Clk or posedge Reset)
if (Reset)
DoutaReg <=0;
else if (Read)
DoutaReg <=Douta;
//******************************************************************************
//gen output signals
//******************************************************************************
//Addra
always @(*)
case(CurrentState)
StateMAC0 : Addra={1'd0 ,Reg_addr_0 };
StateMAC1 : Addra={1'd1 ,Reg_addr_1 };
StateCPU: Addra=CPU_rd_addr;
default: Addra=0;
endcase
//Dina
always @(posedge Clk or posedge Reset)
if (Reset)
Dina <=0;
else
case(CurrentState)
StateMAC0 : Dina<=Douta+Reg_data_0 ;
StateMAC1 : Dina<=Douta+Reg_data_1 ;
StateCPU: Dina<=0;
default: Dina<=0;
endcase
assign Wea =Write;
//Reg_next
always @(CurrentState or Pipeline)
if(CurrentState==StateMAC0)
Reg_next_0 =Pipeline;
else
Reg_next_0 =0;
always @(CurrentState or Pipeline)
if(CurrentState==StateMAC1)
Reg_next_1 =Pipeline;
else
Reg_next_1 =0;
 
 
//CPU_rd_grant
reg CPU_rd_apply_dl1;
reg CPU_rd_apply_dl2;
//rising edge
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
CPU_rd_apply_dl1 <=0;
CPU_rd_apply_dl2 <=0;
end
else
begin
CPU_rd_apply_dl1 <=CPU_rd_apply;
CPU_rd_apply_dl2 <=CPU_rd_apply_dl1;
end
 
always @ (posedge Clk or posedge Reset)
if (Reset)
CPU_rd_apply_reg <=0;
else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)
CPU_rd_apply_reg <=1;
else if (CurrentState==StateCPU&&Write)
CPU_rd_apply_reg <=0;
 
assign CPU_rd_grant =!CPU_rd_apply_reg;
 
always @ (posedge Clk or posedge Reset)
if (Reset)
CPU_rd_dout <=0;
else if (Pipeline&&CurrentState==StateCPU)
CPU_rd_dout <=Douta;
 
endmodule
/trunk/rtl/verilog/miim/eth_shiftreg.v
0,0 → 1,158
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_shiftreg.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/04/27 15:58:47 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.5 2002/08/14 18:16:59 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.4 2002/03/02 21:06:01 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
 
`timescale 1ns/10ps
 
 
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
LatchByte, ShiftedBit, Prsd, LinkFail);
 
 
parameter Tp=1;
 
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
input Mdi; // MII input data
input [4:0] Fiad; // PHY address
input [4:0] Rgad; // Register address (within the selected PHY)
input [15:0]CtrlData; // Control data (data to be written to the PHY)
input WriteOp; // The current operation is a PHY register write operation
input [3:0] ByteSelect; // Byte select
input [1:0] LatchByte; // Byte select for latching (read operation)
 
output ShiftedBit; // Bit shifted out of the shift register
output[15:0]Prsd; // Read Status Data (data read from the PHY)
output LinkFail; // Link Integrity Signal
 
reg [7:0] ShiftReg; // Shift register for shifting the data in and out
reg [15:0]Prsd;
reg LinkFail;
 
 
 
 
// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
ShiftReg[7:0] <= #Tp 8'h0;
Prsd[15:0] <= #Tp 16'h0;
LinkFail <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
if(|ByteSelect)
begin
case (ByteSelect[3:0])
4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];
4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];
default : ShiftReg[7:0] <= #Tp 8'h0;
endcase
end
else
begin
ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(LatchByte[0])
begin
Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(Rgad == 5'h01)
LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
end
else
begin
if(LatchByte[1])
Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
end
end
end
end
end
 
 
assign ShiftedBit = ShiftReg[7];
 
 
endmodule
/trunk/rtl/verilog/miim/eth_outputcontrol.v
0,0 → 1,156
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_outputcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/04/27 15:58:46 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.4 2002/07/09 20:11:59 mohor
// Comment removed.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
 
`timescale 1ns/10ps
 
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
 
parameter Tp = 1;
 
input Clk; // Host Clock
input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
input NoPre; // No Preamble (no 32-bit preamble)
input InProgress; // Operation in progress
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
input [6:0] BitCounter; // Bit Counter
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
 
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
 
wire SerialEn;
 
reg MdoEn_2d;
reg MdoEn_d;
reg MdoEn;
 
reg Mdo_2d;
reg Mdo_d;
reg Mdo; // MII Management Data Output
 
 
 
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
 
 
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
MdoEn_2d <= #Tp 1'b0;
MdoEn_d <= #Tp 1'b0;
MdoEn <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
MdoEn_d <= #Tp MdoEn_2d;
MdoEn <= #Tp MdoEn_d;
end
end
end
 
 
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
Mdo_2d <= #Tp 1'b0;
Mdo_d <= #Tp 1'b0;
Mdo <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
Mdo_d <= #Tp ShiftedBit | Mdo_2d;
Mdo <= #Tp Mdo_d;
end
end
end
 
 
 
endmodule
/trunk/rtl/verilog/miim/eth_clockgen.v
0,0 → 1,137
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_clockgen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/04/27 15:58:45 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:55 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
 
`timescale 1ns/10ps
 
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
 
parameter Tp=1;
 
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
 
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
 
reg Mdc;
reg [7:0] Counter;
 
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
 
 
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period
 
 
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= #Tp 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= #Tp CounterPreset[7:0];
end
else
Counter[7:0] <= #Tp Counter - 8'h1;
end
end
 
 
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= #Tp 1'b0;
else
begin
if(CountEq0)
Mdc <= #Tp ~Mdc;
end
end
 
 
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
 
endmodule
 
 
/trunk/rtl/verilog/miim/timescale.v
0,0 → 1,56
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 11:36:31 mohor
// Log file added.
//
//
//
 
`timescale 1ns / 1ns
/trunk/rtl/verilog/MAC_rx.v
0,0 → 1,201
//////////////////////////////////////////////////////////////////////
//// ////
//// MAC_rx.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
module MAC_rx (
input Reset ,
input Clk_user,
input Clk ,
//RMII interface
input MCrs_dv ,
input [7:0] MRxD ,
input MRxErr ,
//flow_control signals
output [15:0] pause_quanta ,
output pause_quanta_val ,
//user interface
output Rx_mac_ra ,
input Rx_mac_rd ,
output[31:0] Rx_mac_data ,
output[1:0] Rx_mac_BE ,
output Rx_mac_pa ,
output Rx_mac_sop ,
output Rx_mac_eop ,
//CPU
input MAC_rx_add_chk_en ,
input [7:0] MAC_add_prom_data ,
input [2:0] MAC_add_prom_add ,
input MAC_add_prom_wr ,
input broadcast_filter_en ,
input [15:0] broadcast_MAX ,
input RX_APPEND_CRC,
input CRC_chk_en ,
input [5:0] RX_IFG_SET ,
input [15:0] RX_MAX_LENGTH ,// 1518
input [6:0] RX_MIN_LENGTH ,// 64
//RMON interface
output [15:0] Rx_pkt_length_rmon ,
output Rx_apply_rmon ,
output [2:0] Rx_pkt_err_type_rmon ,
output [2:0] Rx_pkt_type_rmon
);
//******************************************************************************
//internal signals
//******************************************************************************
//CRC_chk interface
wire CRC_en ;
wire CRC_init;
wire CRC_err ;
//MAC_rx_add_chk interface
wire MAC_add_en ;
wire MAC_rx_add_chk_err ;
//broadcast_filter
wire broadcast_ptr ;
wire broadcast_drop ;
//flow_control signals
wire [15:0] pause_quanta ;
wire pause_quanta_val ;
//MAC_rx_ctrl interface
wire [7:0] Fifo_data ;
wire Fifo_data_en ;
wire Fifo_full ;
wire Fifo_data_err ;
wire Fifo_data_end ;
//******************************************************************************
//instantiation
//******************************************************************************
 
 
MAC_rx_ctrl U_MAC_rx_ctrl(
.Reset (Reset ),
.Clk (Clk ),
//RMII interface ( //RMII interface ),
.MCrs_dv (MCrs_dv ),
.MRxD (MRxD ),
.MRxErr (MRxErr ),
//CRC_chk interface (//CRC_chk interface ),
.CRC_en (CRC_en ),
.CRC_init (CRC_init ),
.CRC_err (CRC_err ),
//MAC_rx_add_chk interface (//MAC_rx_add_chk interface),
.MAC_add_en (MAC_add_en ),
.MAC_rx_add_chk_err (MAC_rx_add_chk_err ),
//broadcast_filter (//broadcast_filter ),
.broadcast_ptr (broadcast_ptr ),
.broadcast_drop (broadcast_drop ),
//flow_control signals (//flow_control signals ),
.pause_quanta (pause_quanta ),
.pause_quanta_val (pause_quanta_val ),
//MAC_rx_FF interface (//MAC_rx_FF interface ),
.Fifo_data (Fifo_data ),
.Fifo_data_en (Fifo_data_en ),
.Fifo_data_err (Fifo_data_err ),
.Fifo_data_end (Fifo_data_end ),
.Fifo_full (Fifo_full ),
//RMON interface (//RMON interface ),
.Rx_pkt_type_rmon (Rx_pkt_type_rmon ),
.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),
.Rx_apply_rmon (Rx_apply_rmon ),
.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
//CPU (//CPU ),
.RX_IFG_SET (RX_IFG_SET ),
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
.RX_MIN_LENGTH (RX_MIN_LENGTH )
);
 
MAC_rx_FF U_MAC_rx_FF (
.Reset (Reset ),
.Clk_MAC (Clk ),
.Clk_SYS (Clk_user ),
//MAC_rx_ctrl interface (//MAC_rx_ctrl interface ),
.Fifo_data (Fifo_data ),
.Fifo_data_en (Fifo_data_en ),
.Fifo_full (Fifo_full ),
.Fifo_data_err (Fifo_data_err ),
.Fifo_data_end (Fifo_data_end ),
//CPU (//CPU ),
.RX_APPEND_CRC (RX_APPEND_CRC ),
//user interface (//user interface ),
.Rx_mac_ra (Rx_mac_ra ),
.Rx_mac_rd (Rx_mac_rd ),
.Rx_mac_data (Rx_mac_data ),
.Rx_mac_BE (Rx_mac_BE ),
.Rx_mac_sop (Rx_mac_sop ),
.Rx_mac_pa (Rx_mac_pa ),
.Rx_mac_eop (Rx_mac_eop )
);
 
Broadcast_filter U_Broadcast_filter(
.Reset (Reset ),
.Clk (Clk ),
//MAC_rx_ctrl (//MAC_rx_ctrl ),
.broadcast_ptr (broadcast_ptr ),
.broadcast_drop (broadcast_drop ),
//FromCPU (//FromCPU ),
.broadcast_filter_en (broadcast_filter_en ),
.broadcast_MAX (broadcast_MAX )
);
 
CRC_chk U_CRC_chk(
.Reset (Reset ),
.Clk (Clk ),
.CRC_data (Fifo_data ),
.CRC_init (CRC_init ),
.CRC_en (CRC_en ),
//From CPU (//From CPU ),
.CRC_chk_en (CRC_chk_en ),
.CRC_err (CRC_err )
);
 
MAC_rx_add_chk U_MAC_rx_add_chk(
.Reset (Reset ),
.Clk (Clk ),
.Init (CRC_init ),
.data (Fifo_data ),
.MAC_add_en (MAC_add_en ),
.MAC_rx_add_chk_err (MAC_rx_add_chk_err ),
//From CPU (//From CPU ),
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
.MAC_add_prom_data (MAC_add_prom_data ),
.MAC_add_prom_add (MAC_add_prom_add ),
.MAC_add_prom_wr (MAC_add_prom_wr )
);
 
endmodule
/trunk/rtl/verilog/Phy_int.v
0,0 → 1,212
//////////////////////////////////////////////////////////////////////
//// ////
//// Phy_int.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
module Phy_int (
Reset ,
MAC_rx_clk ,
MAC_tx_clk ,
//Rx interface ,
MCrs_dv ,
MRxD ,
MRxErr ,
//Tx interface ,
MTxD ,
MTxEn ,
MCRS ,
//Phy interface ,
Tx_er ,
Tx_en ,
Txd ,
Rx_er ,
Rx_dv ,
Rxd ,
Crs ,
Col ,
//host interface ,
Line_loop_en ,
Speed
 
);
input Reset ;
input MAC_rx_clk ;
input MAC_tx_clk ;
//Rx interface
output MCrs_dv ;
output [7:0] MRxD ;
output MRxErr ;
//Tx interface
input [7:0] MTxD ;
input MTxEn ;
output MCRS ;
//Phy interface
output Tx_er ;
output Tx_en ;
output [7:0] Txd ;
input Rx_er ;
input Rx_dv ;
input [7:0] Rxd ;
input Crs ;
input Col ;
//host interface
input Line_loop_en ;
input [2:0] Speed ;
//******************************************************************************
//internal signals
//******************************************************************************
reg [7:0] MTxD_dl1 ;
reg MTxEn_dl1 ;
reg Tx_odd_data_ptr ;
reg Rx_odd_data_ptr ;
reg Tx_en ;
reg [7:0] Txd ;
reg MCrs_dv ;
reg [7:0] MRxD ;
reg Rx_er_dl1 ;
reg Rx_dv_dl1 ;
reg [7:0] Rxd_dl1 ;
reg [7:0] Rxd_dl2 ;
reg Crs_dl1 ;
reg Col_dl1 ;
//******************************************************************************
//Tx control
//******************************************************************************
//reg boundery signals
always @ (posedge MAC_tx_clk or posedge Reset)
if (Reset)
begin
MTxD_dl1 <=0;
MTxEn_dl1 <=0;
end
else
begin
MTxD_dl1 <=MTxD ;
MTxEn_dl1 <=MTxEn ;
end
always @ (posedge MAC_tx_clk or posedge Reset)
if (Reset)
Tx_odd_data_ptr <=0;
else if (!MTxD_dl1)
Tx_odd_data_ptr <=0;
else
Tx_odd_data_ptr <=!Tx_odd_data_ptr;
 
always @ (posedge MAC_tx_clk or posedge Reset)
if (Reset)
Txd <=0;
else if(Speed[2]&&MTxEn_dl1)
Txd <=MTxD_dl1;
else if(MTxEn_dl1&&!Tx_odd_data_ptr)
Txd <={4'b0,MTxD_dl1[3:0]};
else if(MTxEn_dl1&&Tx_odd_data_ptr)
Txd <={4'b0,MTxD_dl1[7:4]};
else
Txd <=0;
 
always @ (posedge MAC_tx_clk or posedge Reset)
if (Reset)
Tx_en <=0;
else if(MTxEn_dl1)
Tx_en <=MTxEn_dl1;
 
assign Tx_er=0;
 
//******************************************************************************
//Rx control
//******************************************************************************
//reg boundery signals
always @ (posedge MAC_rx_clk or posedge Reset)
if (Reset)
begin
Rx_er_dl1 <=0;
Rx_dv_dl1 <=0;
Rxd_dl1 <=0;
Rxd_dl2 <=0;
Crs_dl1 <=0;
Col_dl1 <=0;
end
else
begin
Rx_er_dl1 <=Rx_er ;
Rx_dv_dl1 <=Rx_dv ;
Rxd_dl1 <=Rxd ;
Rxd_dl2 <=Rxd_dl1 ;
Crs_dl1 <=Crs ;
Col_dl1 <=Col ;
end
 
assign MRxErr =Rx_er_dl1 ;
assign MCRS =Crs_dl1 ;
 
always @ (posedge MAC_rx_clk or posedge Reset)
if (Reset)
MCrs_dv <=0;
else if(Line_loop_en)
MCrs_dv <=Tx_en;
else if(Rx_dv_dl1)
MCrs_dv <=1;
else
MCrs_dv <=0;
 
always @ (posedge MAC_rx_clk or posedge Reset)
if (Reset)
Rx_odd_data_ptr <=0;
else if (!Rx_dv_dl1)
Rx_odd_data_ptr <=0;
else
Rx_odd_data_ptr <=!Rx_odd_data_ptr;
always @ (posedge MAC_rx_clk or posedge Reset)
if (Reset)
MRxD <=0;
else if(Line_loop_en)
MRxD <=Txd;
else if(Speed[2]&&Rx_dv_dl1)
MRxD <=Rxd_dl1;
else if(Rx_dv_dl1&&Rx_odd_data_ptr)
MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]};
 
endmodule

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