URL
https://opencores.org/ocsvn/ethernet_tri_mode/ethernet_tri_mode/trunk
Subversion Repositories ethernet_tri_mode
Compare Revisions
- This comparison shows the changes necessary to convert path
/ethernet_tri_mode/tags/release-1-0/syn
- from Rev 15 to Rev 33
- ↔ Reverse comparison
Rev 15 → Rev 33
/syn.prj
0,0 → 1,86
#-- Synplicity, Inc. |
#-- Version Synplify 8.1 |
#-- Project file D:\root\home\ethernet_tri_mode\syn\syn.prj |
#-- Written on Thu Jan 19 20:25:55 2006 |
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#add_file options |
add_file -verilog "../rtl/verilog/header.v" |
add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v" |
add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v" |
add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v" |
add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v" |
add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v" |
add_file -verilog "../rtl/verilog/MAC_tx/flow_ctrl.v" |
add_file -verilog "../rtl/verilog/MAC_rx/CRC_chk.v" |
add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_add_chk.v" |
add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_FF.v" |
add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v" |
add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v" |
add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v" |
add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v" |
add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v" |
add_file -verilog "../rtl/verilog/TECH/duram.v" |
add_file -verilog "../rtl/verilog/RMON.v" |
add_file -verilog "../rtl/verilog/MAC_rx.v" |
add_file -verilog "../rtl/verilog/MAC_tx.v" |
add_file -verilog "../rtl/verilog/miim/eth_clockgen.v" |
add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v" |
add_file -verilog "../rtl/verilog/miim/eth_shiftreg.v" |
add_file -verilog "../rtl/verilog/miim/timescale.v" |
add_file -verilog "../rtl/verilog/TECH/CLK_SWITCH.v" |
add_file -verilog "../rtl/verilog/TECH/CLK_DIV2.v" |
add_file -verilog "../rtl/verilog/eth_miim.v" |
add_file -verilog "../rtl/verilog/Clk_ctrl.v" |
add_file -verilog "../rtl/verilog/Phy_int.v" |
add_file -verilog "../rtl/verilog/Reg_int.v" |
add_file -verilog "../rtl/verilog/MAC_top.v" |
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#implementation: "syn" |
impl -add syn |
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#device options |
set_option -technology STRATIX |
set_option -part EP1S10 |
set_option -package FC780 |
set_option -speed_grade -5 |
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#compilation/mapping options |
set_option -default_enum_encoding onehot |
set_option -symbolic_fsm_compiler 0 |
set_option -resource_sharing 1 |
set_option -use_fsm_explorer 0 |
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#map options |
set_option -frequency auto |
set_option -run_prop_extract 0 |
set_option -fanout_limit 500 |
set_option -disable_io_insertion 0 |
set_option -pipe 1 |
set_option -update_models_cp 0 |
set_option -retiming 0 |
set_option -verification_mode 0 |
set_option -fixgatedclocks 0 |
set_option -no_sequential_opt 0 |
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#simulation options |
set_option -write_verilog 1 |
set_option -write_vhdl 0 |
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#automatic place and route (vendor) options |
set_option -write_apr_constraint 0 |
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#set result format/file last |
project -result_file "./MAC_top.vqm" |
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# |
#implementation attributes |
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set_option -vlog_std v2001 |
set_option -project_relative_includes 1 |
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#par_1 attributes |
set_option -job par_1 -add par |
set_option -job par_1 -option run_backannotation 0 |
impl -active "syn" |