URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
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- from Rev 221 to Rev 220
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Rev 221 → Rev 220
/trunk/rtl/verilog/eth_wishbone.v
41,11 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.39 2002/10/11 15:35:20 mohor |
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, |
// TxDone and TxRetry are generated after the current WISHBONE access is |
// finished. |
// |
// Revision 1.38 2002/10/10 16:29:30 mohor |
// BIST added. |
// |
363,11 → 358,8
reg TxAbort_wb_q; |
reg TxRetry_wb_q; |
reg TxRetryPacket; |
reg TxRetryPacket_NotCleared; |
reg TxDonePacket; |
reg TxDonePacket_NotCleared; |
reg TxDonePulse_q; |
reg TxAbortPacket; |
reg TxAbortPacket_NotCleared; |
reg RxBDReady; |
reg RxReady; |
reg TxBDReady; |
630,7 → 622,7
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// Reading the Tx buffer descriptor |
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady; |
assign StartTxBDRead = (TxRetry_wb | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady; |
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always @ (posedge WB_CLK_I or posedge Reset) |
begin |
663,7 → 655,7
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// Writing status back to the Tx buffer descriptor |
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite; |
assign TxStatusWrite = (TxDone_wb | TxAbort_wb) & TxEn & TxEn_q & ~BlockingTxStatusWrite; |
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887,10 → 879,7
ReadTxDataFromMemory <=#Tp 1'b1; |
end |
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reg BlockingLastReadOn_Abort_Retry; |
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wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry; |
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wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory; |
wire [31:0] TxData_wb; |
wire ReadTxDataFromFifo_wb; |
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899,29 → 888,15
if(Reset) |
BlockReadTxDataFromMemory <=#Tp 1'b0; |
else |
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket))) |
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX) |
BlockReadTxDataFromMemory <=#Tp 1'b1; |
else |
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket) |
if(ReadTxDataFromFifo_wb | TxDonePulse_q | TxAbortPacket | TxRetryPacket) |
BlockReadTxDataFromMemory <=#Tp 1'b0; |
end |
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always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingLastReadOn_Abort_Retry <=#Tp 1'b0; |
else |
if(TxAbortPacket | TxRetryPacket) |
BlockingLastReadOn_Abort_Retry <=#Tp 1'b0; |
else |
if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady) |
BlockingLastReadOn_Abort_Retry <=#Tp 1'b1; |
end |
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i; |
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt; |
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt; |
1036,7 → 1011,6
MasterWbRX <=#Tp 1'b0; |
m_wb_cyc_o <=#Tp 1'b0; |
m_wb_stb_o <=#Tp 1'b0; |
cyc_cleared<=#Tp 1'b0; |
IncrTxPointer<=#Tp 1'b0; |
end |
default: // Don't touch |
1154,7 → 1128,7
if(Reset) |
TxEndFrm_wb <=#Tp 1'b0; |
else |
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData) |
if(TxLengthLt4 & TxBufferAlmostEmpty & TxUsedData) |
TxEndFrm_wb <=#Tp 1'b1; |
else |
if(TxRetryPulse | TxDonePulse | TxAbortPulse) |
1280,6 → 1254,7
TxDone_wb_q <=#Tp 1'b0; |
TxAbort_wb_q <=#Tp 1'b0; |
TxRetry_wb_q <=#Tp 1'b0; |
TxDonePulse_q <=#Tp 1'b0; |
end |
else |
begin |
1286,6 → 1261,7
TxDone_wb_q <=#Tp TxDone_wb; |
TxAbort_wb_q <=#Tp TxAbort_wb; |
TxRetry_wb_q <=#Tp TxRetry_wb; |
TxDonePulse_q <=#Tp TxDonePulse; |
end |
end |
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1306,18 → 1282,6
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacket_NotCleared <=#Tp 1'b0; |
else |
if(TxAbort_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX))) |
TxAbortPacket_NotCleared <=#Tp 1'b1; |
else |
TxAbortPacket_NotCleared <=#Tp 1'b0; |
end |
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always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacketBlocked <=#Tp 1'b0; |
else |
if(TxAbortPacket) |
1344,18 → 1308,6
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacket_NotCleared <=#Tp 1'b0; |
else |
if(TxRetry_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX))) |
TxRetryPacket_NotCleared <=#Tp 1'b1; |
else |
TxRetryPacket_NotCleared <=#Tp 1'b0; |
end |
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always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacketBlocked <=#Tp 1'b0; |
else |
if(TxRetryPacket) |
1366,44 → 1318,6
end |
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reg TxDonePacketBlocked; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacket <=#Tp 1'b0; |
else |
if(TxDone_wb & (!TxDonePacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX))) |
TxDonePacket <=#Tp 1'b1; |
else |
TxDonePacket <=#Tp 1'b0; |
end |
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always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacket_NotCleared <=#Tp 1'b0; |
else |
if(TxDone_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX))) |
TxDonePacket_NotCleared <=#Tp 1'b1; |
else |
TxDonePacket_NotCleared <=#Tp 1'b0; |
end |
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always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacketBlocked <=#Tp 1'b0; |
else |
if(TxDonePacket) |
TxDonePacketBlocked <=#Tp 1'b1; |
else |
if(!TxDone_wb & TxDone_wb_q) |
TxDonePacketBlocked <=#Tp 1'b0; |
end |
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// Sinchronizing and evaluating tx data |
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I; |
assign SetGotData = (TxStartFrm_wb); |
2095,6 → 2009,7
assign WriteRxDataToMemory = ~RxBufferEmpty; |
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// Generation of the end-of-frame signal |
always @ (posedge MRxClk or posedge Reset) |
begin |