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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 227 to Rev 226
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  •

Rev 227 → Rev 226

/trunk/rtl/verilog/eth_wishbone.v
41,9 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.41 2002/10/18 15:42:09 tadejm
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
//
// Revision 1.40 2002/10/14 16:07:02 mohor
// TxStatus is written after last access to the TX fifo is finished (in case of abort
// or retry). TxDone is fixed.
236,13 → 233,7
 
// Bist
`ifdef ETH_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
, trst, SO, SI, shift_DR, capture_DR, extest, tck
`endif
 
338,11 → 329,10
 
// Bist
`ifdef ETH_BIST
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input trst;
input shift_DR, capture_DR, tck, extest;
input SI;
output SO;
`endif
 
reg TxB_IRQ;
495,12 → 485,7
eth_spram_256x32 bd_ram (
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
`ifdef ETH_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
, .trst(trst), .SO(SO), .SI(SI), .shift_DR(shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)
`endif
);
 
/trunk/rtl/verilog/eth_top.v
41,9 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.35 2002/10/11 13:36:58 mohor
// Typo error fixed. (When using Bist)
//
// Revision 1.34 2002/10/10 16:49:50 mohor
// Signals for WISHBONE B3 compliant interface added.
//
212,13 → 209,7
 
// Bist
`ifdef ETH_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
, trst, SO, SI, shift_DR, capture_DR, extest, tck
`endif
 
);
284,11 → 275,10
 
// Bist
`ifdef ETH_BIST
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input trst;
input shift_DR, capture_DR, tck, extest;
input SI;
output SO;
`endif
 
wire [7:0] r_ClkDiv;
767,11 → 757,9
`ifdef ETH_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.trst(trst), .SO(SO), .SI(SI),
.shift_DR(shift_DR), .capture_DR(capture_DR), .extest(extest),
.tck(tck)
`endif
);
 
/trunk/rtl/verilog/eth_spram_256x32.v
41,9 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.2 2002/09/23 18:24:31 mohor
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
//
61,13 → 58,7
clk, rst, ce, we, oe, addr, di, do
 
`ifdef ETH_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
,trst, SO, SI, shift_DR, capture_DR, extest, tck
`endif
 
 
88,11 → 79,10
 
 
`ifdef ETH_BIST
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
input trst;
input shift_DR, capture_DR, tck, extest;
input SI;
output SO;
`endif
 
`ifdef ETH_XILINX_RAMB4
137,12 → 127,16
 
`ifdef ETH_BIST
,
// reset
.trst (trst),
 
// debug chain signals
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
.SO (SO),
.SI (SI),
.shift_DR (shift_DR),
.capture_DR(capture_DR),
.extest (extest),
.tck (tck)
`endif
);
 
/trunk/bench/verilog/tb_ethernet.v
42,9 → 42,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.17 2002/10/18 13:58:22 tadejm
// Some code changed due to bug fixes.
//
// Revision 1.16 2002/10/09 13:16:51 tadejm
// Just back-up; not completed testbench and some testcases are not
// wotking properly yet.
169,16 → 166,6
.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
.int_o(wb_int)
 
// Bist
`ifdef ETH_BIST
,
.scanb_rst (1'b0),
.scanb_clk (1'b0),
.scanb_si (1'b0),
.scanb_so (),
.scanb_en (1'b0)
`endif
);
 
 
/trunk/bench/verilog/tb_ethernet_with_cop.v
41,9 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/11 13:29:28 mohor
// Bist signals added.
//
// Revision 1.1 2002/09/18 16:40:40 mohor
// Simple testbench that includes eth_cop, eth_host and eth_memory modules.
// This testbench is used for testing the whole environment. Use tb_ethernet
190,12 → 187,7
 
// Bist
`ifdef ETH_BIST
,
.scanb_rst (1'b0),
.scanb_clk (1'b0),
.scanb_si (1'b0),
.scanb_so (),
.scanb_en (1'b0)
, .trst(1'b0), .SO(), .SI(1'b0), .shift_DR(1'b0), .capture_DR(1'b0), .extest(1'b0), .tck(1'b0)
`endif
);

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