URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 257 to Rev 256
- ↔ Reverse comparison
Rev 257 → Rev 256
/trunk/rtl/verilog/eth_transmitcontrol.v
41,11 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/11/19 17:37:32 mohor |
// When control frame (PAUSE) was sent, status was written in the |
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed. |
// Only TXC interrupt is set. |
// |
// Revision 1.4 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
131,8 → 126,6
wire ResetByteCnt; |
wire IncrementByteCnt; |
wire ControlEnd; |
wire IncrementByteCntBy2; |
wire EnableCnt; |
|
|
// A command for Sending the control frame is active (latched) |
227,7 → 220,7
if(TxCtrlStartFrm) |
BlockTxDone <= #Tp 1'b1; |
else |
if(TxStartFrmIn) |
if(TxDoneIn) |
BlockTxDone <= #Tp 1'b0; |
end |
|
258,9 → 251,8
|
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn)); |
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd); |
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time |
|
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0])); |
|
// Byte counter |
always @ (posedge MTxClk or posedge TxReset) |
begin |
270,10 → 262,7
if(ResetByteCnt) |
ByteCnt <= #Tp 6'h0; |
else |
if(IncrementByteCntBy2 & EnableCnt) |
ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2; |
else |
if(IncrementByteCnt & EnableCnt) |
if(IncrementByteCnt & (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))) |
ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1; |
end |
|