URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 260 to Rev 261
- ↔ Reverse comparison
Rev 260 → Rev 261
/trunk/rtl/verilog/eth_rxethmac.v
43,6 → 43,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2002/11/19 17:35:35 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
// |
// Revision 1.8 2002/02/16 07:15:27 mohor |
// Testbench fixed, code simplified, unused signals removed. |
// |
92,7 → 96,7
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn, |
RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2, |
ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData, |
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss |
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK |
); |
|
parameter Tp = 1; |
113,6 → 117,9
input r_Pro; // promiscuous enable |
input [31:0] r_HASH0; // lower 4 bytes Hash Table |
input [31:0] r_HASH1; // upper 4 bytes Hash Table |
input PassAll; |
input ControlFrmAddressOK; |
|
output [7:0] RxData; |
output RxValid; |
output RxStartFrm; |
196,14 → 203,15
// Rx Address Check |
|
eth_rxaddrcheck rxaddrcheck1 |
(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData), |
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro), |
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2), |
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), |
(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData), |
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro), |
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2), |
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), |
.HASH0(r_HASH0), .HASH1(r_HASH1), |
.CrcHash(CrcHash[5:0]), .CrcHashGood(CrcHashGood),.StateData(StateData), |
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort), |
.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss) |
.CrcHash(CrcHash[5:0]), .CrcHashGood(CrcHashGood), .StateData(StateData), |
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort), |
.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll), |
.ControlFrmAddressOK(ControlFrmAddressOK) |
); |
|
|
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.45 2002/11/19 17:33:34 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
// |
// Revision 1.44 2002/11/13 22:21:40 tadejm |
// RxError is not generated when small frame reception is enabled and small |
// frames are received. |
232,7 → 236,7
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, |
|
// Register |
r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, |
r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, |
|
// Interrupts |
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, |
240,6 → 244,7
// Rx Status |
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble, |
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss, |
ReceivedPauseFrm, |
|
// Tx Status |
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost |
304,6 → 309,8
input LoadRxStatus; // Rx status was loaded |
input ReceivedPacketGood;// Received packet's length and CRC are good |
input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD |
input r_RxFlow; |
input ReceivedPauseFrm; |
|
// Tx Status signals |
input [3:0] RetryCntLatched; // Latched Retry Counter |
468,8 → 475,8
|
reg WB_ACK_O; |
|
wire [7:0] RxStatusIn; |
reg [7:0] RxStatusInLatched; |
wire [8:0] RxStatusIn; |
reg [8:0] RxStatusInLatched; |
|
reg WbEn, WbEn_q; |
reg RxEn, RxEn_q; |
1348,7 → 1355,7
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost}; |
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 5'h0, RxStatusInLatched}; |
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched}; |
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched}; |
|
|
2364,7 → 2371,7
end |
|
|
assign RxStatusIn = {AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision}; |
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision}; |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
2435,7 → 2442,7
RxB_IRQ <=#Tp 1'b0; |
else |
if(RxStatusWrite & RxIRQEn) |
RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError; |
RxB_IRQ <=#Tp ReceivedPacketGood & (~RxError) & (~r_RxFlow); // When r_RxFlow is set, RXC irq is set. |
else |
RxB_IRQ <=#Tp 1'b0; |
end |
/trunk/rtl/verilog/eth_rxaddrcheck.v
41,6 → 41,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2002/11/19 17:34:52 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
// |
// Revision 1.7 2002/09/04 18:41:06 mohor |
// Bug when last byte of destination address was not checked fixed. |
// |
67,7 → 71,8
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5, |
ByteCntEq6, ByteCntEq7, HASH0, HASH1, |
CrcHash, CrcHashGood, StateData, RxEndFrm, |
Multicast, MAC, RxAbort, AddressMiss |
Multicast, MAC, RxAbort, AddressMiss, PassAll, |
ControlFrmAddressOK |
); |
|
parameter Tp = 1; |
92,6 → 97,8
input [47:0] MAC; |
input [1:0] StateData; |
input RxEndFrm; |
input PassAll; |
input ControlFrmAddressOK; |
|
output RxAbort; |
output AddressMiss; |
137,7 → 144,7
if(Reset) |
AddressMiss <= #Tp 1'b0; |
else if(ByteCntEq7 & RxCheckEn) |
AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK)); |
AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK))); |
end |
|
|
/trunk/rtl/verilog/eth_receivecontrol.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
71,9 → 74,10
|
|
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm, |
RxEndFrm, RxFlow, ReceiveEnd, MAC, PassAll, DlyCrcEn, TxDoneIn, |
RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn, |
TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood, |
TxUsedDataOutDetected, Pause, ReceivedPauseFrm |
TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK, |
LoadRxStatus, SetPauseTimer |
); |
|
parameter Tp = 1; |
90,7 → 94,6
input RxFlow; |
input ReceiveEnd; |
input [47:0]MAC; |
input PassAll; |
input DlyCrcEn; |
input TxDoneIn; |
input TxAbortIn; |
98,9 → 101,12
input ReceivedLengthOK; |
input ReceivedPacketGood; |
input TxUsedDataOutDetected; |
input LoadRxStatus; |
|
output Pause; |
output ReceivedPauseFrm; |
output AddressOK; |
output SetPauseTimer; |
|
reg Pause; |
reg AddressOK; // Multicast or unicast address detected |
136,7 → 142,6
wire ByteCntEq16; // ByteCnt = 16 |
wire ByteCntEq17; // ByteCnt = 17 |
wire ByteCntEq18; // ByteCnt = 18 |
wire SetPauseTimer; // |
wire DecrementPauseTimer; // |
wire PauseTimerEq0; // |
wire ResetSlotTimer; // |
271,7 → 276,7
if(RxReset) |
LatchedTimerValue[15:0] <= #Tp 16'h0; |
else |
if(~PassAll & DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18) |
if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18) |
LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0]; |
else |
if(ReceiveEnd) |
419,7 → 424,7
if(ByteCntEq16 & TypeLengthOK & OpCodeOK) |
ReceivedPauseFrm <=#Tp 1'b1; |
else |
if(ReceiveEnd) |
if(RxStartFrm) |
ReceivedPauseFrm <=#Tp 1'b0; |
end |
|
/trunk/rtl/verilog/eth_maccontrol.v
41,6 → 41,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/11/21 00:14:39 mohor |
// TxDone and TxAbort changed so they're not propagated to the wishbone |
// module when control frame is transmitted. |
// |
// Revision 1.4 2002/11/19 17:37:32 mohor |
// When control frame (PAUSE) was sent, status was written in the |
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed. |
79,10 → 83,10
|
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn, |
TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd, |
ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, PassAll, DlyCrcEn, TxPauseTV, |
ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV, |
MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut, |
TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm, |
ReceivedPauseFrm |
ReceivedPauseFrm, ControlFrmAddressOK, LoadRxStatus, SetPauseTimer |
); |
|
|
111,10 → 115,10
input ReceivedLengthOK; // Length of the received packet is OK |
input TxFlow; // Tx flow control (from registers) |
input RxFlow; // Rx flow control (from registers) |
input PassAll; // Pass All received frames (from registers) |
input DlyCrcEn; // Delayed CRC enabled (from registers) |
input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers) |
input [47:0] MAC; // MAC address (from registers) |
input LoadRxStatus; |
|
output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC) |
output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC) |
127,6 → 131,8
output WillSendControlFrame; |
output TxCtrlEndFrm; |
output ReceivedPauseFrm; |
output ControlFrmAddressOK; |
output SetPauseTimer; |
|
reg TxUsedDataOutDetected; |
reg TxAbortInLatched; |
238,10 → 244,11
( |
.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData), |
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow), |
.ReceiveEnd(ReceiveEnd), .MAC(MAC), .PassAll(PassAll), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn), |
.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn), |
.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK), |
.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected), |
.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm) |
.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK), |
.LoadRxStatus(LoadRxStatus), .SetPauseTimer(SetPauseTimer) |
); |
|
|
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.42 2002/11/21 00:09:19 mohor |
// TPauseRq synchronized to tx_clk. |
// |
// Revision 1.41 2002/11/19 18:13:49 mohor |
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. |
// |
490,7 → 493,7
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq), |
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm), |
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i), |
.ReceivedPauseFrm(ReceivedPauseFrm) |
.SetPauseTimer(SetPauseTimer) |
|
); |
|
531,7 → 534,7
.RxData(RxData), .RxValid(RxValid), |
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), |
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), |
.PassAll(r_PassAll), .TxFlow(r_TxFlow), |
.TxFlow(r_TxFlow), |
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn), |
.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad), |
.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn), |
541,7 → 544,8
.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData), |
.TxDoneOut(TxDone), .TxAbortOut(TxAbort), |
.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm), |
.ReceivedPauseFrm(ReceivedPauseFrm) |
.ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK), |
.LoadRxStatus(LoadRxStatus), .SetPauseTimer(SetPauseTimer) |
); |
|
|
620,7 → 624,7
.StateSFD(RxStateSFD), .StateData(RxStateData), |
.MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro), |
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort), |
.AddressMiss(AddressMiss) |
.AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK) |
); |
|
|
770,8 → 774,56
end |
|
|
wire LatchedMRxErr; |
reg RxAbort_latch; |
reg RxAbort_sync1; |
reg RxAbort_sync2; |
reg RxAbort_wb; |
reg RxAbortRst_sync1; |
reg RxAbortRst; |
|
// Synchronizing RxAbort to the WISHBONE clock |
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
RxAbort_latch <= #Tp 1'b0; |
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll))) |
RxAbort_latch <= #Tp 1'b1; |
else if(RxAbortRst) |
RxAbort_latch <= #Tp 1'b0; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
RxAbort_sync1 <= #Tp 1'b0; |
RxAbort_wb <= #Tp 1'b0; |
RxAbort_wb <= #Tp 1'b0; |
end |
else |
begin |
RxAbort_sync1 <= #Tp RxAbort_latch; |
RxAbort_wb <= #Tp RxAbort_sync1; |
end |
end |
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
RxAbortRst_sync1 <= #Tp 1'b0; |
RxAbortRst <= #Tp 1'b0; |
end |
else |
begin |
RxAbortRst_sync1 <= #Tp RxAbort_wb; |
RxAbortRst <= #Tp RxAbortRst_sync1; |
end |
end |
|
|
|
// Connecting Wishbone module |
eth_wishbone wishbone |
( |
803,7 → 855,7
|
// Register |
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum), |
.TX_BD_NUM_Wr(TX_BD_NUM_Wr), |
.TX_BD_NUM_Wr(TX_BD_NUM_Wr), .r_RxFlow(r_RxFlow), |
|
//RX |
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid), |
811,13 → 863,14
.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ), |
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ), |
|
.RxAbort(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | ReceivedPauseFrm & ~r_PassAll), |
.RxAbort(RxAbort_wb), |
|
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt), |
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble), |
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched), |
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched), |
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss) |
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss), |
.ReceivedPauseFrm(ReceivedPauseFrm) |
|
`ifdef ETH_BIST |
, |
840,7 → 893,7
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble), |
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt), |
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame), |
.ReceivedPauseFrm(ReceivedPauseFrm),.InvalidSymbol(InvalidSymbol), |
.InvalidSymbol(InvalidSymbol), |
.MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i), |
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall), |
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame), |
/trunk/rtl/verilog/eth_macstatus.v
41,6 → 41,11
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.13 2002/11/13 22:30:58 tadejm |
// Late collision is reported only when not in the full duplex. |
// Sample is taken (for status) as soon as MRxDV is not valid (regardless |
// of the received byte cnt). |
// |
// Revision 1.12 2002/09/12 14:50:16 mohor |
// CarrierSenseLost bug fixed when operating in full duplex mode. |
// |
100,7 → 105,7
module eth_macstatus( |
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError, |
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting, |
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm, |
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, |
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision, |
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn, |
LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured, |
129,7 → 134,6
input RxByteCntEq0; |
input RxByteCntGreat2; |
input RxByteCntMaxFrame; |
input ReceivedPauseFrm; |
input [3:0] MRxD; |
input Collision; |
input [5:0] CollValid; |
/trunk/rtl/verilog/eth_registers.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.23 2002/11/19 18:13:49 mohor |
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. |
// |
// Revision 1.22 2002/11/14 18:37:20 mohor |
// r_Rst signal does not reset any module any more and is removed from the design. |
// |
153,7 → 156,7
LinkFail, r_MAC, WCtrlDataStart, RStatStart, |
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o, |
r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm, |
StartTxDone, TxClk, RxClk, ReceivedPauseFrm |
StartTxDone, TxClk, RxClk, SetPauseTimer |
); |
|
parameter Tp = 1; |
244,7 → 247,7
input StartTxDone; |
input TxClk; |
input RxClk; |
input ReceivedPauseFrm; // sinhroniziraj tale shit da bo delal interrupt. Pazi na PassAll bit |
input SetPauseTimer; |
|
reg irq_txb; |
reg irq_txe; |
262,7 → 265,9
reg SetRxCIrq_rxclk; |
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3; |
reg SetRxCIrq; |
reg ResetRxCIrq_sync1, ResetRxCIrq_sync2; |
reg ResetRxCIrq_sync1; |
reg ResetRxCIrq_sync2; |
reg ResetRxCIrq_sync3; |
|
wire Write = Cs & Rw; |
wire Read = Cs & ~Rw; |
781,10 → 786,10
if(Reset) |
SetRxCIrq_rxclk <=#Tp 1'b0; |
else |
if(ReceivedPauseFrm & r_RxFlow) |
if(SetPauseTimer & r_RxFlow) |
SetRxCIrq_rxclk <=#Tp 1'b1; |
else |
if(ResetRxCIrq_sync2) |
if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3)) |
SetRxCIrq_rxclk <=#Tp 1'b0; |
end |
|
829,20 → 834,24
ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2; |
end |
|
always @ (posedge TxClk or posedge Reset) |
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
ResetRxCIrq_sync2 <=#Tp 1'b0; |
else |
ResetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1; |
ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1; |
end |
|
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
ResetRxCIrq_sync3 <=#Tp 1'b0; |
else |
ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2; |
end |
|
|
|
|
|
|
// Interrupt generation |
always @ (posedge Clk or posedge Reset) |
begin |