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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 285 to Rev 286
    Reverse comparison

Rev 285 → Rev 286

/trunk/bench/verilog/tb_eth_defines.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2002/11/19 20:27:46 mohor
// Temp version.
//
// Revision 1.9 2002/10/09 13:16:51 tadejm
// Just back-up; not completed testbench and some testcases are not
// wotking properly yet.
87,13 → 90,6
`define TX_BD_BASE `ETH_BASE + 32'h00000400
`define RX_BD_BASE `ETH_BASE + 32'h00000600
 
`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
 
 
 
/* Tx BD */
`define ETH_TX_BD_READY 32'h8000 /* Tx BD Ready */
`define ETH_TX_BD_IRQ 32'h4000 /* Tx BD IRQ Enable */
/trunk/rtl/verilog/eth_defines.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.29 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
// Revision 1.28 2002/11/15 14:27:15 mohor
// Since r_Rst bit is not used any more, default value is changed to 0xa000.
//
259,3 → 262,16
// WISHBONE interface is Revision B3 compliant (uncomment when needed)
//`define ETH_WISHBONE_B3
 
 
// Following defines are needed when eth_cop.v is used. Otherwise they may be deleted.
`define ETH_BASE 32'hd0000000
`define ETH_WIDTH 32'h800
`define MEMORY_BASE 32'h2000
`define MEMORY_WIDTH 32'h10000
 
`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
// Previous defines are only needed for eth_cop.v
 
/trunk/rtl/verilog/eth_cop.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/10/10 16:43:59 mohor
// Minor $display change.
//
// Revision 1.2 2002/09/09 12:54:13 mohor
// error acknowledge cycle termination added to display.
//
58,7 → 61,7
//
//
 
`include "tb_eth_defines.v"
`include "eth_defines.v"
`include "timescale.v"
 
module eth_cop
382,4 → 385,4
 
 
 
endmodule
endmodule

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