OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 298 to Rev 299
    Reverse comparison

Rev 298 → Rev 299

/trunk/bench/verilog/tb_ethernet_with_cop.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/10/18 17:03:34 tadejm
// Changed BIST scan signals.
//
// Revision 1.2 2002/10/11 13:29:28 mohor
// Bist signals added.
//
191,7 → 194,7
// Bist
`ifdef ETH_BIST
,
.scanb_rst (1'b0),
.scanb_rst (1'b1),
.scanb_clk (1'b0),
.scanb_si (1'b0),
.scanb_so (),
/trunk/bench/verilog/tb_ethernet.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.28 2003/01/31 15:58:27 mohor
// Tests test_mac_full_duplex_receive 4-7 fixed to proper BD.
//
// Revision 1.27 2003/01/30 13:38:15 mohor
// Underrun test fixed. Many other tests fixed.
//
208,7 → 211,7
// Bist
`ifdef ETH_BIST
,
.scanb_rst (1'b0),
.scanb_rst (1'b1),
.scanb_clk (1'b0),
.scanb_si (1'b0),
.scanb_so (),
/trunk/sim/rtl_sim/bin/sim_file_list.lst
6,5 → 6,9
../../../bench/verilog/wb_slave_behavioral.v
../../../bench/verilog/wb_master32.v
../../../bench/verilog/wb_master_behavioral.v
../../../../../lib/vs_rams/018/vs_hdsp_256x32/vs_hdsp_256x32.v
../../../../../lib/artisan/art_hssp_256x32_bist.v
../../../../../lib/artisan/art_hssp_256x32/art_hssp_256x32.v
../../../../../bist/rtl/verilog/bist.v
../../../../../bist/rtl/verilog/bist_sp_top.v
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.