URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
/
- from Rev 350 to Rev 351
- ↔ Reverse comparison
Rev 350 → Rev 351
/ethmac/trunk/rtl/verilog/eth_defines.v
330,12 → 330,3
// WISHBONE interface is Revision B3 compliant (uncomment when needed) |
//`define ETH_WISHBONE_B3 |
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// Following defines are needed when eth_cop.v is used. Otherwise they may be deleted. |
`define ETH_BASE 32'hd0000000 |
`define ETH_WIDTH 32'h800 |
`define MEMORY_BASE 32'h2000 |
`define MEMORY_WIDTH 32'h10000 |
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// Previous defines are only needed for eth_cop.v |
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/ethmac/trunk/rtl/verilog/eth_cop.v
61,7 → 61,6
// |
// |
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`include "eth_defines.v" |
`include "timescale.v" |
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module eth_cop |
91,7 → 90,11
); |
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parameter Tp=1; |
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parameter ETH_BASE = 32'hd0000000; |
parameter ETH_WIDTH = 32'h800; |
parameter MEMORY_BASE = 32'h2000; |
parameter MEMORY_WIDTH = 32'h10000; |
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// WISHBONE common |
input wb_clk_i, wb_rst_i; |
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147,14 → 150,14
reg m2_wb_err_o; |
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wire m_wb_access_finished; |
wire m1_addressed_s1 = (m1_wb_adr_i >= `ETH_BASE) & |
(m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH)); |
wire m1_addressed_s2 = (m1_wb_adr_i >= `MEMORY_BASE) & |
(m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)); |
wire m2_addressed_s1 = (m2_wb_adr_i >= `ETH_BASE) & |
(m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH)); |
wire m2_addressed_s2 = (m2_wb_adr_i >= `MEMORY_BASE) & |
(m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)); |
wire m1_addressed_s1 = (m1_wb_adr_i >= ETH_BASE) & |
(m1_wb_adr_i < (ETH_BASE + ETH_WIDTH)); |
wire m1_addressed_s2 = (m1_wb_adr_i >= MEMORY_BASE) & |
(m1_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH)); |
wire m2_addressed_s1 = (m2_wb_adr_i >= ETH_BASE) & |
(m2_wb_adr_i < (ETH_BASE + ETH_WIDTH)); |
wire m2_addressed_s2 = (m2_wb_adr_i >= MEMORY_BASE) & |
(m2_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH)); |
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wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (m1_addressed_s1 | m1_addressed_s2); |
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (m2_addressed_s1 | m2_addressed_s2); |