OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 42 to Rev 41
    ↔ Reverse comparison
  •

Rev 42 → Rev 41

/trunk/rtl/verilog/eth_wishbone.v
41,9 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.3 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
99,15 → 96,12
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
// Register
r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr, r_RecSmall,
r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr,
 
WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ
 
);
 
139,16 → 133,14
 
input Reset; // Reset signal
 
// Status signals
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
input LatchedCrcError; // CRC error
input RxLateCollision; // Late collision occured while receiving frame
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
input DribbleNibble; // Extra nibble received
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input [15:0] RxLength; // Length of the incoming frame
input LoadRxStatus; // Rx status was loaded
 
 
// DMA
// input [1:0] WB_ACK_I; // DMA acknowledge input
// output [1:0] WB_REQ_O; // DMA request output
// output [1:0] WB_ND_O; // DMA force new descriptor output
// output WB_RD_O; // DMA restart descriptor output
 
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
181,7 → 173,6
input [7:0] r_TxBDNum; // Receive buffer descriptor number
input r_DmaEn; // DMA enable
input TX_BD_NUM_Wr; // RxBDNumber written
input r_RecSmall; // Receive small frames igor !!! tega uporabi
 
// Interrupts
output TxB_IRQ;
204,7 → 195,7
reg [15:0] TxLength;
reg [15:0] TxStatus;
 
reg [14:13] RxStatusOld;
reg [15:0] RxStatus;
 
reg TxStartFrm_wb;
reg TxRetry_wb;
249,7 → 240,6
reg ShiftWillEnd;
 
reg WriteRxDataToFifo;
reg [15:0] LatchedRxLength;
 
reg ShiftEnded;
 
279,14 → 269,14
wire [7:0] TempTxBDAddress;
wire [7:0] TempRxBDAddress;
 
reg [15:0] RxLength;
wire [15:0] NewRxStatus;
 
wire SetGotData;
wire GotDataEvaluate;
 
reg temp_ack;
 
wire [5:0] RxStatusIn;
reg [5:0] RxStatusInLatched;
 
`ifdef ETH_REGISTERED_OUTPUTS
reg temp_ack2;
reg [31:0] registered_ram_do;
366,6 → 356,8
end
 
 
reg [3:0] debug;
 
// Enabling access to the RAM for three devices.
always @ (posedge WB_CLK_I or posedge Reset)
begin
376,6 → 368,7
TxEn <=#Tp 1'b0;
ram_addr <=#Tp 8'h0;
ram_di <=#Tp 32'h0;
debug <=#Tp 4'h0;
end
else
begin
388,6 → 381,7
TxEn <=#Tp 1'b0;
ram_addr <=#Tp RxBDAddress + RxPointerRead;
ram_di <=#Tp RxBDDataIn;
debug <=#Tp 4'h1;
end
5'b100_01 :
begin
396,6 → 390,7
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
ram_addr <=#Tp TxBDAddress + TxPointerRead;
ram_di <=#Tp TxBDDataIn;
debug <=#Tp 4'h2;
end
5'b010_x0 :
begin
406,6 → 401,7
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs & WB_WE_I;
BDRead <=#Tp BDCs & ~WB_WE_I;
debug <=#Tp 4'h3;
end
5'b010_x1 :
begin
414,6 → 410,7
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
ram_addr <=#Tp TxBDAddress + TxPointerRead;
ram_di <=#Tp TxBDDataIn;
debug <=#Tp 4'h4;
end
5'b001_xx :
begin
424,10 → 421,12
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs & WB_WE_I;
BDRead <=#Tp BDCs & ~WB_WE_I;
debug <=#Tp 4'h5;
end
5'b100_00 :
begin
WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
debug <=#Tp 4'h6;
end
5'b000_00 :
begin
438,6 → 437,7
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs & WB_WE_I;
BDRead <=#Tp BDCs & ~WB_WE_I;
debug <=#Tp 4'h7;
end
default :
begin
448,6 → 448,7
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs & WB_WE_I;
BDRead <=#Tp BDCs & ~WB_WE_I;
debug <=#Tp 4'h8;
end
endcase
end
961,7 → 962,7
// bit 4 od rx je carrier sense lost
// bit [3:0] od rx je retry count
 
assign WrapRxStatusBit = RxStatusOld[13];
assign WrapRxStatusBit = RxStatus[13];
 
 
// Temporary Tx and Rx buffer descriptor address
994,7 → 995,10
RxBDAddress <=#Tp TempRxBDAddress;
end
 
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatusOld, 7'h0, RxStatusInLatched}; // tu dopolni, da se bo vpisoval status
assign NewRxStatus[15:0] = 16'hdead;
 
 
assign RxBDDataIn = {RxLength, NewRxStatus}; // tu dopolni, da se bo vpisoval status
assign TxBDDataIn = {32'h004380ef}; // tu dopolni, da se bo vpisoval status
 
 
1309,10 → 1313,10
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatusOld <=#Tp 2'h0;
RxStatus <=#Tp 16'h0;
else
if(RxEn & RxEn_q & RxBDRead)
RxStatusOld <=#Tp ram_do[14:13];
RxStatus <=#Tp ram_do[15:0];
end
 
 
1380,31 → 1384,6
// Reception status is written back to the buffer descriptor after the end of frame is detected.
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
 
reg RxStatusWriteLatched;
reg RxStatusWrite_rck;
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWrite)
RxStatusWriteLatched <=#Tp 1'b1;
else
if(RxStatusWrite_rck)
RxStatusWriteLatched <=#Tp 1'b0;
end
 
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxStatusWrite_rck <=#Tp 1'b0;
else
RxStatusWrite_rck <=#Tp RxStatusWriteLatched;
end
 
 
reg RxEnableWindow;
 
// Indicating that last byte is being reveived
1505,7 → 1484,20
endcase
end
 
// Assembling data that will be written to the rx_fifo
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxLength <=#Tp 16'h0;
else
if(RxStartFrm)
RxLength <=#Tp 16'h1;
else
if(RxValid & (RxStartFrm | RxEnableWindow))
RxLength <=#Tp RxLength + 1'b1;
end
 
 
reg WriteRxDataToFifoSync1;
reg WriteRxDataToFifoSync2;
 
1672,44 → 1664,5
assign Busy_IRQ = 1'b0;
 
 
 
reg LoadStatusBlocked;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LoadStatusBlocked <=#Tp 1'b0;
else
if(LoadRxStatus)
LoadStatusBlocked <=#Tp 1'b1;
else
if(RxStatusWrite_rck)
LoadStatusBlocked <=#Tp 1'b0;
end
 
// LatchedRxLength[15:0]
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxLength[15:0] <=#Tp 16'h0;
else
if(LoadRxStatus & ~LoadStatusBlocked)
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
end
 
 
 
assign RxStatusIn = {InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxStatusInLatched <=#Tp 'h0;
else
if(LoadRxStatus & ~LoadStatusBlocked)
RxStatusInLatched <=#Tp RxStatusIn;
end
 
 
 
endmodule
 
/trunk/rtl/verilog/eth_wishbonedma.v
41,9 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.10 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
119,17 → 116,13
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm,
// Register
r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr, r_RecSmall,
r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr,
 
WillSendControlFrame, TxCtrlEndFrm,
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ
 
 
);
 
 
154,16 → 147,6
output [1:0] WB_ND_O; // DMA force new descriptor output
output WB_RD_O; // DMA restart descriptor output
 
// Status
input InvalidSymbol;
input LatchedCrcError;
input RxLateCollision;
input ShortFrame;
input DribbleNibble;
input ReceivedPacketTooBig;
input [15:0] RxLength;
input LoadRxStatus;
 
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
195,7 → 178,6
input [7:0] r_TxBDNum; // Receive buffer descriptor number
input r_DmaEn; // DMA enable
input TX_BD_NUM_Wr; // RxBDNumber written
input r_RecSmall; // Receive small frames
 
// Interrupts
output TxB_IRQ;
382,6 → 364,7
wire [7:0] TempTxBDAddress;
wire [7:0] TempRxBDAddress;
 
wire [15:0] RxLength;
wire [15:0] NewRxStatus;
 
wire SetGotData;
852,11 → 835,13
end
 
 
assign RxLength[15:0] = 16'h1399;
assign NewRxStatus[15:0] = {1'b0, WbWriteError, RxStatus[13:0]};
 
 
//assign BDDataIn = TxStatusWrite ? {TxLength[15:0], StatusIzTxEthMACModula} : {RxLength, NewRxStatus};
assign BDDataIn = TxStatusWrite ? {TxStatus[31:9], 9'h0}
: {16'h1399, NewRxStatus};
: {RxLength, NewRxStatus};
 
assign BDStatusWrite = TxStatusWrite | RxStatusWrite;
 
/trunk/rtl/verilog/eth_top.v
41,9 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.9 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
222,7 → 219,6
wire TxAbort;
wire TxUnderRun;
wire TxDone;
wire [5:0] CollValid;
 
 
 
245,7 → 241,6
wire RegCs; // Connected to registers
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
wire r_DmaEn; // DMA enable
wire r_RecSmall; // Receive small frames
wire r_Rst; // Reset
wire r_LoopBck; // Loopback
wire r_TxEn; // Tx Enable
260,11 → 255,7
wire [15:0] r_MaxFL; // Maximum frame length
 
wire [15:0] r_MinFL; // Minimum frame length
wire ShortFrame;
wire DribbleNibble; // Extra nibble received
wire ReceivedPacketTooBig; // Received packet is too big
wire [47:0] r_MAC; // MAC address
wire LoadRxStatus; // Rx status was loaded
 
wire [7:0] r_TxBDNum; // Receive buffer descriptor number
wire [6:0] r_IPGT; //
310,7 → 301,7
(
.DataIn(wb_dat_i), .Address(wb_adr_i[7:2]), .Rw(wb_we_i),
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
.DataOut(RegDataOut), .r_DmaEn(r_DmaEn), .r_RecSmall(r_RecSmall),
.DataOut(RegDataOut), .r_DmaEn(r_DmaEn), .r_RecSmall(),
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
.r_DlyCrcEn(r_DlyCrcEn), .r_Rst(r_Rst), .r_FullD(r_FullD),
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
348,9 → 339,6
wire ReceiveEnd;
wire ReceivedPacketGood;
wire ReceivedLengthOK;
wire InvalidSymbol;
wire LatchedCrcError;
wire RxLateCollision;
 
// Connecting MACControl
eth_maccontrol maccontrol1
574,23 → 562,20
 
// Register
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
.r_DmaEn(r_DmaEn), .TX_BD_NUM_Wr(TX_BD_NUM_Wr), .r_RecSmall(r_RecSmall),
.r_DmaEn(r_DmaEn), .TX_BD_NUM_Wr(TX_BD_NUM_Wr),
 
//RX
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ)
 
`ifdef WISHBONE_DMA
`else
.RxAbort(RxAbort),
,
.RxAbort(RxAbort)
`endif
 
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus)
 
);
 
 
598,18 → 583,13
// Connecting MacStatus module
eth_macstatus macstatus1
(
.MRxClk(mrx_clk_pad_i), .Reset(r_Rst),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
.ReceivedPauseFrm(ReceivedPauseFrm),.InvalidSymbol(InvalidSymbol),
.MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
.LoadRxStatus(LoadRxStatus)
.MRxClk(mrx_clk_pad_i), .Reset(r_Rst), .TransmitEnd(),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
.ReceivedPauseFrm(ReceivedPauseFrm)
);
 
 
/trunk/rtl/verilog/eth_defines.v
41,11 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/02/05 16:44:38 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
// Revision 1.7 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
126,7 → 121,7
`define ETH_IPGR1_DEF 32'h0000000C
`define ETH_IPGR2_DEF 32'h00000012
`define ETH_PACKETLEN_DEF 32'h003C0600
`define ETH_COLLCONF_DEF 32'h000F003f
`define ETH_COLLCONF_DEF 32'h000F0040
`define ETH_CTRLMODER_DEF 32'h00000000
`define ETH_MIIMODER_DEF 32'h00000064
`define ETH_MIICOMMAND_DEF 32'h00000000
/trunk/rtl/verilog/eth_macstatus.v
41,9 → 41,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
73,12 → 70,9
 
 
module eth_macstatus(
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, TransmitEnd, ReceivedPacketGood, RxCrcError,
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
LoadRxStatus
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm
);
 
 
102,35 → 96,22
input RxByteCntGreat2;
input RxByteCntMaxFrame;
input ReceivedPauseFrm;
input [3:0] MRxD;
input Collision;
input [5:0] CollValid;
input r_RecSmall;
input [15:0] r_MinFL;
input [15:0] r_MaxFL;
input r_HugEn;
 
output ReceivedLengthOK;
output ReceiveEnd;
output ReceivedPacketGood;
output InvalidSymbol;
output LatchedCrcError;
output RxLateCollision;
output ShortFrame;
output DribbleNibble;
output ReceivedPacketTooBig;
output LoadRxStatus;
output TransmitEnd;
 
reg ReceiveEnd;
 
reg LatchedCrcError;
reg LatchedMRxErr;
reg LoadRxStatus;
reg InvalidSymbol;
reg PreloadRxStatus;
reg [15:0] LatchedRxByteCnt;
 
wire TakeSample;
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
 
 
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
137,11 → 118,13
if(Reset)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateSFD)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateData[0])
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
begin
if(RxStateSFD)
LatchedCrcError <=#Tp 1'b0;
else
if(RxStateData[0])
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
end
end
 
 
164,129 → 147,51
 
 
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] > 63 & RxByteCnt[15:0] < 1519;
assign ReceivedLengthOK = LatchedRxByteCnt[15:0] > 63 & LatchedRxByteCnt[15:0] < 1519;
 
 
 
 
 
// Time to take a sample
assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
RxStateData[0] & MRxDV & RxByteCntMaxFrame;
 
 
// LoadRxStatus
// LatchedRxByteCnt[15:0]
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LoadRxStatus <=#Tp 1'b0;
LatchedRxByteCnt[15:0] <=#Tp 16'h0;
else
LoadRxStatus <=#Tp TakeSample;
begin
if(RxStateSFD)
LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0];
else
if(RxStateData[0])
LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0];
end
end
 
 
 
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceiveEnd <=#Tp 1'b0;
else
ReceiveEnd <=#Tp LoadRxStatus;
end
// Time to take a sample
assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
RxStateData[0] & MRxDV & RxByteCntMaxFrame;
 
 
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & ~LatchedMRxErr & MRxD[3:0] == 4'he;
 
 
// InvalidSymbol
// PreloadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
InvalidSymbol <=#Tp 1'b0;
PreloadRxStatus <=#Tp 1'b0;
else
if(LoadRxStatus & ~SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b0;
else
if(SetInvalidSymbol)
InvalidSymbol <=#Tp 1'b1;
PreloadRxStatus <=#Tp TakeSample;
end
 
 
// Late Collision
 
reg RxLateCollision;
reg RxColWindow;
// Collision Window
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxLateCollision <=#Tp 1'b0;
ReceiveEnd <=#Tp 1'b0;
else
if(LoadRxStatus)
RxLateCollision <=#Tp 1'b0;
else
if(Collision & (~RxColWindow | r_RecSmall))
RxLateCollision <=#Tp 1'b1;
ReceiveEnd <=#Tp PreloadRxStatus;
end
 
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxColWindow <=#Tp 1'b1;
else
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
RxColWindow <=#Tp 1'b0;
else
if(RxStateIdle)
RxColWindow <=#Tp 1'b1;
end
 
 
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShortFrame <=#Tp 1'b0;
else
if(LoadRxStatus)
ShortFrame <=#Tp 1'b0;
else
if(TakeSample)
ShortFrame <=#Tp r_RecSmall & RxByteCnt[15:0] < r_MinFL[15:0];
end
 
 
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DribbleNibble <=#Tp 1'b0;
else
if(RxStateSFD)
DribbleNibble <=#Tp 1'b0;
else
if(~MRxDV & RxStateData[1])
DribbleNibble <=#Tp 1'b1;
end
 
 
reg ReceivedPacketTooBig;
assign ReceivedLengthOK = RxByteCnt[15:0] > 63 & RxByteCnt[15:0] < 1519;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(LoadRxStatus)
ReceivedPacketTooBig <=#Tp 1'b0;
else
if(TakeSample)
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.