URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 87 to Rev 86
- ↔ Reverse comparison
Rev 87 → Rev 86
/trunk/rtl/verilog/eth_wishbone.v
41,9 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.15 2002/03/08 06:56:46 mohor |
// Big Endian problem when sending frames fixed. |
// |
// Revision 1.14 2002/03/02 19:12:40 mohor |
// Byte ordering changed (Big Endian used). casex changed with case because |
// Xilinx Foundation had problems. Tested in HW. It WORKS. |
1446,7 → 1443,7
if(Reset) |
RxStatusWriteLatched <=#Tp 1'b0; |
else |
if(RxStatusWrite & ~RxStatusWrite_rck) |
if(RxStatusWrite) |
RxStatusWriteLatched <=#Tp 1'b1; |
else |
if(RxStatusWrite_rck) |
1459,10 → 1456,7
if(Reset) |
RxStatusWrite_rck <=#Tp 1'b0; |
else |
if(RxStatusWriteLatched) |
RxStatusWrite_rck <=#Tp 1'b1; |
else |
RxStatusWrite_rck <=#Tp 1'b0; |
RxStatusWrite_rck <=#Tp RxStatusWriteLatched; |
end |
|
|
1753,7 → 1747,7
if(LoadRxStatus & ~RxAbortLatched) |
LoadStatusBlocked <=#Tp 1'b1; |
else |
if(RxStatusWrite_rck | RxStartFrm) |
if(RxStatusWrite_rck) |
LoadStatusBlocked <=#Tp 1'b0; |
end |
|