URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
/
- from Rev 88 to Rev 87
- ↔ Reverse comparison
Rev 88 → Rev 87
/trunk/rtl/verilog/eth_wishbone.v
41,9 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.16 2002/03/09 13:51:20 mohor |
// Status was not latched correctly sometimes. Fixed. |
// |
// Revision 1.15 2002/03/08 06:56:46 mohor |
// Big Endian problem when sending frames fixed. |
// |
1629,13 → 1626,10
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eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH) |
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o), |
.clk(WB_CLK_I), .reset(Reset), |
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i), |
.clear(RxAbortSync2 | RxStatusWriteLatched), .full(RxBufferFull), |
.almost_full(RxBufferAlmostFull), .almost_empty(RxBufferAlmostEmpty), |
.empty(RxBufferEmpty) |
); |
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o), .clk(WB_CLK_I), |
.reset(Reset), .write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i), |
.clear(RxAbortSync2), .full(RxBufferFull), .almost_full(RxBufferAlmostFull), |
.almost_empty(RxBufferAlmostEmpty), .empty(RxBufferEmpty)); |
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assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty); |
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