URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
/
- from Rev 90 to Rev 89
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Rev 90 → Rev 89
/trunk/rtl/verilog/eth_wishbone.v
41,9 → 41,6
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.17 2002/03/09 16:08:45 mohor |
// rx_fifo was not always cleared ok. Fixed. |
// |
// Revision 1.16 2002/03/09 13:51:20 mohor |
// Status was not latched correctly sometimes. Fixed. |
// |
326,6 → 323,7
wire TxAbortPulse; |
|
wire StartRxBDRead; |
wire StartRxStatusWrite; |
|
wire StartTxBDRead; |
|
442,8 → 440,8
else |
begin |
// Switching between three stages depends on enable signals |
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case |
5'b100_10, 5'b100_11 : |
casex ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case |
5'b100_1x : |
begin |
WbEn <=#Tp 1'b0; |
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled |
459,7 → 457,7
ram_addr <=#Tp TxBDAddress + TxPointerRead; |
ram_di <=#Tp TxBDDataIn; |
end |
5'b010_00, 5'b010_10 : |
5'b010_x0 : |
begin |
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled |
RxEn <=#Tp 1'b0; |
469,7 → 467,7
BDWrite <=#Tp BDCs & WB_WE_I; |
BDRead <=#Tp BDCs & ~WB_WE_I; |
end |
5'b010_01, 5'b010_11 : |
5'b010_x1 : |
begin |
WbEn <=#Tp 1'b0; |
RxEn <=#Tp 1'b0; |
477,7 → 475,7
ram_addr <=#Tp TxBDAddress + TxPointerRead; |
ram_di <=#Tp TxBDDataIn; |
end |
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 : |
5'b001_xx : |
begin |
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage) |
RxEn <=#Tp 1'b0; |
571,7 → 569,7
if(Reset) |
TxBDRead <=#Tp 1'b1; |
else |
if(StartTxBDRead & ~TxBDReady) |
if(StartTxBDRead) |
TxBDRead <=#Tp 1'b1; |
else |
if(TxBDReady) |
621,7 → 619,7
if(Reset) |
BlockingTxBDRead <=#Tp 1'b0; |
else |
if(StartTxBDRead & ~TxBDReady) |
if(StartTxBDRead) |
BlockingTxBDRead <=#Tp 1'b1; |
else |
if(TxStartFrm_wb) |
755,7 → 753,7
if(Reset) |
BlockReadTxDataFromMemory <=#Tp 1'b0; |
else |
if(ReadTxDataFromFifo_wb | ResetReadTxDataFromMemory) |
if(ReadTxDataFromFifo_wb) |
BlockReadTxDataFromMemory <=#Tp 1'b0; |
else |
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX) |
767,8 → 765,8
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i; |
|
assign m_wb_sel_o = 4'hf; |
reg[3:0] state; |
|
|
// Enabling master wishbone access to the memory for two devices TX and RX. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
780,7 → 778,6
m_wb_cyc_o <=#Tp 1'b0; |
m_wb_stb_o <=#Tp 1'b0; |
m_wb_we_o <=#Tp 1'b0; |
state <=#Tp 4'h0; |
end |
else |
begin |
794,7 → 791,6
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_stb_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b1; |
state <=#Tp 4'h1; |
end |
5'b00_10_0, 5'b00_10_1 : |
begin |
804,7 → 800,6
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_stb_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b0; |
state <=#Tp 4'h2; |
end |
5'b10_10_1 : |
begin |
814,7 → 809,6
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_stb_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b0; |
state <=#Tp 4'h3; |
end |
5'b01_01_1 : |
begin |
822,7 → 816,6
MasterWbRX <=#Tp 1'b1; |
m_wb_adr_o <=#Tp RxPointer; |
m_wb_we_o <=#Tp 1'b1; |
state <=#Tp 4'h4; |
end |
5'b10_01_1, 5'b10_11_1 : |
begin |
830,7 → 823,6
MasterWbRX <=#Tp 1'b1; |
m_wb_adr_o <=#Tp RxPointer; |
m_wb_we_o <=#Tp 1'b1; |
state <=#Tp 4'h5; |
end |
5'b01_10_1, 5'b01_11_1 : |
begin |
838,7 → 830,6
MasterWbRX <=#Tp 1'b0; |
m_wb_adr_o <=#Tp TxPointer; |
m_wb_we_o <=#Tp 1'b0; |
state <=#Tp 4'h6; |
end |
5'b10_00_1, 5'b01_00_1 : |
begin |
846,7 → 837,6
MasterWbRX <=#Tp 1'b0; |
m_wb_cyc_o <=#Tp 1'b0; |
m_wb_stb_o <=#Tp 1'b0; |
state <=#Tp 4'h7; |
end |
default: // Don't touch |
begin |
854,7 → 844,6
MasterWbRX <=#Tp MasterWbRX; |
m_wb_cyc_o <=#Tp m_wb_cyc_o; |
m_wb_stb_o <=#Tp m_wb_stb_o; |
state <=#Tp state; |
end |
endcase |
end |
1344,7 → 1333,7
end |
|
|
assign StartRxBDRead = RxStatusWrite | RxAbortLatched; |
assign StartRxBDRead = RxStatusWrite | RxAbort; |
|
// Reading the Rx buffer descriptor |
always @ (posedge WB_CLK_I or posedge Reset) |
1352,7 → 1341,7
if(Reset) |
RxBDRead <=#Tp 1'b1; |
else |
if(StartRxBDRead & ~RxBDReady) |
if(StartRxBDRead) |
RxBDRead <=#Tp 1'b1; |
else |
if(RxBDReady) |
1638,53 → 1627,12
reg RxAbortSyncb1; |
reg RxAbortSyncb2; |
|
reg LatchedRxStartFrm; |
reg SyncRxStartFrm; |
reg SyncRxStartFrm_q; |
wire RxFifoReset; |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedRxStartFrm <=#Tp 0; |
else |
if(RxStartFrm & ~SyncRxStartFrm) |
LatchedRxStartFrm <=#Tp 1; |
else |
if(SyncRxStartFrm) |
LatchedRxStartFrm <=#Tp 0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm <=#Tp 0; |
else |
if(LatchedRxStartFrm) |
SyncRxStartFrm <=#Tp 1; |
else |
SyncRxStartFrm <=#Tp 0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm_q <=#Tp 0; |
else |
SyncRxStartFrm_q <=#Tp SyncRxStartFrm; |
end |
|
|
assign RxFifoReset = SyncRxStartFrm & ~SyncRxStartFrm_q; |
|
|
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH) |
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o), |
.clk(WB_CLK_I), .reset(Reset), |
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i), |
.clear(RxFifoReset), .full(RxBufferFull), |
.clear(RxAbortSync2 | RxStatusWriteLatched), .full(RxBufferFull), |
.almost_full(RxBufferAlmostFull), .almost_empty(RxBufferAlmostEmpty), |
.empty(RxBufferEmpty) |
); |
1699,10 → 1647,10
if(Reset) |
ShiftEnded_tck <=#Tp 1'b0; |
else |
if(SetWriteRxDataToFifo & StartShiftWillEnd & ~RxAbort & ~ShiftEnded_tck) |
if(SetWriteRxDataToFifo & StartShiftWillEnd & ~RxAbort) |
ShiftEnded_tck <=#Tp 1'b1; |
else |
if(ShiftEnded | RxAbort) |
if(ShiftEndedSync2 | RxAbort) |
ShiftEnded_tck <=#Tp 1'b0; |
end |
|
1719,7 → 1667,11
if(Reset) |
ShiftEndedSync2 <=#Tp 1'b0; |
else |
ShiftEndedSync2 <=#Tp ShiftEndedSync1; |
if(ShiftEndedSync1) |
ShiftEndedSync2 <=#Tp 1'b1; |
else |
if(ShiftEnded) |
ShiftEndedSync2 <=#Tp 1'b0; |
end |
|
|
1729,7 → 1681,7
if(Reset) |
ShiftEnded <=#Tp 1'b0; |
else |
if(ShiftEndedSync2 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded) |
if(ShiftEndedSync2 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty) |
ShiftEnded <=#Tp 1'b1; |
else |
if(RxStatusWrite) |