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    from Rev 163 to Rev 164
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Rev 163 → Rev 164

/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.34 2002/09/08 16:31:49 mohor
// Async reset for WB_ACK_O removed (when core was in reset, it was
// impossible to access BDs).
// RxPointers and TxPointers names changed to be more descriptive.
// TxUnderRun synchronized.
//
// Revision 1.33 2002/09/04 18:47:57 mohor
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
195,16 → 201,13
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost,
reg1, reg2, reg3, reg4
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
 
);
 
 
parameter Tp = 1;
 
output [31:0] reg1, reg2, reg3, reg4;
 
// WISHBONE common
input WB_CLK_I; // WISHBONE clock
2188,68 → 2191,6
// bit 1 od rx je LatchedCrcError
// bit 0 od rx je RxLateCollision
 
assign reg1 = {RxPointerMSB[31:2], 2'h0}; /* 0x58 */
 
assign reg2 = { /* 0x5c */
RxStatusWriteLatched, // 31
RxStatusWrite_rck, // 30
RxEn_needed, // 29
StartRxBDRead, // 28
RxStatusWrite, // 27
1'b1, //RxAbortLatched, // 26
RxBDRead, // 25
RxBDReady, // 24
ShiftEnded, // 23
RxPointerRead, // 23
LastByteIn, // 21
ShiftWillEnd, // 20
2'h0, RxByteCnt[1:0], // 19:16
2'h0, RxPointerLSB_rst[1:0], // 15:12
RxBDAddress[7:0], // 11:4
4'h0 // 3:0
};
 
assign reg3 = { /* 0x60 */
ShiftEndedSync_c2, // 31
RxAbortSyncb1, // 30
RxAbortSyncb2, // 31
RxAbortSync1, // 30
RxAbortSync2, // 29
1'b0, //LoadStatusBlocked, // 28
LoadRxStatus, // 27
1'b0, //LoadStatusBlocked, // 26
RxOverrun, // 25
RxAbort, // 24
RxValid, // 23
RxEndFrm, // 22
RxEnableWindow, // 21
StartShiftWillEnd, // 20
ShiftWillEnd, // 19
ShiftEnded_rck, // 18
SetWriteRxDataToFifo, // 17
WriteRxDataToFifo, // 16
WriteRxDataToFifoSync3, // 15
WriteRxDataToFifoSync2, // 14
WriteRxDataToFifoSync1, // 13
WriteRxDataToFifo_wb, // 12
LatchedRxStartFrm, // 11
RxStartFrm, // 10
SyncRxStartFrm, // 9
SyncRxStartFrm_q, // 8
SyncRxStartFrm_q2, // 7
RxBufferEmpty, // 6
RxBufferFull, // 5
rxfifo_cnt[4:0] // 4:0
};
 
assign reg4 = { /* 0x64 */
WriteRxDataToMemory, // 4
ShiftEndedSync1, // 3
ShiftEndedSync2, // 2
ShiftEndedSync3, // 1
ShiftEndedSync_c1 // 0
};
 
 
endmodule
 
/trunk/rtl/verilog/eth_top.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.29 2002/09/09 13:03:13 mohor
// Error acknowledge is generated when accessing BDs and RST bit in the
// MODER register (r_Rst) is set.
//
// Revision 1.28 2002/09/04 18:44:10 mohor
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
// connected.
387,7 → 391,6
end
`endif
 
wire [31:0] reg1, reg2, reg3, reg4;
 
// Connecting Ethernet registers
eth_registers ethreg1
416,10 → 419,8
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
.ReceivedPauseFrm(ReceivedPauseFrm),
.ReceivedPauseFrm(ReceivedPauseFrm)
.reg1(reg1), .reg2(reg2), .reg3(reg3), .reg4(reg4)
 
);
 
 
708,10 → 709,8
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood),
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood)
.reg1(reg1), .reg2(reg2), .reg3(reg3), .reg4(reg4)
 
);
 
 
/trunk/rtl/verilog/eth_registers.v
41,6 → 41,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.20 2002/09/04 18:40:25 mohor
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
// the control frames connected.
//
// Revision 1.19 2002/08/19 16:01:40 mohor
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
143,14 → 147,11
LinkFail, r_MAC, WCtrlDataStart, RStatStart,
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
StartTxDone, TxClk, RxClk, ReceivedPauseFrm,
reg1, reg2, reg3, reg4
StartTxDone, TxClk, RxClk, ReceivedPauseFrm
);
 
parameter Tp = 1;
 
input [31:0] reg1, reg2, reg3, reg4;
 
input [31:0] DataIn;
input [7:0] Address;
 
609,7 → 610,6
MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
HASH0Out or HASH1Out or TXCTRLOut or RXCTRLOut
or reg1 or reg2 or reg3 or reg4
)
begin
if(Read) // read
638,11 → 638,6
`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
`ETH_RX_CTRL_ADR : DataOut<=RXCTRLOut;
 
8'h16 /* 0x58 */ : DataOut<=reg1;
8'h17 /* 0x5c */ : DataOut<=reg2;
8'h18 /* 0x60 */ : DataOut<=reg3;
8'h19 /* 0x64 */ : DataOut<=reg4;
 
default: DataOut<=32'h0;
endcase
end

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