OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 17 to Rev 18
    ↔ Reverse comparison
  •

Rev 17 → Rev 18

/trunk/rtl/verilog/eth_rxethmac.v
43,6 → 43,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
226,7 → 236,7
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
Broadcast <= #Tp 1'b0;
else
if(StateData[0] & &LatchedByte[7:0] & ByteCntEq1)
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
Broadcast <= #Tp 1'b1;
end
end
/trunk/rtl/verilog/eth_txethmac.v
43,6 → 43,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
164,7 → 174,7
 
 
 
assign ResetCollision = ~(StatePreamble | |StateData | StatePAD | StateFCS);
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
 
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
 
343,7 → 353,7
if(Reset)
MTxEn <= #Tp 1'b0;
else
MTxEn <= #Tp StatePreamble | |StateData | StatePAD | StateFCS | StateJam;
MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
 
 
373,7 → 383,7
if(Reset)
WillTransmit <= #Tp 1'b0;
else
WillTransmit <= #Tp StartPreamble | StatePreamble | |StateData | StatePAD | StateFCS | StateJam;
WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
 
 
435,7 → 445,7
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
 
assign Initialize_Crc = StateIdle | StatePreamble | |DlyCrcCnt;
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
 
 
// Connecting module Crc
/trunk/rtl/verilog/eth_txcounters.v
43,6 → 43,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
118,7 → 128,7
 
 
 
assign IncrementNibCnt = StateIPG | StatePreamble | |StateData & ~|DlyCrcCnt[2:0] | StatePAD
assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) & ~|DlyCrcCnt[2:0] | StatePAD
| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
 
 
/trunk/rtl/verilog/eth_transmitcontrol.v
41,6 → 41,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
224,7 → 234,7
if(ResetByteCnt)
ByteCnt <= #Tp 6'h0;
else
if(IncrementByteCnt & (~DlyCrcEn | DlyCrcEn & &DlyCrcCnt[1:0]))
if(IncrementByteCnt & (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0])))
ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
end
 
236,7 → 246,7
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
case(ByteCnt)
6'h0: if(~DlyCrcEn | DlyCrcEn & &DlyCrcCnt[1:0])
6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
else
MuxedCtrlData[7:0] = 8'h0;
/trunk/rtl/verilog/eth_macstatus.v
41,6 → 41,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
120,7 → 130,7
if(~MRxErr & MRxDV & RxStateIdle & ~Transmitting)
LatchedMRxErr <=#Tp 1'b0;
else
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | |RxStateData | RxStateIdle & ~Transmitting))
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
LatchedMRxErr <=#Tp 1'b1;
end
 
/trunk/rtl/verilog/eth_rxstatem.v
43,6 → 43,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
101,7 → 111,7
 
 
// Defining the next state
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | |StateData & (ByteCntEq0 | ByteCntGreat2));
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData) & (ByteCntEq0 | ByteCntGreat2));
 
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
 
/trunk/rtl/verilog/eth_txstatem.v
43,6 → 43,16
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
156,7 → 166,7
assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad & CrcEn | Pad & NibbleMinFl)
| ~Collision & StatePAD & NibbleMinFl;
 
assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | |StateData[1:0] | StatePAD | StateFCS);
assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
 
assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.