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/trunk/rtl/verilog/eth_defines.v
41,6 → 41,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
64,37 → 70,28
// Should be cleared for the ASIC implementation
 
 
// Address is {`ETHERNET_SPACE, REG_SPACE, 12'hx}
`define ETH_ETHERNET_SPACE 16'hf000 // Ethernet space is allocated from 0xF0000000 to 0xF000FFFF
`define ETH_REG_SPACE 4'h0 // Register space is allocated to 0xF0000000
`define ETH_BD_SPACE 4'h1 // Buffer descriptor space is allocated to 0xF0001000
`define ETH_TX_DATA 4'h2 // Tx data is written to address 0xF0002000. Since DMA is used, TX_DATA is not used in equations.
`define ETH_RX_DATA 4'h3 // Rx data is read from address 0xF0003000. Since DMA is used, RX_DATA is not used in equations.
 
`define ETH_MODER_ADR 6'h0 // 0x0
`define ETH_INT_SOURCE_ADR 6'h1 // 0x4
`define ETH_INT_MASK_ADR 6'h2 // 0x8
`define ETH_IPGT_ADR 6'h3 // 0xC
`define ETH_IPGR1_ADR 6'h4 // 0x10
`define ETH_IPGR2_ADR 6'h5 // 0x14
`define ETH_PACKETLEN_ADR 6'h6 // 0x18
`define ETH_COLLCONF_ADR 6'h7 // 0x1C
`define ETH_RX_BD_ADR_ADR 6'h8 // 0x20
`define ETH_CTRLMODER_ADR 6'h9 // 0x24
`define ETH_MIIMODER_ADR 6'hA // 0x28
`define ETH_MIICOMMAND_ADR 6'hB // 0x2C
`define ETH_MIIADDRESS_ADR 6'hC // 0x30
`define ETH_MIITX_DATA_ADR 6'hD // 0x34
`define ETH_MIIRX_DATA_ADR 6'hE // 0x38
`define ETH_MIISTATUS_ADR 6'hF // 0x3C
`define ETH_MAC_ADDR0_ADR 6'h10 // 0x40
`define ETH_MAC_ADDR1_ADR 6'h11 // 0x44
 
`define ETH_PACKET_SEND_ADR 32'h20 // Packet for TX are written to the address 0x20
 
`define ETH_MODER_ADR 6'h0
`define ETH_INT_SOURCE_ADR 6'h1
`define ETH_INT_MASK_ADR 6'h2
`define ETH_IPGT_ADR 6'h3
`define ETH_IPGR1_ADR 6'h4
`define ETH_IPGR2_ADR 6'h5
`define ETH_PACKETLEN_ADR 6'h6
`define ETH_COLLCONF_ADR 6'h7
`define ETH_RX_BD_ADR_ADR 6'h8
`define ETH_CTRLMODER_ADR 6'hA
`define ETH_MIIMODER_ADR 6'hB
`define ETH_MIICOMMAND_ADR 6'hC
`define ETH_MIIADDRESS_ADR 6'hD
`define ETH_MIITX_DATA_ADR 6'hE
`define ETH_MIIRX_DATA_ADR 6'hF
`define ETH_MIISTATUS_ADR 6'h10
`define ETH_MAC_ADDR0_ADR 6'h11
`define ETH_MAC_ADDR1_ADR 6'h12
 
 
 
`define ETH_MODER_DEF 32'h0000A000
`define ETH_INT_SOURCE_DEF 32'h00000000
`define ETH_INT_MASK_DEF 32'h00000000
/trunk/rtl/verilog/eth_wishbonedma.v
41,6 → 41,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.2 2001/08/08 08:28:21 mohor
// "else" was missing within the always block in file eth_wishbonedma.v.
//
74,8 → 80,8
WB_CLK_I, WB_RST_I, WB_DAT_I, WB_DAT_O,
 
// WISHBONE slave
WB_ADR_I, WB_SEL_I, WB_WE_I, WB_CYC_I, WB_STB_I, WB_ACK_O,
WB_REQ_O, WB_ACK_I, WB_ND_O, WB_RD_O,
WB_ADR_I, WB_SEL_I, WB_WE_I, WB_ACK_O,
WB_REQ_O, WB_ACK_I, WB_ND_O, WB_RD_O, BDCs,
 
//TX
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData, StatusIzTxEthMACModula,
88,7 → 94,10
// Register
r_TxEn, r_RxEn, r_RxBDAddress, r_DmaEn, RX_BD_ADR_Wr,
 
WillSendControlFrame, TxCtrlEndFrm
WillSendControlFrame, TxCtrlEndFrm,
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ
 
);
 
105,8 → 114,7
input [31:0] WB_ADR_I; // WISHBONE address input
input [3:0] WB_SEL_I; // WISHBONE byte select input
input WB_WE_I; // WISHBONE write enable input
input WB_CYC_I; // WISHBONE cycle input
input WB_STB_I; // WISHBONE strobe input
input BDCs; // Buffer descriptors are selected
output WB_ACK_O; // WISHBONE acknowledge output
 
// DMA
147,6 → 155,13
input r_DmaEn; // DMA enable
input RX_BD_ADR_Wr; // RxBDAddress written
 
// Interrupts
output TxB_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxF_IRQ;
output Busy_IRQ;
 
reg WB_REQ_O_RX;
reg WB_ND_O_TX; // New descriptor
reg WB_RD_O; // Restart descriptor
175,7 → 190,7
reg TxEndFrm_wbLatched;
 
reg [15:0] TxLength;
reg [15:0] TxStatus;
reg [31:0] TxStatus;
 
reg [15:0] RxStatus;
 
226,7 → 241,6
reg GotDataSync1;
reg GotDataSync2;
wire TPauseRqSync2;
//reg GotDataSync3;
wire GotDataSync3;
reg GotData;
reg SyncGetNewTxData_wb1;
234,15 → 248,12
reg SyncGetNewTxData_wb3;
reg TxDoneSync1;
reg TxDoneSync2;
//reg TxDoneSync3;
wire TxDoneSync3;
reg TxRetrySync1;
reg TxRetrySync2;
//reg TxRetrySync3;
wire TxRetrySync3;
reg TxAbortSync1;
reg TxAbortSync2;
//reg TxAbortSync3;
wire TxAbortSync3;
 
reg TxAbort_q;
261,17 → 272,14
reg Shifting_wb_Sync1;
reg Shifting_wb_Sync2;
reg LatchNow_wb;
//wire LatchNow_wb;
 
reg ShiftEndedSync1;
reg ShiftEndedSync2;
reg ShiftEndedSync3;
//reg ShiftEnded;
wire ShiftEnded;
 
reg RxStartFrmSync1;
reg RxStartFrmSync2;
//reg RxStartFrmSync3;
wire RxStartFrmSync3;
 
reg DMACycleFinishedTx_q;
321,7 → 329,10
wire ResetTxDataRead;
wire StartTxStatusWrite;
wire ResetTxStatusWrite;
 
wire TxIRQEn;
wire WrapTxStatusBit;
 
wire WrapRxStatusBit;
 
wire [1:0] TxValidBytes;
350,8 → 361,6
wire SetClearTxBDReady;
wire ResetClearTxBDReady;
 
wire AccessToBD;
 
wire ResetTxCtrlEndFrm_wb;
wire SetTxCtrlEndFrm_wb;
358,11 → 367,8
assign AccessToBD = WB_ADR_I[15:12] == `ETH_BD_SPACE;
assign DWord = &WB_SEL_I;
assign BDWe = DWord & WB_CYC_I & WB_STB_I & WB_WE_I & AccessToBD;
assign BDRead = DWord & WB_CYC_I & WB_STB_I & ~WB_WE_I & AccessToBD;
assign BDWe = BDCs & WB_WE_I;
assign BDRead = BDCs & ~WB_WE_I;
assign WB_ACK_O = BDWe | BDRead & BDRead_q; // ACK is delayed one clock because of BLOCKRAM properties when performing read
 
 
386,7 → 392,7
.WEA(BDWe), .CLKA(WB_CLK_I), .ENA(1'b1),
.RSTA(WB_RST_I), .DIB(BDDataIn[15:0]), .DOB(BDDataOut[15:0]),
.ADDRB(BDAddress[7:0]), .WEB(BDStatusWrite), .CLKB(WB_CLK_I),
.ENB(EnableRAM), .RSTB(WB_RST_I) );
.ENB(EnableRAM), .RSTB(WB_RST_I) );
RAMB4_S16_S16 RAM2 ( .DIA(WB_DAT_I[31:16]), .DOA(WB_BDDataOut[31:16]), .ADDRA(WB_ADR_I[9:2]),
.WEA(BDWe), .CLKA(WB_CLK_I), .ENA(1'b1),
.RSTA(WB_RST_I), .DIB(BDDataIn[31:16]), .DOB(BDDataOut[31:16]),
446,7 → 452,7
TxBDReady <=#Tp 1'b0;
else
if(TxEn & TxBDRead)
TxBDReady <=#Tp BDDataOut[15]; // TxBDReady is sampled only once at the beginning
TxBDReady <=#Tp BDDataOut[15]; // TxBDReady=BDDataOut[15] // TxBDReady is sampled only once at the beginning
else
if(TxDone & ~TxDone_q | TxAbort & ~TxAbort_q | TxRetry & ~TxRetry_q | ClearTxBDReady | TxPauseRq)
TxBDReady <=#Tp 1'b0;
463,7 → 469,7
else
if(TxEn & TxBDRead)
begin
TxPauseRq <=#Tp BDDataOut[13]; // Tx PAUSE request
TxPauseRq <=#Tp BDDataOut[9]; // Tx PAUSE request
end
else
TxPauseRq <=#Tp 1'b0;
500,7 → 506,7
if(WB_RST_I)
TxDataRead <=#Tp 1'b0;
else
if(StartTxDataRead)
if(StartTxDataRead & r_DmaEn)
TxDataRead <=#Tp 1'b1;
else
if(ResetTxDataRead)
508,7 → 514,7
end
 
// Requesting tx data from the DMA
assign WB_REQ_O[0] = TxDataRead & r_DmaEn;
assign WB_REQ_O[0] = TxDataRead;
assign DMACycleFinishedTx = WB_REQ_O[0] & WB_ACK_I[0] & TxBDReady;
 
 
577,10 → 583,10
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
if(WB_RST_I)
TxStatus <=#Tp 16'h0;
TxStatus <=#Tp 32'h0;
else
if(TxBDRead & TxEn)
TxStatus <=#Tp BDDataOut[15:0];
TxStatus <=#Tp BDDataOut;
end
 
 
733,12 → 739,53
 
// Bit 14 is used as a wrap bit. When active it indicates the last buffer descriptor in a row. After
// using this descriptor, first BD will be used again.
assign WrapTxStatusBit = TxStatus[14];
assign WrapRxStatusBit = RxStatus[14];
assign PerPacketCrcEn = RxStatus[13] & RxStatus[12];
assign PerPacketPad = RxStatus[11];
 
 
 
// TX
// bit 15 od tx je ready
// bit 14 od tx je interrupt (Tx buffer ali tx error bit se postavi v interrupt registru, ko se ta buffer odda)
// bit 13 od tx je wrap
// bit 12 od tx je pad
// bit 11 od tx je crc
// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
// bit 9 od tx je pause request (control frame)
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
// bit 8 od tx je defer indication
// bit 7 od tx je late collision
// bit 6 od tx je retransmittion limit
// bit 5 od tx je underrun
// bit 4 od tx je carrier sense lost
// bit [3:0] od tx je retry count
 
//assign TxBDReady = TxStatus[15]; // already used
assign TxIRQEn = TxStatus[14];
assign WrapTxStatusBit = TxStatus[13]; // ok povezan
assign PerPacketPad = TxStatus[12]; // ok povezan
assign PerPacketCrcEn = TxStatus[11] & TxStatus[10]; // When last is also set // ok povezan
//assign TxPauseRq = TxStatus[9]; // already used
 
 
 
// RX
// bit 15 od rx je empty
// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
// bit 13 od rx je wrap
// bit 12 od rx je reserved
// bit 11 od rx je reserved
// bit 10 od rx je last (crc se doda le ce je bit 11 in hkrati bit 10)
// bit 9 od rx je pause request (control frame)
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
// bit 8 od rx je defer indication
// bit 7 od rx je late collision
// bit 6 od rx je retransmittion limit
// bit 5 od rx je underrun
// bit 4 od rx je carrier sense lost
// bit [3:0] od rx je retry count
 
assign WrapRxStatusBit = RxStatus[13];
 
 
// Temporary Tx and Rx buffer descriptor address
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_RxBDAddress) | // Using first Rx BD
787,11 → 834,13
assign NewRxStatus[15:0] = {1'b0, WbWriteError, RxStatus[13:0]};
 
 
assign BDDataIn = TxStatusWrite ? {TxLength[15:0], StatusIzTxEthMACModula} : {RxLength, NewRxStatus};
//assign BDDataIn = TxStatusWrite ? {TxLength[15:0], StatusIzTxEthMACModula} : {RxLength, NewRxStatus};
assign BDDataIn = TxStatusWrite ? {TxStatus[31:9], 9'h0}
: {RxLength, NewRxStatus};
 
assign BDStatusWrite = TxStatusWrite | RxStatusWrite;
 
 
 
// Generating delayed signals
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
1540,7 → 1589,7
if(WB_RST_I)
WB_REQ_O_RX <=#Tp 1'b0;
else
if(LatchNow_wb & ~RxDataValid_wb)
if(LatchNow_wb & ~RxDataValid_wb & r_DmaEn)
WB_REQ_O_RX <=#Tp 1'b1;
else
if(DMACycleFinishedRx)
1548,7 → 1597,7
end
 
 
assign WB_REQ_O[1] = WB_REQ_O_RX & r_DmaEn;
assign WB_REQ_O[1] = WB_REQ_O_RX;
assign DMACycleFinishedRx = WB_REQ_O[1] & WB_ACK_I[1];
 
 
1605,5 → 1654,14
RxEndFrm_wb <=#Tp 1'b0;
end
 
 
// Interrupts
assign TxB_IRQ = 1'b0;
assign TxE_IRQ = 1'b0;
assign RxB_IRQ = 1'b0;
assign RxF_IRQ = 1'b0;
assign Busy_IRQ = 1'b0;
 
 
endmodule
 
/trunk/rtl/verilog/eth_top.v
41,6 → 41,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.2 2001/08/15 14:03:59 mohor
// Signal names changed on the top level for easier pad insertion (ASIC).
//
85,9 → 91,11
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
// MIIM
mdc_pad_o, md_pad_i, md_pad_o, md_padoen_o
mdc_pad_o, md_pad_i, md_pad_o, md_padoen_o,
 
int_o
 
 
);
 
 
117,26 → 125,27
 
// Tx
input mtx_clk_pad_i; // Transmit clock (from PHY)
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
output mtxen_pad_o; // Transmit enable (to PHY)
output mtxerr_pad_o; // Transmit error (to PHY)
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
output mtxen_pad_o; // Transmit enable (to PHY)
output mtxerr_pad_o; // Transmit error (to PHY)
 
// Rx
input mrx_clk_pad_i; // Receive clock (from PHY)
input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
input mrxdv_pad_i; // Receive data valid (from PHY)
input mrxerr_pad_i; // Receive data error (from PHY)
input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
input mrxdv_pad_i; // Receive data valid (from PHY)
input mrxerr_pad_i; // Receive data error (from PHY)
 
// Common Tx and Rx
input mcoll_pad_i; // Collision (from PHY)
input mcrs_pad_i; // Carrier sense (from PHY)
input mcoll_pad_i; // Collision (from PHY)
input mcrs_pad_i; // Carrier sense (from PHY)
 
// MII Management interface
input md_pad_i; // MII data input (from I/O cell)
output mdc_pad_o; // MII Management data clock (to PHY)
output md_pad_o; // MII data output (to I/O cell)
output md_padoen_o; // MII data output enable (to I/O cell)
input md_pad_i; // MII data input (from I/O cell)
output mdc_pad_o; // MII Management data clock (to PHY)
output md_pad_o; // MII data output (to I/O cell)
output md_padoen_o; // MII data output enable (to I/O cell)
 
output int_o; // Interrupt output
 
wire [7:0] r_ClkDiv;
wire r_MiiNoPre;
217,26 → 226,23
wire r_TxFlow; // Tx flow control enable
wire r_IFG; // Minimum interframe gap for incoming packets
 
wire EthAddMatch;
wire WB_STB_I_eth;
wire WB_CYC_I_eth;
wire TxB_IRQ; // Interrupt Tx Buffer
wire TxE_IRQ; // Interrupt Tx Error
wire RxB_IRQ; // Interrupt Rx Buffer
wire RxF_IRQ; // Interrupt Rx Frame
wire Busy_IRQ; // Interrupt Busy (lack of buffers)
 
wire DWord;
wire RegAck;
wire BDAck;
wire [31:0] DMA_WB_DAT_O; // wb_dat_o that comes from the WishboneDMA module
wire BDCs; // Buffer descriptor CS
 
 
 
assign EthAddMatch = wb_adr_i[31:16] == `ETH_ETHERNET_SPACE;
assign WB_STB_I_eth = wb_stb_i & EthAddMatch;
assign WB_CYC_I_eth = wb_stb_i & EthAddMatch;
 
assign wb_err_o = wb_stb_i & wb_cyc_i & EthAddMatch & ~DWord;
assign DWord = &wb_sel_i;
assign RegCs = wb_stb_i & wb_cyc_i & DWord & EthAddMatch & (wb_adr_i[15:12] == `ETH_REG_SPACE);
assign RegAck = RegCs;
assign wb_ack_o = RegAck | BDAck;
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[17] & ~wb_adr_i[16];
assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[17] & wb_adr_i[16];
assign wb_ack_o = RegCs | BDAck;
assign wb_err_o = wb_stb_i & wb_cyc_i & ~DWord;
 
 
// Selecting the WISHBONE output data
254,10 → 260,9
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
.r_IFG(r_IFG), .r_Pro(), .r_Iam(),
.r_Bro(), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
.r_RxEn(r_RxEn), .Busy_IRQ(), .RxF_IRQ(),
.RxB_IRQ(), .TxE_IRQ(), .TxB_IRQ(),
.Busy_MASK(), .RxF_MASK(), .RxB_MASK(),
.TxE_MASK(), .TxB_MASK(), .r_IPGT(r_IPGT),
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ),
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.r_IPGT(r_IPGT),
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
267,7 → 272,7
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
.r_RxBDAddress(r_RxBDAddress), .RX_BD_ADR_Wr(RX_BD_ADR_Wr)
.r_RxBDAddress(r_RxBDAddress), .RX_BD_ADR_Wr(RX_BD_ADR_Wr), .int_o(int_o)
);
 
 
343,7 → 348,7
// Connecting TxEthMAC
eth_txethmac txethmac1
(
.MTxClk(mtx_clk_pad_i), .Reset(r_Rst), .CarrierSense(TxCarrierSense),
.MTxClk(mtx_clk_pad_i), .Reset(r_Rst), .CarrierSense(TxCarrierSense),
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
375,7 → 380,7
// Connecting RxEthMAC
eth_rxethmac rxethmac1
(
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(r_Rst),
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
479,12 → 484,12
 
// WISHBONE slave
.WB_ADR_I(wb_adr_i), .WB_SEL_I(wb_sel_i), .WB_WE_I(wb_we_i),
.WB_CYC_I(WB_CYC_I_eth), .WB_STB_I(WB_STB_I_eth), .WB_ACK_O(BDAck),
.BDCs(BDCs), .WB_ACK_O(BDAck),
.WB_REQ_O(wb_req_o), .WB_ACK_I(wb_ack_i), .WB_ND_O(wb_nd_o),
.WB_RD_O(wb_rd_o),
 
//TX
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
.TxUsedData(TxUsedData), .TxData(TxData), .StatusIzTxEthMACModula(16'h0),
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
.TxDone(TxDone), .TPauseRq(TPauseRq), .TxPauseTV(TxPauseTV),
496,8 → 501,11
.r_DmaEn(r_DmaEn), .RX_BD_ADR_Wr(RX_BD_ADR_Wr),
 
//RX
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm)
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ)
 
);
 
 
/trunk/rtl/verilog/eth_rxstatem.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
115,7 → 118,8
 
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
 
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting);
//assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting);
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
 
assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
 
/trunk/rtl/verilog/eth_registers.v
41,6 → 41,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
70,14 → 76,14
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, r_DmaEn,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn, Busy_IRQ, RxF_IRQ,
RxB_IRQ, TxE_IRQ, TxB_IRQ, Busy_MASK, RxF_MASK, RxB_MASK, TxE_MASK,
TxB_MASK, r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
LinkFail, r_MAC, WCtrlDataStart, RStatStart,
UpdateMIIRX_DATAReg, Prsd, r_RxBDAddress, RX_BD_ADR_Wr
UpdateMIIRX_DATAReg, Prsd, r_RxBDAddress, RX_BD_ADR_Wr, int_o
);
 
parameter Tp = 1;
118,18 → 124,12
output r_TxEn;
output r_RxEn;
 
output Busy_IRQ;
output RxF_IRQ;
output RxB_IRQ;
output TxE_IRQ;
output TxB_IRQ;
input TxB_IRQ;
input TxE_IRQ;
input RxB_IRQ;
input RxF_IRQ;
input Busy_IRQ;
 
output Busy_MASK;
output RxF_MASK;
output RxB_MASK;
output TxE_MASK;
output TxB_MASK;
 
output [6:0] r_IPGT;
 
output [6:0] r_IPGR1;
157,7 → 157,7
output [4:0] r_RGAD;
output [4:0] r_FIAD;
 
output [15:0] r_CtrlData;
output [15:0]r_CtrlData;
 
 
input NValid_stat;
164,39 → 164,42
input Busy_stat;
input LinkFail;
 
output [47:0] r_MAC;
 
output [47:0]r_MAC;
output [7:0] r_RxBDAddress;
 
output RX_BD_ADR_Wr;
output int_o;
 
reg irq_txb;
reg irq_txe;
reg irq_rxb;
reg irq_rxf;
reg irq_busy;
 
 
wire Write = Cs & Rw;
wire Read = Cs & ~Rw;
 
wire MODER_Wr = (Address == `ETH_MODER_ADR) & Write;
wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR) & Write;
wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR) & Write;
wire IPGT_Wr = (Address == `ETH_IPGT_ADR) & Write;
wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR) & Write;
wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR) & Write;
wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR) & Write;
wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR) & Write;
wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write;
wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR ) & Write;
wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR ) & Write;
wire IPGT_Wr = (Address == `ETH_IPGT_ADR ) & Write;
wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR ) & Write;
wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR ) & Write;
wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR ) & Write;
wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR ) & Write;
wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR ) & Write;
wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR ) & Write;
wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR ) & Write;
wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR ) & Write;
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write;
wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write;
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
assign RX_BD_ADR_Wr = (Address == `ETH_RX_BD_ADR_ADR ) & Write;
 
wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR) & Write;
wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR) & Write;
wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR) & Write;
wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR) & Write;
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR) & Write;
wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR) & Write;
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR) & Write;
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR) & Write;
assign RX_BD_ADR_Wr = (Address == `ETH_RX_BD_ADR_ADR) & Write;
 
 
 
wire [31:0] MODEROut;
wire [31:0] INT_SOURCEOut;
wire [31:0] INT_MASKOut;
217,7 → 220,6
wire [31:0] RX_BD_ADROut;
 
eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
eth_register #(32) INT_SOURCE (.DataIn(DataIn), .DataOut(INT_SOURCEOut), .Write(INT_SOURCE_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_SOURCE_DEF));
eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
332,18 → 334,6
assign r_TxEn = MODEROut[1];
assign r_RxEn = MODEROut[0];
 
assign Busy_IRQ = INT_SOURCEOut[4];
assign RxF_IRQ = INT_SOURCEOut[3];
assign RxB_IRQ = INT_SOURCEOut[2];
assign TxE_IRQ = INT_SOURCEOut[1];
assign TxB_IRQ = INT_SOURCEOut[0];
 
assign Busy_MASK = INT_MASKOut[4];
assign RxF_MASK = INT_MASKOut[3];
assign RxB_MASK = INT_MASKOut[2];
assign TxE_MASK = INT_MASKOut[1];
assign TxB_MASK = INT_MASKOut[0];
 
assign r_IPGT[6:0] = IPGTOut[6:0];
 
assign r_IPGR1[6:0] = IPGR1Out[6:0];
387,4 → 377,74
assign r_RxBDAddress[7:0] = RX_BD_ADROut[7:0];
 
 
// Interrupt generation
 
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txb <= 1'b0;
else
if(TxB_IRQ & INT_MASKOut[0])
irq_txb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[0])
irq_txb <= #Tp 1'b0;
end
 
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txe <= 1'b0;
else
if(TxE_IRQ & INT_MASKOut[1])
irq_txe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[1])
irq_txe <= #Tp 1'b0;
end
 
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxb <= 1'b0;
else
if(RxB_IRQ & INT_MASKOut[2])
irq_rxb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[2])
irq_rxb <= #Tp 1'b0;
end
 
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxf <= 1'b0;
else
if(RxF_IRQ & INT_MASKOut[3])
irq_rxf <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[3])
irq_rxf <= #Tp 1'b0;
end
 
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_busy <= 1'b0;
else
if(Busy_IRQ & INT_MASKOut[4])
irq_busy <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[4])
irq_busy <= #Tp 1'b0;
end
 
// Generating interrupt signal
assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxf | irq_busy;
 
// For reading interrupt status
assign INT_SOURCEOut = {28'h0, irq_busy, irq_rxf, irq_rxb, irq_txe, irq_txb};
 
 
 
endmodule

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